1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, MemExuOutput} 26import xiangshan.cache._ 27import xiangshan.cache.{DCacheWordIO, DCacheLineIO, MemoryOpConstants} 28import xiangshan.cache.mmu.{TlbRequestIO, TlbHintIO} 29import xiangshan.mem._ 30import xiangshan.backend._ 31import xiangshan.backend.rob.RobLsqIO 32import coupledL2.{CMOReq, CMOResp} 33import xiangshan.backend.fu.FuType 34 35class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 36 val isStore = Input(Bool()) 37 val vaddr = Output(UInt(XLEN.W)) 38 val vstart = Output(UInt((log2Up(VLEN) + 1).W)) 39 val vl = Output(UInt((log2Up(VLEN) + 1).W)) 40 val gpaddr = Output(UInt(XLEN.W)) 41 val isForVSnonLeafPTE = Output(Bool()) 42} 43 44class FwdEntry extends Bundle { 45 val validFast = Bool() // validFast is generated the same cycle with query 46 val valid = Bool() // valid is generated 1 cycle after query request 47 val data = UInt(8.W) // data is generated 1 cycle after query request 48} 49 50// inflight miss block reqs 51class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 52 val block_addr = UInt(PAddrBits.W) 53 val valid = Bool() 54} 55 56class LsqEnqIO(implicit p: Parameters) extends MemBlockBundle { 57 val canAccept = Output(Bool()) 58 val needAlloc = Vec(LSQEnqWidth, Input(UInt(2.W))) 59 val req = Vec(LSQEnqWidth, Flipped(ValidIO(new DynInst))) 60 val iqAccept = Input(Vec(LSQEnqWidth, Bool())) 61 val resp = Vec(LSQEnqWidth, Output(new LSIdx)) 62} 63 64// Load / Store Queue Wrapper for XiangShan Out of Order LSU 65class LsqWrapper(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasPerfEvents { 66 val io = IO(new Bundle() { 67 val hartId = Input(UInt(hartIdLen.W)) 68 val brqRedirect = Flipped(ValidIO(new Redirect)) 69 val stvecFeedback = Vec(VecStorePipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO))) 70 val ldvecFeedback = Vec(VecLoadPipelineWidth, Flipped(ValidIO(new FeedbackToLsqIO))) 71 val enq = new LsqEnqIO 72 val ldu = new Bundle() { 73 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 74 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 75 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 76 } 77 val sta = new Bundle() { 78 val storeMaskIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreMaskBundle))) // from store_s0, store mask, send to sq from rs 79 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 80 val storeAddrInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) // from store_s2 81 } 82 val std = new Bundle() { 83 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput(isVector = true)))) // from store_s0, store data, send to sq from rs 84 } 85 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 86 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 87 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 88 val sbuffer = Vec(EnsbufferWidth, Decoupled(new DCacheWordReqWithVaddrAndPfFlag)) 89 val sbufferVecDifftestInfo = Vec(EnsbufferWidth, Decoupled(new DynInst)) // The vector store difftest needs is 90 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 91 val rob = Flipped(new RobLsqIO) 92 val nuke_rollback = Vec(StorePipelineWidth, Output(Valid(new Redirect))) 93 val nack_rollback = Output(Valid(new Redirect)) 94 val release = Flipped(Valid(new Release)) 95 // val refill = Flipped(Valid(new Refill)) 96 val tl_d_channel = Input(new DcacheToLduForwardIO) 97 val maControl = Flipped(new StoreMaBufToSqControlIO) 98 val uncacheOutstanding = Input(Bool()) 99 val uncache = new UncacheWordIO 100 val mmioStout = DecoupledIO(new MemExuOutput) // writeback uncached store 101 // TODO: implement vector store 102 val vecmmioStout = DecoupledIO(new MemExuOutput(isVector = true)) // vec writeback uncached store 103 val sqEmpty = Output(Bool()) 104 val lq_rep_full = Output(Bool()) 105 val sqFull = Output(Bool()) 106 val lqFull = Output(Bool()) 107 val sqCancelCnt = Output(UInt(log2Up(StoreQueueSize+1).W)) 108 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 109 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 110 val sqDeq = Output(UInt(log2Ceil(EnsbufferWidth + 1).W)) 111 val lqCanAccept = Output(Bool()) 112 val sqCanAccept = Output(Bool()) 113 val lqDeqPtr = Output(new LqPtr) 114 val sqDeqPtr = Output(new SqPtr) 115 val exceptionAddr = new ExceptionAddrIO 116 val flushFrmMaBuf = Input(Bool()) 117 val issuePtrExt = Output(new SqPtr) 118 val l2_hint = Input(Valid(new L2ToL1Hint())) 119 val tlb_hint = Flipped(new TlbHintIO) 120 val cmoOpReq = DecoupledIO(new CMOReq) 121 val cmoOpResp = Flipped(DecoupledIO(new CMOResp)) 122 val flushSbuffer = new SbufferFlushBundle 123 val force_write = Output(Bool()) 124 val lqEmpty = Output(Bool()) 125 126 // top-down 127 val debugTopDown = new LoadQueueTopDownIO 128 }) 129 130 val loadQueue = Module(new LoadQueue) 131 val storeQueue = Module(new StoreQueue) 132 133 storeQueue.io.hartId := io.hartId 134 storeQueue.io.uncacheOutstanding := io.uncacheOutstanding 135 136 137 dontTouch(loadQueue.io.tlbReplayDelayCycleCtrl) 138 // Todo: imm 139 val tlbReplayDelayCycleCtrl = WireInit(VecInit(Seq(14.U(ReSelectLen.W), 0.U(ReSelectLen.W), 125.U(ReSelectLen.W), 0.U(ReSelectLen.W)))) 140 loadQueue.io.tlbReplayDelayCycleCtrl := tlbReplayDelayCycleCtrl 141 142 // io.enq logic 143 // LSQ: send out canAccept when both load queue and store queue are ready 144 // Dispatch: send instructions to LSQ only when they are ready 145 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 146 io.lqCanAccept := loadQueue.io.enq.canAccept 147 io.sqCanAccept := storeQueue.io.enq.canAccept 148 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 149 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 150 io.lqDeqPtr := loadQueue.io.lqDeqPtr 151 io.sqDeqPtr := storeQueue.io.sqDeqPtr 152 for (i <- io.enq.req.indices) { 153 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 154 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 155 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 156 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 157 158 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 159 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 160 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 161 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 162 163 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 164 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 165 } 166 167 // store queue wiring 168 storeQueue.io.brqRedirect <> io.brqRedirect 169 storeQueue.io.vecFeedback <> io.stvecFeedback 170 storeQueue.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 171 storeQueue.io.storeAddrInRe <> io.sta.storeAddrInRe // from store_s2 172 storeQueue.io.storeDataIn <> io.std.storeDataIn // from store_s0 173 storeQueue.io.storeMaskIn <> io.sta.storeMaskIn // from store_s0 174 storeQueue.io.sbuffer <> io.sbuffer 175 storeQueue.io.sbufferVecDifftestInfo <> io.sbufferVecDifftestInfo 176 storeQueue.io.mmioStout <> io.mmioStout 177 storeQueue.io.vecmmioStout <> io.vecmmioStout 178 storeQueue.io.rob <> io.rob 179 storeQueue.io.exceptionAddr.isStore := DontCare 180 storeQueue.io.sqCancelCnt <> io.sqCancelCnt 181 storeQueue.io.sqDeq <> io.sqDeq 182 storeQueue.io.sqEmpty <> io.sqEmpty 183 storeQueue.io.sqFull <> io.sqFull 184 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 185 storeQueue.io.force_write <> io.force_write 186 storeQueue.io.cmoOpReq <> io.cmoOpReq 187 storeQueue.io.cmoOpResp <> io.cmoOpResp 188 storeQueue.io.flushSbuffer <> io.flushSbuffer 189 storeQueue.io.maControl <> io.maControl 190 191 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 192 193 // load queue wiring 194 loadQueue.io.redirect <> io.brqRedirect 195 loadQueue.io.vecFeedback <> io.ldvecFeedback 196 loadQueue.io.ldu <> io.ldu 197 loadQueue.io.ldout <> io.ldout 198 loadQueue.io.ld_raw_data <> io.ld_raw_data 199 loadQueue.io.rob <> io.rob 200 loadQueue.io.nuke_rollback <> io.nuke_rollback 201 loadQueue.io.nack_rollback <> io.nack_rollback 202 loadQueue.io.replay <> io.replay 203 // loadQueue.io.refill <> io.refill 204 loadQueue.io.tl_d_channel <> io.tl_d_channel 205 loadQueue.io.release <> io.release 206 loadQueue.io.exceptionAddr.isStore := DontCare 207 loadQueue.io.flushFrmMaBuf := io.flushFrmMaBuf 208 loadQueue.io.lqCancelCnt <> io.lqCancelCnt 209 loadQueue.io.sq.stAddrReadySqPtr <> storeQueue.io.stAddrReadySqPtr 210 loadQueue.io.sq.stAddrReadyVec <> storeQueue.io.stAddrReadyVec 211 loadQueue.io.sq.stDataReadySqPtr <> storeQueue.io.stDataReadySqPtr 212 loadQueue.io.sq.stDataReadyVec <> storeQueue.io.stDataReadyVec 213 loadQueue.io.sq.stIssuePtr <> storeQueue.io.stIssuePtr 214 loadQueue.io.sq.sqEmpty <> storeQueue.io.sqEmpty 215 loadQueue.io.sta.storeAddrIn <> io.sta.storeAddrIn // store_s1 216 loadQueue.io.std.storeDataIn <> io.std.storeDataIn // store_s0 217 loadQueue.io.lqFull <> io.lqFull 218 loadQueue.io.lq_rep_full <> io.lq_rep_full 219 loadQueue.io.lqDeq <> io.lqDeq 220 loadQueue.io.l2_hint <> io.l2_hint 221 loadQueue.io.tlb_hint <> io.tlb_hint 222 loadQueue.io.lqEmpty <> io.lqEmpty 223 224 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 225 // s0: commit 226 // s1: exception find 227 // s2: exception triggered 228 // s3: ptr updated & new address 229 // address will be used at the next cycle after exception is triggered 230 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 231 io.exceptionAddr.vstart := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vstart, loadQueue.io.exceptionAddr.vstart) 232 io.exceptionAddr.vl := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vl, loadQueue.io.exceptionAddr.vl) 233 io.exceptionAddr.gpaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.gpaddr, loadQueue.io.exceptionAddr.gpaddr) 234 io.exceptionAddr.isForVSnonLeafPTE:= Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.isForVSnonLeafPTE, loadQueue.io.exceptionAddr.isForVSnonLeafPTE) 235 io.issuePtrExt := storeQueue.io.stAddrReadySqPtr 236 237 // naive uncache arbiter 238 val s_idle :: s_load :: s_store :: Nil = Enum(3) 239 val pendingstate = RegInit(s_idle) 240 241 switch(pendingstate){ 242 is(s_idle){ 243 when(io.uncache.req.fire){ 244 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, 245 Mux(io.uncacheOutstanding, s_idle, s_store)) 246 } 247 } 248 is(s_load){ 249 when(io.uncache.resp.fire){ 250 pendingstate := s_idle 251 } 252 } 253 is(s_store){ 254 when(io.uncache.resp.fire){ 255 pendingstate := s_idle 256 } 257 } 258 } 259 260 loadQueue.io.uncache := DontCare 261 storeQueue.io.uncache := DontCare 262 loadQueue.io.uncache.req.ready := false.B 263 storeQueue.io.uncache.req.ready := false.B 264 loadQueue.io.uncache.resp.valid := false.B 265 storeQueue.io.uncache.resp.valid := false.B 266 when(loadQueue.io.uncache.req.valid){ 267 io.uncache.req <> loadQueue.io.uncache.req 268 }.otherwise{ 269 io.uncache.req <> storeQueue.io.uncache.req 270 } 271 when (io.uncacheOutstanding) { 272 io.uncache.resp <> loadQueue.io.uncache.resp 273 } .otherwise { 274 when(pendingstate === s_load){ 275 io.uncache.resp <> loadQueue.io.uncache.resp 276 }.otherwise{ 277 io.uncache.resp <> storeQueue.io.uncache.resp 278 } 279 } 280 281 loadQueue.io.debugTopDown <> io.debugTopDown 282 283 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 284 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 285 when (!io.uncacheOutstanding) { 286 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 287 } 288 289 290 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) 291 generatePerfEvent() 292} 293 294class LsqEnqCtrl(implicit p: Parameters) extends XSModule 295 with HasVLSUParameters { 296 val io = IO(new Bundle { 297 val redirect = Flipped(ValidIO(new Redirect)) 298 // to dispatch 299 val enq = new LsqEnqIO 300 // from `memBlock.io.lqDeq 301 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 302 // from `memBlock.io.sqDeq` 303 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 304 // from/tp lsq 305 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 306 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 307 val lqFreeCount = Output(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 308 val sqFreeCount = Output(UInt(log2Up(StoreQueueSize + 1).W)) 309 val enqLsq = Flipped(new LsqEnqIO) 310 }) 311 312 val lqPtr = RegInit(0.U.asTypeOf(new LqPtr)) 313 val sqPtr = RegInit(0.U.asTypeOf(new SqPtr)) 314 val lqCounter = RegInit(VirtualLoadQueueSize.U(log2Up(VirtualLoadQueueSize + 1).W)) 315 val sqCounter = RegInit(StoreQueueSize.U(log2Up(StoreQueueSize + 1).W)) 316 val canAccept = RegInit(false.B) 317 318 val blockVec = io.enq.iqAccept.map(!_) :+ true.B 319 val numLsElem = io.enq.req.map(_.bits.numLsElem) 320 val needEnqLoadQueue = VecInit(io.enq.req.map(x => FuType.isLoad(x.bits.fuType) || FuType.isVNonsegLoad(x.bits.fuType))) 321 val needEnqStoreQueue = VecInit(io.enq.req.map(x => FuType.isStore(x.bits.fuType) || FuType.isVNonsegStore(x.bits.fuType))) 322 val loadQueueElem = needEnqLoadQueue.zip(numLsElem).map(x => Mux(x._1, x._2, 0.U)) 323 val storeQueueElem = needEnqStoreQueue.zip(numLsElem).map(x => Mux(x._1, x._2, 0.U)) 324 val loadFlowPopCount = 0.U +: loadQueueElem.zipWithIndex.map{ case (l, i) => 325 loadQueueElem.take(i + 1).reduce(_ + _) 326 } 327 val storeFlowPopCount = 0.U +: storeQueueElem.zipWithIndex.map { case (s, i) => 328 storeQueueElem.take(i + 1).reduce(_ + _) 329 } 330 val lqAllocNumber = PriorityMux(blockVec.zip(loadFlowPopCount)) 331 val sqAllocNumber = PriorityMux(blockVec.zip(storeFlowPopCount)) 332 333 io.lqFreeCount := lqCounter 334 io.sqFreeCount := sqCounter 335 // How to update ptr and counter: 336 // (1) by default, updated according to enq/commit 337 // (2) when redirect and dispatch queue is empty, update according to lsq 338 val t1_redirect = RegNext(io.redirect.valid) 339 val t2_redirect = RegNext(t1_redirect) 340 val t2_update = t2_redirect && !VecInit(io.enq.needAlloc.map(_.orR)).asUInt.orR 341 val t3_update = RegNext(t2_update) 342 val t3_lqCancelCnt = GatedRegNext(io.lqCancelCnt) 343 val t3_sqCancelCnt = GatedRegNext(io.sqCancelCnt) 344 when (t3_update) { 345 lqPtr := lqPtr - t3_lqCancelCnt 346 lqCounter := lqCounter + io.lcommit + t3_lqCancelCnt 347 sqPtr := sqPtr - t3_sqCancelCnt 348 sqCounter := sqCounter + io.scommit + t3_sqCancelCnt 349 }.elsewhen (!io.redirect.valid && io.enq.canAccept) { 350 lqPtr := lqPtr + lqAllocNumber 351 lqCounter := lqCounter + io.lcommit - lqAllocNumber 352 sqPtr := sqPtr + sqAllocNumber 353 sqCounter := sqCounter + io.scommit - sqAllocNumber 354 }.otherwise { 355 lqCounter := lqCounter + io.lcommit 356 sqCounter := sqCounter + io.scommit 357 } 358 359 360 //TODO MaxAllocate and width of lqOffset/sqOffset needs to be discussed 361 val lqMaxAllocate = LSQLdEnqWidth 362 val sqMaxAllocate = LSQStEnqWidth 363 val maxAllocate = lqMaxAllocate max sqMaxAllocate 364 val ldCanAccept = lqCounter >= lqAllocNumber +& lqMaxAllocate.U 365 val sqCanAccept = sqCounter >= sqAllocNumber +& sqMaxAllocate.U 366 // It is possible that t3_update and enq are true at the same clock cycle. 367 // For example, if redirect.valid lasts more than one clock cycle, 368 // after the last redirect, new instructions may enter but previously redirect has not been resolved (updated according to the cancel count from LSQ). 369 // To solve the issue easily, we block enqueue when t3_update, which is RegNext(t2_update). 370 io.enq.canAccept := RegNext(ldCanAccept && sqCanAccept && !t2_update) 371 val lqOffset = Wire(Vec(io.enq.resp.length, UInt(lqPtr.value.getWidth.W))) 372 val sqOffset = Wire(Vec(io.enq.resp.length, UInt(sqPtr.value.getWidth.W))) 373 for ((resp, i) <- io.enq.resp.zipWithIndex) { 374 lqOffset(i) := loadFlowPopCount(i) 375 resp.lqIdx := lqPtr + lqOffset(i) 376 sqOffset(i) := storeFlowPopCount(i) 377 resp.sqIdx := sqPtr + sqOffset(i) 378 } 379 380 io.enqLsq.needAlloc := RegNext(io.enq.needAlloc) 381 io.enqLsq.iqAccept := RegNext(io.enq.iqAccept) 382 io.enqLsq.req.zip(io.enq.req).zip(io.enq.resp).foreach{ case ((toLsq, enq), resp) => 383 val do_enq = enq.valid && !io.redirect.valid && io.enq.canAccept 384 toLsq.valid := RegNext(do_enq) 385 toLsq.bits := RegEnable(enq.bits, do_enq) 386 toLsq.bits.lqIdx := RegEnable(resp.lqIdx, do_enq) 387 toLsq.bits.sqIdx := RegEnable(resp.sqIdx, do_enq) 388 } 389 390}