1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.mem 19 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utility._ 25import utils._ 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, MemExuInput} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.cache._ 30import xiangshan.backend.fu.FenceToSbuffer 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.mem.prefetch.PrefetchReqBundle 33import math._ 34 35object genWmask { 36 def apply(addr: UInt, sizeEncode: UInt): UInt = { 37 (LookupTree(sizeEncode, List( 38 "b00".U -> 0x1.U, //0001 << addr(2:0) 39 "b01".U -> 0x3.U, //0011 40 "b10".U -> 0xf.U, //1111 41 "b11".U -> 0xff.U //11111111 42 )) << addr(2, 0)).asUInt 43 } 44} 45 46object genVWmask { 47 def apply(addr: UInt, sizeEncode: UInt): UInt = { 48 (LookupTree(sizeEncode, List( 49 "b00".U -> 0x1.U, //0001 << addr(2:0) 50 "b01".U -> 0x3.U, //0011 51 "b10".U -> 0xf.U, //1111 52 "b11".U -> 0xff.U //11111111 53 )) << addr(3, 0)).asUInt 54 } 55} 56 57object genWdata { 58 def apply(data: UInt, sizeEncode: UInt): UInt = { 59 LookupTree(sizeEncode, List( 60 "b00".U -> Fill(16, data(7, 0)), 61 "b01".U -> Fill(8, data(15, 0)), 62 "b10".U -> Fill(4, data(31, 0)), 63 "b11".U -> Fill(2, data(63,0)) 64 )) 65 } 66} 67 68object shiftDataToLow { 69 def apply(addr: UInt,data : UInt): UInt = { 70 Mux(addr(3), (data >> 64).asUInt,data) 71 } 72} 73object shiftMaskToLow { 74 def apply(addr: UInt,mask: UInt): UInt = { 75 Mux(addr(3),(mask >> 8).asUInt,mask) 76 } 77} 78 79class LsPipelineBundle(implicit p: Parameters) extends XSBundle 80 with HasDCacheParameters 81 with HasVLSUParameters { 82 val uop = new DynInst 83 val vaddr = UInt(VAddrBits.W) 84 // For exception vaddr generate 85 val fullva = UInt(XLEN.W) 86 val vaNeedExt = Bool() 87 val isHyper = Bool() 88 val paddr = UInt(PAddrBits.W) 89 val gpaddr = UInt(XLEN.W) 90 val isForVSnonLeafPTE = Bool() 91 // val func = UInt(6.W) 92 val mask = UInt((VLEN/8).W) 93 val data = UInt((VLEN+1).W) 94 val wlineflag = Bool() // store write the whole cache line 95 96 val miss = Bool() 97 val tlbMiss = Bool() 98 val ptwBack = Bool() 99 val af = Bool() 100 val mmio = Bool() 101 val atomic = Bool() 102 103 val forwardMask = Vec(VLEN/8, Bool()) 104 val forwardData = Vec(VLEN/8, UInt(8.W)) 105 106 // prefetch 107 val isPrefetch = Bool() 108 val isHWPrefetch = Bool() 109 def isSWPrefetch = isPrefetch && !isHWPrefetch 110 111 // misalignBuffer 112 val isFrmMisAlignBuf = Bool() 113 114 // vector 115 val isvec = Bool() 116 val isLastElem = Bool() 117 val is128bit = Bool() 118 val uop_unit_stride_fof = Bool() 119 val usSecondInv = Bool() 120 val elemIdx = UInt(elemIdxBits.W) 121 val alignedType = UInt(alignTypeBits.W) 122 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 123 // val rob_idx_valid = Vec(2,Bool()) 124 // val inner_idx = Vec(2,UInt(3.W)) 125 // val rob_idx = Vec(2,new RobPtr) 126 val reg_offset = UInt(vOffsetBits.W) 127 val elemIdxInsideVd = UInt(elemIdxBits.W) 128 // val offset = Vec(2,UInt(4.W)) 129 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 130 val is_first_ele = Bool() 131 val vecBaseVaddr = UInt(VAddrBits.W) 132 val vecVaddrOffset = UInt(VAddrBits.W) 133 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 134 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 135 136 // For debug usage 137 val isFirstIssue = Bool() 138 val hasROBEntry = Bool() 139 140 // For load replay 141 val isLoadReplay = Bool() 142 val isFastPath = Bool() 143 val isFastReplay = Bool() 144 val replayCarry = new ReplayCarry(nWays) 145 146 // For dcache miss load 147 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 148 val handledByMSHR = Bool() 149 val replacementUpdated = Bool() 150 val missDbUpdated = Bool() 151 152 val forward_tlDchannel = Bool() 153 val dcacheRequireReplay = Bool() 154 val delayedLoadError = Bool() 155 val lateKill = Bool() 156 val feedbacked = Bool() 157 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 158 // loadQueueReplay index. 159 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 160 // hardware prefetch and fast replay no need to query tlb 161 val tlbNoQuery = Bool() 162} 163 164class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 165 val meta_prefetch = UInt(L1PfSourceBits.W) 166 val meta_access = Bool() 167 168 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 169 if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 170 if (latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 171 if (latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 172 if (latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 173 if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 174 if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 175 if (latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 176 if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask 177 if (latch) data := RegEnable(input.data, enable) else data := input.data 178 if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop 179 if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 180 if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss 181 if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 182 if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 183 if (latch) af := RegEnable(input.af, enable) else af := input.af 184 if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 185 if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 186 if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 187 if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 188 if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 189 if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 190 if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 191 if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 192 if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 193 if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 194 if (latch) tlbNoQuery := RegEnable(input.tlbNoQuery, enable) else tlbNoQuery := input.tlbNoQuery 195 if (latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 196 if (latch) isLastElem := RegEnable(input.isLastElem, enable) else isLastElem := input.isLastElem 197 if (latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 198 if (latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 199 if (latch) is_first_ele := RegEnable(input.is_first_ele, enable) else is_first_ele := input.is_first_ele 200 if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 201 if (latch) usSecondInv := RegEnable(input.usSecondInv, enable) else usSecondInv := input.usSecondInv 202 if (latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 203 if (latch) elemIdx := RegEnable(input.elemIdx, enable) else elemIdx := input.elemIdx 204 if (latch) alignedType := RegEnable(input.alignedType, enable) else alignedType := input.alignedType 205 if (latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 206 if (latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 207 if (latch) vecBaseVaddr := RegEnable(input.vecBaseVaddr, enable) else vecBaseVaddr := input.vecBaseVaddr 208 if (latch) vecVaddrOffset := RegEnable(input.vecVaddrOffset, enable) else vecVaddrOffset := input.vecVaddrOffset 209 // if (latch) flowPtr := RegEnable(input.flowPtr, enable) else flowPtr := input.flowPtr 210 // if (latch) sflowPtr := RegEnable(input.sflowPtr, enable) else sflowPtr := input.sflowPtr 211 212 meta_prefetch := DontCare 213 meta_access := DontCare 214 forward_tlDchannel := DontCare 215 mshrid := DontCare 216 replayCarry := DontCare 217 atomic := DontCare 218 isLoadReplay := DontCare 219 isFastPath := DontCare 220 isFastReplay := DontCare 221 handledByMSHR := DontCare 222 replacementUpdated := DontCare 223 missDbUpdated := DontCare 224 delayedLoadError := DontCare 225 lateKill := DontCare 226 feedbacked := DontCare 227 ldCancel := DontCare 228 } 229 230 def asPrefetchReqBundle(): PrefetchReqBundle = { 231 val res = Wire(new PrefetchReqBundle) 232 res.vaddr := this.vaddr 233 res.paddr := this.paddr 234 res.pc := this.uop.pc 235 res.miss := this.miss 236 res.pfHitStream := isFromStream(this.meta_prefetch) 237 238 res 239 } 240} 241 242class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 243 244class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 245 // load inst replay informations 246 val rep_info = new LoadToLsqReplayIO 247 // queue entry data, except flag bits, will be updated if writeQueue is true, 248 // valid bit in LqWriteBundle will be ignored 249 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 250 251 252 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 253 if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 254 if(latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 255 if(latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt 256 if(latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper 257 if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 258 if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 259 if(latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE 260 if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask 261 if(latch) data := RegEnable(input.data, enable) else data := input.data 262 if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop 263 if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 264 if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss 265 if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 266 if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 267 if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 268 if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic 269 if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 270 if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 271 if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 272 if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 273 if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 274 if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 275 if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 276 if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay 277 if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath 278 if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay 279 if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid 280 if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel 281 if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry 282 if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 283 if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 284 if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR 285 if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated 286 if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated 287 if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError 288 if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill 289 if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked 290 if(latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 291 if(latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 292 if(latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 293 if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 294 if(latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 295 if(latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 296 if(latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 297 298 rep_info := DontCare 299 data_wen_dup := DontCare 300 } 301} 302 303class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 304 val need_rep = Bool() 305} 306 307class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 308 val vaddr = Output(UInt(VAddrBits.W)) 309 val paddr = Output(UInt(PAddrBits.W)) 310 val mask = Output(UInt((VLEN/8).W)) 311 val uop = Output(new DynInst) // for replay 312 val pc = Output(UInt(VAddrBits.W)) //for debug 313 val valid = Output(Bool()) 314 315 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 316 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 317 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 318 319 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 320 val sqIdx = Output(new SqPtr) 321 322 // dataInvalid suggests store to load forward found forward should happen, 323 // but data is not available for now. If dataInvalid, load inst should 324 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 325 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 326 327 // matchInvalid suggests in store to load forward logic, paddr cam result does 328 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 329 // should be raised to flush SQ and committed sbuffer. 330 val matchInvalid = Input(Bool()) // resp to load_s2 331 332 // addrInvalid suggests store to load forward found forward should happen, 333 // but address (SSID) is not available for now. If addrInvalid, load inst should 334 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 335 val addrInvalid = Input(Bool()) 336} 337 338// LoadForwardQueryIO used in load pipeline 339// 340// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 341// PipeIO use predecoded sqIdxMask for better forward timing 342class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 343 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 344 // sqIdxMask is calcuated in earlier stage for better timing 345 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 346 347 // dataInvalid: addr match, but data is not valid for now 348 val dataInvalidFast = Input(Bool()) // resp to load_s1 349 // val dataInvalid = Input(Bool()) // resp to load_s2 350 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 351 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 352} 353 354// Query load queue for ld-ld violation 355// 356// Req should be send in load_s1 357// Resp will be generated 1 cycle later 358// 359// Note that query req may be !ready, as dcache is releasing a block 360// If it happens, a replay from rs is needed. 361class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 362 val uop = new DynInst 363 // mask: load's data mask. 364 val mask = UInt((VLEN/8).W) 365 366 // paddr: load's paddr. 367 val paddr = UInt(PAddrBits.W) 368 // dataInvalid: load data is invalid. 369 val data_valid = Bool() 370} 371 372class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 373 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 374 val rep_frm_fetch = Bool() 375} 376 377class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 378 val req = Decoupled(new LoadNukeQueryReq) 379 val resp = Flipped(Valid(new LoadNukeQueryResp)) 380 val revoke = Output(Bool()) 381} 382 383class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 384 // robIdx: Requestor's (a store instruction) rob index for match logic. 385 val robIdx = new RobPtr 386 387 // paddr: requestor's (a store instruction) physical address for match logic. 388 val paddr = UInt(PAddrBits.W) 389 390 // mask: requestor's (a store instruction) data width mask for match logic. 391 val mask = UInt((VLEN/8).W) 392 393 // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr. 394 val matchLine = Bool() 395} 396 397class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle { 398 // from storeMisalignBuffer to storeQueue, control it's sbuffer write 399 val control = Output(new XSBundle { 400 // control sq to write-into sb 401 val writeSb = Bool() 402 val wdata = UInt(VLEN.W) 403 val wmask = UInt((VLEN / 8).W) 404 val paddr = UInt(PAddrBits.W) 405 val vaddr = UInt(VAddrBits.W) 406 val last = Bool() 407 val hasException = Bool() 408 // remove this entry in sq 409 val removeSq = Bool() 410 }) 411 // from storeQueue to storeMisalignBuffer, provide detail info of this store 412 val storeInfo = Input(new XSBundle { 413 val data = UInt(VLEN.W) 414 // is the data of the unaligned store ready at sq? 415 val dataReady = Bool() 416 // complete a data transfer from sq to sb 417 val completeSbTrans = Bool() 418 }) 419} 420 421// Store byte valid mask write bundle 422// 423// Store byte valid mask write to SQ takes 2 cycles 424class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 425 val sqIdx = new SqPtr 426 val mask = UInt((VLEN/8).W) 427} 428 429class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 430 // old dcache: optimize data sram read fanout 431 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 432 // val bank_oh = UInt(DCacheBanks.W) 433 434 // new dcache 435 val respDcacheData = UInt(VLEN.W) 436 val forwardMask = Vec(VLEN/8, Bool()) 437 val forwardData = Vec(VLEN/8, UInt(8.W)) 438 val uop = new DynInst // for data selection, only fwen and fuOpType are used 439 val addrOffset = UInt(4.W) // for data selection 440 441 // forward tilelink D channel 442 val forward_D = Bool() 443 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 444 445 // forward mshr data 446 val forward_mshr = Bool() 447 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 448 449 val forward_result_valid = Bool() 450 451 def mergeTLData(): UInt = { 452 // merge TL D or MSHR data at load s2 453 val dcache_data = respDcacheData 454 val use_D = forward_D && forward_result_valid 455 val use_mshr = forward_mshr && forward_result_valid 456 Mux( 457 use_D || use_mshr, 458 Mux( 459 use_D, 460 forwardData_D.asUInt, 461 forwardData_mshr.asUInt 462 ), 463 dcache_data 464 ) 465 } 466 467 def mergeLsqFwdData(dcacheData: UInt): UInt = { 468 // merge dcache and lsq forward data at load s3 469 val rdataVec = VecInit((0 until VLEN / 8).map(j => 470 Mux(forwardMask(j), forwardData(j), dcacheData(8*(j+1)-1, 8*j)) 471 )) 472 rdataVec.asUInt 473 } 474} 475 476// Load writeback data from load queue (refill) 477class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 478 val lqData = UInt(64.W) // load queue has merged data 479 val uop = new DynInst // for data selection, only fwen and fuOpType are used 480 val addrOffset = UInt(3.W) // for data selection 481 482 def mergedData(): UInt = { 483 lqData 484 } 485} 486 487// Bundle for load / store wait waking up 488class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 489 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 490 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 491} 492 493object AddPipelineReg { 494 class PipelineRegModule[T <: Data](gen: T) extends Module { 495 val io = IO(new Bundle() { 496 val in = Flipped(DecoupledIO(gen.cloneType)) 497 val out = DecoupledIO(gen.cloneType) 498 val isFlush = Input(Bool()) 499 }) 500 501 val valid = RegInit(false.B) 502 valid.suggestName("pipeline_reg_valid") 503 when (io.out.fire) { valid := false.B } 504 when (io.in.fire) { valid := true.B } 505 when (io.isFlush) { valid := false.B } 506 507 io.in.ready := !valid || io.out.ready 508 io.out.bits := RegEnable(io.in.bits, io.in.fire) 509 io.out.valid := valid //&& !isFlush 510 } 511 512 def apply[T <: Data] 513 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 514 moduleName: Option[String] = None 515 ): Unit = { 516 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 517 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 518 pipelineReg.io.in <> left 519 right <> pipelineReg.io.out 520 pipelineReg.io.isFlush := isFlush 521 } 522}