1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.{SignExt, ZeroExt} 7import xiangshan.ExceptionNO._ 8import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 9import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 10import xiangshan.backend.fu.NewCSR.CSRDefines.{HgatpMode, SatpMode} 11import xiangshan.backend.fu.NewCSR._ 12import xiangshan.AddrTransType 13 14 15class TrapEntryVSEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 16 17 val vsstatus = ValidIO((new SstatusBundle ).addInEvent(_.SPP, _.SPIE, _.SIE)) 18 val vsepc = ValidIO((new Epc ).addInEvent(_.epc)) 19 val vscause = ValidIO((new CauseBundle ).addInEvent(_.Interrupt, _.ExceptionCode)) 20 val vstval = ValidIO((new OneFieldBundle).addInEvent(_.ALL)) 21 val targetPc = ValidIO(new TargetPCBundle) 22 23 def getBundleByName(name: String): Valid[CSRBundle] = { 24 name match { 25 case "vsstatus" => this.vsstatus 26 case "vsepc" => this.vsepc 27 case "vscause" => this.vscause 28 case "vstval" => this.vstval 29 } 30 } 31} 32 33class TrapEntryVSEventModule(implicit val p: Parameters) extends Module with CSREventBase { 34 val in = IO(new TrapEntryEventInput) 35 val out = IO(new TrapEntryVSEventOutput) 36 37 when (valid) { 38 assert(in.privState.isVirtual, "The mode must be VU or VS when entry VS mode") 39 } 40 41 private val current = in 42 private val iMode = current.iMode 43 private val dMode = current.dMode 44 private val satp = current.satp 45 private val vsatp = current.vsatp 46 private val hgatp = current.hgatp 47 48 private val trapCode = in.causeNO.ExceptionCode.asUInt 49 private val isException = !in.causeNO.Interrupt.asBool 50 private val isInterrupt = in.causeNO.Interrupt.asBool 51 private val virtualInterruptIsHvictlInject = in.virtualInterruptIsHvictlInject 52 private val hvictlIID = in.hvictlIID 53 54 when(valid && isInterrupt && !virtualInterruptIsHvictlInject) { 55 assert( 56 (InterruptNO.getVS ++ InterruptNO.getLocal).map(_.U === trapCode).reduce(_ || _), 57 "The VS mode can only handle VSEI, VSTI, VSSI and local interrupts" 58 ) 59 } 60 61 private val highPrioTrapNO = Mux( 62 InterruptNO.getVS.map(_.U === trapCode).reduce(_ || _) && isInterrupt, 63 trapCode - 1.U, // map VSSIP, VSTIP, VSEIP to SSIP, STIP, SEIP 64 trapCode, 65 ) 66 67 private val trapPC = genTrapVA( 68 iMode, 69 satp, 70 vsatp, 71 hgatp, 72 in.trapPc, 73 ) 74 75 private val trapMemVA = in.memExceptionVAddr 76 77 private val trapMemGPA = in.memExceptionGPAddr 78 79 private val trapInst = Mux(in.trapInst.valid, in.trapInst.bits, 0.U) 80 81 private val fetchIsVirt = current.iMode.isVirtual 82 private val memIsVirt = current.dMode.isVirtual 83 84 private val isFetchExcp = isException && Seq(/*EX_IAM, */ EX_IAF, EX_IPF).map(_.U === highPrioTrapNO).reduce(_ || _) 85 private val isMemExcp = isException && Seq(EX_LAM, EX_LAF, EX_SAM, EX_SAF, EX_LPF, EX_SPF).map(_.U === highPrioTrapNO).reduce(_ || _) 86 private val isBpExcp = isException && EX_BP.U === highPrioTrapNO 87 private val fetchCrossPage = in.isCrossPageIPF 88 private val isFetchMalAddr = in.isFetchMalAddr 89 private val isIllegalInst = isException && (EX_II.U === highPrioTrapNO || EX_VI.U === highPrioTrapNO) 90 91 // Software breakpoint exceptions are permitted to write either 0 or the pc to xtval 92 // We fill pc here 93 private val tvalFillPc = isFetchExcp && !fetchCrossPage || isBpExcp 94 private val tvalFillPcPlus2 = isFetchExcp && fetchCrossPage 95 private val tvalFillMemVaddr = isMemExcp 96 private val tvalFillGVA = 97 (isFetchExcp || isBpExcp) && fetchIsVirt || 98 isMemExcp && memIsVirt 99 private val tvalFillInst = isIllegalInst 100 101 private val tval = Mux1H(Seq( 102 (tvalFillPc ) -> trapPC, 103 (tvalFillPcPlus2 ) -> (trapPC + 2.U), 104 (tvalFillMemVaddr && !memIsVirt ) -> trapMemVA, 105 (tvalFillMemVaddr && memIsVirt ) -> trapMemVA, 106 (tvalFillInst ) -> trapInst, 107 )) 108 109 private val instrAddrTransType = AddrTransType( 110 bare = vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Bare, 111 sv39 = vsatp.MODE === SatpMode.Sv39, 112 sv48 = vsatp.MODE === SatpMode.Sv48, 113 sv39x4 = vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv39x4, 114 sv48x4 = vsatp.MODE === SatpMode.Bare && hgatp.MODE === HgatpMode.Sv48x4 115 ) 116 117 out := DontCare 118 119 out.privState.valid := valid 120 121 out.vsstatus .valid := valid 122 out.vsepc .valid := valid 123 out.vscause .valid := valid 124 out.vstval .valid := valid 125 out.targetPc .valid := valid 126 127 out.privState.bits := PrivState.ModeVS 128 // vsstatus 129 out.vsstatus.bits.SPP := current.privState.PRVM.asUInt(0, 0) // SPP is not PrivMode enum type, so asUInt and shrink the width 130 out.vsstatus.bits.SPIE := current.vsstatus.SIE 131 out.vsstatus.bits.SIE := 0.U 132 // SPVP is not PrivMode enum type, so asUInt and shrink the width 133 out.vsepc.bits.epc := Mux(isFetchMalAddr, in.fetchMalTval(63, 1), trapPC(63, 1)) 134 out.vscause.bits.Interrupt := isInterrupt 135 out.vscause.bits.ExceptionCode := Mux(virtualInterruptIsHvictlInject, hvictlIID, highPrioTrapNO) 136 out.vstval.bits.ALL := Mux(isFetchMalAddr, in.fetchMalTval, tval) 137 out.targetPc.bits.pc := in.pcFromXtvec 138 out.targetPc.bits.raiseIPF := instrAddrTransType.checkPageFault(in.pcFromXtvec) 139 out.targetPc.bits.raiseIAF := instrAddrTransType.checkAccessFault(in.pcFromXtvec) 140 out.targetPc.bits.raiseIGPF := instrAddrTransType.checkGuestPageFault(in.pcFromXtvec) 141 142 dontTouch(tvalFillGVA) 143} 144 145trait TrapEntryVSEventSinkBundle { self: CSRModule[_] => 146 val trapToVS = IO(Flipped(new TrapEntryVSEventOutput)) 147 148 private val updateBundle: ValidIO[CSRBundle] = trapToVS.getBundleByName(self.modName.toLowerCase()) 149 150 (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) => 151 if (updateBundle.bits.eventFields.contains(source)) { 152 when(updateBundle.valid) { 153 sink := source 154 } 155 } 156 } 157} 158