1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.cache.mmu 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import xiangshan._ 24import utils._ 25import utility._ 26import xiangshan.backend.rob.RobPtr 27import xiangshan.backend.fu.util.HasCSRConst 28import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 29import freechips.rocketchip.tilelink._ 30import xiangshan.backend.fu.{PMPReqBundle, PMPConfig} 31import xiangshan.backend.fu.PMPBundle 32 33 34abstract class TlbBundle(implicit p: Parameters) extends XSBundle with HasTlbConst 35abstract class TlbModule(implicit p: Parameters) extends XSModule with HasTlbConst 36 37 38class PtePermBundle(implicit p: Parameters) extends TlbBundle { 39 val d = Bool() 40 val a = Bool() 41 val g = Bool() 42 val u = Bool() 43 val x = Bool() 44 val w = Bool() 45 val r = Bool() 46 47 override def toPrintable: Printable = { 48 p"d:${d} a:${a} g:${g} u:${u} x:${x} w:${w} r:${r}"// + 49 //(if(hasV) (p"v:${v}") else p"") 50 } 51} 52 53class TlbPMBundle(implicit p: Parameters) extends TlbBundle { 54 val r = Bool() 55 val w = Bool() 56 val x = Bool() 57 val c = Bool() 58 val atomic = Bool() 59 60 def assign_ap(pm: PMPConfig) = { 61 r := pm.r 62 w := pm.w 63 x := pm.x 64 c := pm.c 65 atomic := pm.atomic 66 } 67} 68 69class TlbPermBundle(implicit p: Parameters) extends TlbBundle { 70 val pf = Bool() // NOTE: if this is true, just raise pf 71 val af = Bool() // NOTE: if this is true, just raise af 72 val v = Bool() // if stage1 pte is fake_pte, v is false 73 // pagetable perm (software defined) 74 val d = Bool() 75 val a = Bool() 76 val g = Bool() 77 val u = Bool() 78 val x = Bool() 79 val w = Bool() 80 val r = Bool() 81 82 def apply(item: PtwSectorResp) = { 83 val ptePerm = item.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 84 this.pf := item.pf 85 this.af := item.af 86 this.v := item.v 87 this.d := ptePerm.d 88 this.a := ptePerm.a 89 this.g := ptePerm.g 90 this.u := ptePerm.u 91 this.x := ptePerm.x 92 this.w := ptePerm.w 93 this.r := ptePerm.r 94 95 this 96 } 97 98 def applyS2(item: HptwResp) = { 99 val ptePerm = item.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 100 this.pf := item.gpf 101 this.af := item.gaf 102 this.v := DontCare 103 this.d := ptePerm.d 104 this.a := ptePerm.a 105 this.g := ptePerm.g 106 this.u := ptePerm.u 107 this.x := ptePerm.x 108 this.w := ptePerm.w 109 this.r := ptePerm.r 110 111 this 112 } 113 114 override def toPrintable: Printable = { 115 p"pf:${pf} af:${af} d:${d} a:${a} g:${g} u:${u} x:${x} w:${w} r:${r} " 116 } 117} 118 119class TlbSectorPermBundle(implicit p: Parameters) extends TlbBundle { 120 val pf = Bool() // NOTE: if this is true, just raise pf 121 val af = Bool() // NOTE: if this is true, just raise af 122 val v = Bool() // if stage1 pte is fake_pte, v is false 123 // pagetable perm (software defined) 124 val d = Bool() 125 val a = Bool() 126 val g = Bool() 127 val u = Bool() 128 val x = Bool() 129 val w = Bool() 130 val r = Bool() 131 132 def apply(item: PtwSectorResp) = { 133 val ptePerm = item.entry.perm.get.asTypeOf(new PtePermBundle().cloneType) 134 this.pf := item.pf 135 this.af := item.af 136 this.v := item.v 137 this.d := ptePerm.d 138 this.a := ptePerm.a 139 this.g := ptePerm.g 140 this.u := ptePerm.u 141 this.x := ptePerm.x 142 this.w := ptePerm.w 143 this.r := ptePerm.r 144 145 this 146 } 147 override def toPrintable: Printable = { 148 p"pf:${pf} af:${af} d:${d} a:${a} g:${g} u:${u} x:${x} w:${w} r:${r} " 149 } 150} 151 152// multi-read && single-write 153// input is data, output is hot-code(not one-hot) 154class CAMTemplate[T <: Data](val gen: T, val set: Int, val readWidth: Int)(implicit p: Parameters) extends TlbModule { 155 val io = IO(new Bundle { 156 val r = new Bundle { 157 val req = Input(Vec(readWidth, gen)) 158 val resp = Output(Vec(readWidth, Vec(set, Bool()))) 159 } 160 val w = Input(new Bundle { 161 val valid = Bool() 162 val bits = new Bundle { 163 val index = UInt(log2Up(set).W) 164 val data = gen 165 } 166 }) 167 }) 168 169 val wordType = UInt(gen.getWidth.W) 170 val array = Reg(Vec(set, wordType)) 171 172 io.r.resp.zipWithIndex.map{ case (a,i) => 173 a := array.map(io.r.req(i).asUInt === _) 174 } 175 176 when (io.w.valid) { 177 array(io.w.bits.index) := io.w.bits.data.asUInt 178 } 179} 180 181class TlbSectorEntry(pageNormal: Boolean, pageSuper: Boolean)(implicit p: Parameters) extends TlbBundle { 182 require(pageNormal && pageSuper) 183 184 val tag = UInt(sectorvpnLen.W) 185 val asid = UInt(asidLen.W) 186 /* level, 11: 512GB size page(only for sv48) 187 10: 1GB size page 188 01: 2MB size page 189 00: 4KB size page 190 future sv57 extension should change level width 191 */ 192 val level = Some(UInt(2.W)) 193 val ppn = UInt(sectorppnLen.W) 194 val pbmt = UInt(ptePbmtLen.W) 195 val g_pbmt = UInt(ptePbmtLen.W) 196 val perm = new TlbSectorPermBundle 197 val valididx = Vec(tlbcontiguous, Bool()) 198 val pteidx = Vec(tlbcontiguous, Bool()) 199 val ppn_low = Vec(tlbcontiguous, UInt(sectortlbwidth.W)) 200 201 val g_perm = new TlbPermBundle 202 val vmid = UInt(vmidLen.W) 203 val s2xlate = UInt(2.W) 204 205 206 /** level usage: 207 * !PageSuper: page is only normal, level is None, match all the tag 208 * !PageNormal: page is only super, level is a Bool(), match high 9*2 parts 209 * bits0 0: need mid 9bits 210 * 1: no need mid 9bits 211 * PageSuper && PageNormal: page hold all the three type, 212 * bits0 0: need low 9bits 213 * bits1 0: need mid 9bits 214 */ 215 216 def hit(vpn: UInt, asid: UInt, nSets: Int = 1, ignoreAsid: Boolean = false, vmid: UInt, hasS2xlate: Bool, onlyS2: Bool = false.B, onlyS1: Bool = false.B): Bool = { 217 val asid_hit = Mux(hasS2xlate && onlyS2, true.B, if (ignoreAsid) true.B else (this.asid === asid)) 218 val addr_low_hit = valididx(vpn(2, 0)) 219 val vmid_hit = Mux(hasS2xlate, this.vmid === vmid, true.B) 220 val isPageSuper = !(level.getOrElse(0.U) === 0.U) 221 val pteidx_hit = Mux(hasS2xlate && !isPageSuper && !onlyS1, pteidx(vpn(2, 0)), true.B) 222 223 val tmp_level = level.get 224 val tag_matchs = Wire(Vec(Level + 1, Bool())) 225 tag_matchs(0) := tag(vpnnLen - sectortlbwidth - 1, 0) === vpn(vpnnLen - 1, sectortlbwidth) 226 for (i <- 1 until Level) { 227 tag_matchs(i) := tag(vpnnLen * (i + 1) - sectortlbwidth - 1, vpnnLen * i - sectortlbwidth) === vpn(vpnnLen * (i + 1) - 1, vpnnLen * i) 228 } 229 tag_matchs(Level) := tag(sectorvpnLen - 1, vpnnLen * Level - sectortlbwidth) === vpn(vpnLen - 1, vpnnLen * Level) 230 val level_matchs = Wire(Vec(Level + 1, Bool())) 231 for (i <- 0 until Level) { 232 level_matchs(i) := tag_matchs(i) || tmp_level >= (i + 1).U 233 } 234 level_matchs(Level) := tag_matchs(Level) 235 236 asid_hit && level_matchs.asUInt.andR && addr_low_hit && vmid_hit && pteidx_hit 237 } 238 239 def wbhit(data: PtwRespS2, asid: UInt, nSets: Int = 1, ignoreAsid: Boolean = false, s2xlate: UInt): Bool = { 240 val s1vpn = data.s1.entry.tag 241 val s2vpn = data.s2.entry.tag(vpnLen - 1, sectortlbwidth) 242 val wb_vpn = Mux(s2xlate === onlyStage2, s2vpn, s1vpn) 243 val vpn = Cat(wb_vpn, 0.U(sectortlbwidth.W)) 244 val asid_hit = if (ignoreAsid) true.B else (this.asid === asid) 245 val vpn_hit = Wire(Bool()) 246 val index_hit = Wire(Vec(tlbcontiguous, Bool())) 247 val wb_valididx = Wire(Vec(tlbcontiguous, Bool())) 248 val hasS2xlate = this.s2xlate =/= noS2xlate 249 val onlyS1 = this.s2xlate === onlyStage1 250 val onlyS2 = this.s2xlate === onlyStage2 251 val pteidx_hit = MuxCase(true.B, Seq( 252 onlyS2 -> (VecInit(UIntToOH(data.s2.entry.tag(sectortlbwidth - 1, 0))).asUInt === pteidx.asUInt), 253 hasS2xlate -> (pteidx.asUInt === data.s1.pteidx.asUInt) 254 )) 255 wb_valididx := Mux(s2xlate === onlyStage2, VecInit(UIntToOH(data.s2.entry.tag(sectortlbwidth - 1, 0)).asBools), data.s1.valididx) 256 val s2xlate_hit = s2xlate === this.s2xlate 257 258 val tmp_level = level.get 259 val tag_matchs = Wire(Vec(Level + 1, Bool())) 260 tag_matchs(0) := tag(vpnnLen - sectortlbwidth - 1, 0) === vpn(vpnnLen - 1, sectortlbwidth) 261 for (i <- 1 until Level) { 262 tag_matchs(i) := tag(vpnnLen * (i + 1) - sectortlbwidth - 1, vpnnLen * i - sectortlbwidth) === vpn(vpnnLen * (i + 1) - 1, vpnnLen * i) 263 } 264 tag_matchs(Level) := tag(sectorvpnLen - 1, vpnnLen * Level - sectortlbwidth) === vpn(vpnLen - 1, vpnnLen * Level) 265 val level_matchs = Wire(Vec(Level + 1, Bool())) 266 for (i <- 0 until Level) { 267 level_matchs(i) := tag_matchs(i) || tmp_level >= (i + 1).U 268 } 269 level_matchs(Level) := tag_matchs(Level) 270 vpn_hit := asid_hit && level_matchs.asUInt.andR 271 272 for (i <- 0 until tlbcontiguous) { 273 index_hit(i) := wb_valididx(i) && valididx(i) 274 } 275 276 // For example, tlb req to page cache with vpn 0x10 277 // At this time, 0x13 has not been paged, so page cache only resp 0x10 278 // When 0x13 refill to page cache, previous item will be flushed 279 // Now 0x10 and 0x13 are both valid in page cache 280 // However, when 0x13 refill to tlb, will trigger multi hit 281 // So will only trigger multi-hit when PopCount(data.valididx) = 1 282 vpn_hit && index_hit.reduce(_ || _) && PopCount(wb_valididx) === 1.U && s2xlate_hit && pteidx_hit 283 } 284 285 def apply(item: PtwRespS2): TlbSectorEntry = { 286 this.asid := item.s1.entry.asid 287 val inner_level = MuxLookup(item.s2xlate, 2.U)(Seq( 288 onlyStage1 -> item.s1.entry.level.getOrElse(0.U), 289 onlyStage2 -> item.s2.entry.level.getOrElse(0.U), 290 allStage -> (item.s1.entry.level.getOrElse(0.U) min item.s2.entry.level.getOrElse(0.U)), 291 noS2xlate -> item.s1.entry.level.getOrElse(0.U) 292 )) 293 this.level.map(_ := inner_level) 294 this.perm.apply(item.s1) 295 this.pbmt := item.s1.entry.pbmt 296 297 val s1tag = item.s1.entry.tag 298 val s2tag = item.s2.entry.tag(gvpnLen - 1, sectortlbwidth) 299 // if stage1 page is larger than stage2 page, need to merge s1tag and s2tag. 300 val s1tagFix = MuxCase(s1tag, Seq( 301 (item.s1.entry.level.getOrElse(0.U) === 3.U && item.s2.entry.level.getOrElse(0.U) === 2.U) -> Cat(item.s1.entry.tag(sectorvpnLen - 1, vpnnLen * 3 - sectortlbwidth), item.s2.entry.tag(vpnnLen * 3 - 1, vpnnLen * 2), 0.U((vpnnLen * 2 - sectortlbwidth).W)), 302 (item.s1.entry.level.getOrElse(0.U) === 3.U && item.s2.entry.level.getOrElse(0.U) === 1.U) -> Cat(item.s1.entry.tag(sectorvpnLen - 1, vpnnLen * 3 - sectortlbwidth), item.s2.entry.tag(vpnnLen * 3 - 1, vpnnLen), 0.U((vpnnLen - sectortlbwidth).W)), 303 (item.s1.entry.level.getOrElse(0.U) === 3.U && item.s2.entry.level.getOrElse(0.U) === 0.U) -> Cat(item.s1.entry.tag(sectorvpnLen - 1, vpnnLen * 3 - sectortlbwidth), item.s2.entry.tag(vpnnLen * 3 - 1, sectortlbwidth)), 304 (item.s1.entry.level.getOrElse(0.U) === 2.U && item.s2.entry.level.getOrElse(0.U) === 1.U) -> Cat(item.s1.entry.tag(sectorvpnLen - 1, vpnnLen * 2 - sectortlbwidth), item.s2.entry.tag(vpnnLen * 2 - 1, vpnnLen), 0.U((vpnnLen - sectortlbwidth).W)), 305 (item.s1.entry.level.getOrElse(0.U) === 2.U && item.s2.entry.level.getOrElse(0.U) === 0.U) -> Cat(item.s1.entry.tag(sectorvpnLen - 1, vpnnLen * 2 - sectortlbwidth), item.s2.entry.tag(vpnnLen * 2 - 1, sectortlbwidth)), 306 (item.s1.entry.level.getOrElse(0.U) === 1.U && item.s2.entry.level.getOrElse(0.U) === 0.U) -> Cat(item.s1.entry.tag(sectorvpnLen - 1, vpnnLen - sectortlbwidth), item.s2.entry.tag(vpnnLen - 1, sectortlbwidth)) 307 )) 308 this.tag := Mux(item.s2xlate === onlyStage2, s2tag, Mux(item.s2xlate === allStage, s1tagFix, s1tag)) 309 val s2page_pageSuper = item.s2.entry.level.getOrElse(0.U) =/= 0.U 310 this.pteidx := Mux(item.s2xlate === onlyStage2, VecInit(UIntToOH(item.s2.entry.tag(sectortlbwidth - 1, 0)).asBools), item.s1.pteidx) 311 val s2_valid = Mux(s2page_pageSuper, VecInit(Seq.fill(tlbcontiguous)(true.B)), VecInit(UIntToOH(item.s2.entry.tag(sectortlbwidth - 1, 0)).asBools)) 312 this.valididx := Mux(item.s2xlate === onlyStage2, s2_valid, item.s1.valididx) 313 // if stage2 page is larger than stage1 page, need to merge s2tag and s2ppn to get a new s2ppn. 314 val s1ppn = item.s1.entry.ppn 315 val s1ppn_low = item.s1.ppn_low 316 val s2ppn = MuxLookup(item.s2.entry.level.getOrElse(0.U), item.s2.entry.ppn(ppnLen - 1, sectortlbwidth))(Seq( 317 3.U -> Cat(item.s2.entry.ppn(ppnLen - 1, vpnnLen * 3), item.s2.entry.tag(vpnnLen * 3 - 1, sectortlbwidth)), 318 2.U -> Cat(item.s2.entry.ppn(ppnLen - 1, vpnnLen * 2), item.s2.entry.tag(vpnnLen * 2 - 1, sectortlbwidth)), 319 1.U -> Cat(item.s2.entry.ppn(ppnLen - 1, vpnnLen), item.s2.entry.tag(vpnnLen - 1, sectortlbwidth)) 320 )) 321 val s2ppn_tmp = MuxLookup(item.s2.entry.level.getOrElse(0.U), item.s2.entry.ppn(ppnLen - 1, 0))(Seq( 322 3.U -> Cat(item.s2.entry.ppn(ppnLen - 1, vpnnLen * 3), item.s2.entry.tag(vpnnLen * 3 - 1, 0)), 323 2.U -> Cat(item.s2.entry.ppn(ppnLen - 1, vpnnLen * 2), item.s2.entry.tag(vpnnLen * 2 - 1, 0)), 324 1.U -> Cat(item.s2.entry.ppn(ppnLen - 1, vpnnLen), item.s2.entry.tag(vpnnLen - 1, 0)) 325 )) 326 val s2ppn_low = VecInit(Seq.fill(tlbcontiguous)(s2ppn_tmp(sectortlbwidth - 1, 0))) 327 this.ppn := Mux(item.s2xlate === noS2xlate || item.s2xlate === onlyStage1, s1ppn, s2ppn) 328 this.ppn_low := Mux(item.s2xlate === noS2xlate || item.s2xlate === onlyStage1, s1ppn_low, s2ppn_low) 329 this.vmid := item.s1.entry.vmid.getOrElse(0.U) 330 this.g_pbmt := item.s2.entry.pbmt 331 this.g_perm.applyS2(item.s2) 332 this.s2xlate := item.s2xlate 333 this 334 } 335 336 // 4KB is normal entry, 2MB/1GB is considered as super entry 337 def is_normalentry(): Bool = { 338 if (!pageSuper) { true.B } 339 else if (!pageNormal) { false.B } 340 else { level.get === 0.U } 341 } 342 343 344 def genPPN(saveLevel: Boolean = false, valid: Bool = false.B)(vpn: UInt) : UInt = { 345 val inner_level = level.getOrElse(0.U) 346 val ppn_res = Cat(ppn(sectorppnLen - 1, vpnnLen * 3 - sectortlbwidth), 347 Mux(inner_level >= "b11".U , vpn(vpnnLen * 3 - 1, vpnnLen * 2), ppn(vpnnLen * 3 - sectortlbwidth - 1, vpnnLen * 2 - sectortlbwidth)), 348 Mux(inner_level >= "b10".U , vpn(vpnnLen * 2 - 1, vpnnLen), ppn(vpnnLen * 2 - sectortlbwidth - 1, vpnnLen - sectortlbwidth)), 349 Mux(inner_level >= "b01".U , vpn(vpnnLen - 1, 0), Cat(ppn(vpnnLen - sectortlbwidth - 1, 0), ppn_low(vpn(sectortlbwidth - 1, 0))))) 350 351 if (saveLevel) 352 RegEnable(ppn_res, valid) 353 else 354 ppn_res 355 } 356 357 def hasS2xlate(): Bool = { 358 this.s2xlate =/= noS2xlate 359 } 360 361 override def toPrintable: Printable = { 362 val inner_level = level.getOrElse(2.U) 363 p"asid: ${asid} level:${inner_level} vpn:${Hexadecimal(tag)} ppn:${Hexadecimal(ppn)} perm:${perm}" 364 } 365 366} 367 368object TlbCmd { 369 def read = "b00".U 370 def write = "b01".U 371 def exec = "b10".U 372 373 def atom_read = "b100".U // lr 374 def atom_write = "b101".U // sc / amo 375 376 def apply() = UInt(3.W) 377 def isRead(a: UInt) = a(1,0)===read 378 def isWrite(a: UInt) = a(1,0)===write 379 def isExec(a: UInt) = a(1,0)===exec 380 381 def isAtom(a: UInt) = a(2) 382 def isAmo(a: UInt) = a===atom_write // NOTE: sc mixed 383} 384 385// Svpbmt extension 386object Pbmt { 387 def pma: UInt = "b00".U // None 388 def nc: UInt = "b01".U // Non-cacheable, idempotent, weakly-ordered (RVWMO), main memory 389 def io: UInt = "b10".U // Non-cacheable, non-idempotent, strongly-ordered (I/O ordering), I/O 390 def rsvd: UInt = "b11".U // Reserved for future standard use 391 def width: Int = 2 392 393 def apply() = UInt(2.W) 394 def isUncache(a: UInt) = a===nc || a===io 395} 396 397class TlbStorageIO(nSets: Int, nWays: Int, ports: Int, nDups: Int = 1)(implicit p: Parameters) extends MMUIOBaseBundle { 398 val r = new Bundle { 399 val req = Vec(ports, Flipped(DecoupledIO(new Bundle { 400 val vpn = Output(UInt(vpnLen.W)) 401 val s2xlate = Output(UInt(2.W)) 402 }))) 403 val resp = Vec(ports, ValidIO(new Bundle{ 404 val hit = Output(Bool()) 405 val ppn = Vec(nDups, Output(UInt(ppnLen.W))) 406 val pbmt = Vec(nDups, Output(UInt(ptePbmtLen.W))) 407 val g_pbmt = Vec(nDups, Output(UInt(ptePbmtLen.W))) 408 val perm = Vec(nDups, Output(new TlbSectorPermBundle())) 409 val g_perm = Vec(nDups, Output(new TlbPermBundle())) 410 val s2xlate = Vec(nDups, Output(UInt(2.W))) 411 })) 412 } 413 val w = Flipped(ValidIO(new Bundle { 414 val wayIdx = Output(UInt(log2Up(nWays).W)) 415 val data = Output(new PtwRespS2) 416 })) 417 val access = Vec(ports, new ReplaceAccessBundle(nSets, nWays)) 418 419 def r_req_apply(valid: Bool, vpn: UInt, i: Int, s2xlate:UInt): Unit = { 420 this.r.req(i).valid := valid 421 this.r.req(i).bits.vpn := vpn 422 this.r.req(i).bits.s2xlate := s2xlate 423 424 } 425 426 def r_resp_apply(i: Int) = { 427 (this.r.resp(i).bits.hit, this.r.resp(i).bits.ppn, this.r.resp(i).bits.perm, this.r.resp(i).bits.g_perm, this.r.resp(i).bits.pbmt, this.r.resp(i).bits.g_pbmt) 428 } 429 430 def w_apply(valid: Bool, wayIdx: UInt, data: PtwRespS2): Unit = { 431 this.w.valid := valid 432 this.w.bits.wayIdx := wayIdx 433 this.w.bits.data := data 434 } 435 436} 437 438class TlbStorageWrapperIO(ports: Int, q: TLBParameters, nDups: Int = 1)(implicit p: Parameters) extends MMUIOBaseBundle { 439 val r = new Bundle { 440 val req = Vec(ports, Flipped(DecoupledIO(new Bundle { 441 val vpn = Output(UInt(vpnLen.W)) 442 val s2xlate = Output(UInt(2.W)) 443 }))) 444 val resp = Vec(ports, ValidIO(new Bundle{ 445 val hit = Output(Bool()) 446 val ppn = Vec(nDups, Output(UInt(ppnLen.W))) 447 val pbmt = Vec(nDups, Output(UInt(ptePbmtLen.W))) 448 val g_pbmt = Vec(nDups, Output(UInt(ptePbmtLen.W))) 449 val perm = Vec(nDups, Output(new TlbPermBundle())) 450 val g_perm = Vec(nDups, Output(new TlbPermBundle())) 451 val s2xlate = Vec(nDups, Output(UInt(2.W))) 452 })) 453 } 454 val w = Flipped(ValidIO(new Bundle { 455 val data = Output(new PtwRespS2) 456 })) 457 val replace = if (q.outReplace) Flipped(new TlbReplaceIO(ports, q)) else null 458 459 def r_req_apply(valid: Bool, vpn: UInt, i: Int, s2xlate: UInt): Unit = { 460 this.r.req(i).valid := valid 461 this.r.req(i).bits.vpn := vpn 462 this.r.req(i).bits.s2xlate := s2xlate 463 } 464 465 def r_resp_apply(i: Int) = { 466 (this.r.resp(i).bits.hit, this.r.resp(i).bits.ppn, this.r.resp(i).bits.perm, this.r.resp(i).bits.g_perm, this.r.resp(i).bits.s2xlate, this.r.resp(i).bits.pbmt, this.r.resp(i).bits.g_pbmt) 467 } 468 469 def w_apply(valid: Bool, data: PtwRespS2): Unit = { 470 this.w.valid := valid 471 this.w.bits.data := data 472 } 473} 474 475class ReplaceAccessBundle(nSets: Int, nWays: Int)(implicit p: Parameters) extends TlbBundle { 476 val sets = Output(UInt(log2Up(nSets).W)) 477 val touch_ways = ValidIO(Output(UInt(log2Up(nWays).W))) 478} 479 480class ReplaceIO(Width: Int, nSets: Int, nWays: Int)(implicit p: Parameters) extends TlbBundle { 481 val access = Vec(Width, Flipped(new ReplaceAccessBundle(nSets, nWays))) 482 483 val refillIdx = Output(UInt(log2Up(nWays).W)) 484 val chosen_set = Flipped(Output(UInt(log2Up(nSets).W))) 485 486 def apply_sep(in: Seq[ReplaceIO], vpn: UInt): Unit = { 487 for ((ac_rep, ac_tlb) <- access.zip(in.map(a => a.access.map(b => b)).flatten)) { 488 ac_rep := ac_tlb 489 } 490 this.chosen_set := get_set_idx(vpn, nSets) 491 in.map(a => a.refillIdx := this.refillIdx) 492 } 493} 494 495class TlbReplaceIO(Width: Int, q: TLBParameters)(implicit p: Parameters) extends 496 TlbBundle { 497 val page = new ReplaceIO(Width, q.NSets, q.NWays) 498 499 def apply_sep(in: Seq[TlbReplaceIO], vpn: UInt) = { 500 this.page.apply_sep(in.map(_.page), vpn) 501 } 502 503} 504 505class MemBlockidxBundle(implicit p: Parameters) extends TlbBundle { 506 val is_ld = Bool() 507 val is_st = Bool() 508 val idx = UInt(log2Ceil(VirtualLoadQueueMaxStoreQueueSize).W) 509} 510 511class TlbReq(implicit p: Parameters) extends TlbBundle { 512 val vaddr = Output(UInt(VAddrBits.W)) 513 val fullva = Output(UInt(XLEN.W)) 514 val checkfullva = Output(Bool()) 515 val cmd = Output(TlbCmd()) 516 val hyperinst = Output(Bool()) 517 val hlvx = Output(Bool()) 518 val size = Output(UInt(log2Ceil(log2Ceil(VLEN/8)+1).W)) 519 val kill = Output(Bool()) // Use for blocked tlb that need sync with other module like icache 520 val memidx = Output(new MemBlockidxBundle) 521 // do not translate, but still do pmp/pma check 522 val no_translate = Output(Bool()) 523 val pmp_addr = Output(UInt(PAddrBits.W)) // load s1 send prefetch paddr 524 val debug = new Bundle { 525 val pc = Output(UInt(XLEN.W)) 526 val robIdx = Output(new RobPtr) 527 val isFirstIssue = Output(Bool()) 528 } 529 530 // Maybe Block req needs a kill: for itlb, itlb and icache may not sync, itlb should wait icache to go ahead 531 override def toPrintable: Printable = { 532 p"vaddr:0x${Hexadecimal(vaddr)} cmd:${cmd} kill:${kill} pc:0x${Hexadecimal(debug.pc)} robIdx:${debug.robIdx}" 533 } 534} 535 536class TlbExceptionBundle(implicit p: Parameters) extends TlbBundle { 537 val ld = Output(Bool()) 538 val st = Output(Bool()) 539 val instr = Output(Bool()) 540} 541 542class TlbResp(nDups: Int = 1)(implicit p: Parameters) extends TlbBundle { 543 val paddr = Vec(nDups, Output(UInt(PAddrBits.W))) 544 val gpaddr = Vec(nDups, Output(UInt(XLEN.W))) 545 val pbmt = Vec(nDups, Output(UInt(ptePbmtLen.W))) 546 val miss = Output(Bool()) 547 val fastMiss = Output(Bool()) 548 val excp = Vec(nDups, new Bundle { 549 val gpf = new TlbExceptionBundle() 550 val pf = new TlbExceptionBundle() 551 val af = new TlbExceptionBundle() 552 }) 553 val ptwBack = Output(Bool()) // when ptw back, wake up replay rs's state 554 val memidx = Output(new MemBlockidxBundle) 555 556 val debug = new Bundle { 557 val robIdx = Output(new RobPtr) 558 val isFirstIssue = Output(Bool()) 559 } 560 override def toPrintable: Printable = { 561 p"paddr:0x${Hexadecimal(paddr(0))} miss:${miss} excp.pf: ld:${excp(0).pf.ld} st:${excp(0).pf.st} instr:${excp(0).pf.instr} ptwBack:${ptwBack}" 562 } 563} 564 565class TlbRequestIO(nRespDups: Int = 1)(implicit p: Parameters) extends TlbBundle { 566 val req = DecoupledIO(new TlbReq) 567 val req_kill = Output(Bool()) 568 val resp = Flipped(DecoupledIO(new TlbResp(nRespDups))) 569} 570 571class TlbPtwIO(Width: Int = 1)(implicit p: Parameters) extends TlbBundle { 572 val req = Vec(Width, DecoupledIO(new PtwReq)) 573 val resp = Flipped(DecoupledIO(new PtwRespS2)) 574 575 576 override def toPrintable: Printable = { 577 p"req(0):${req(0).valid} ${req(0).ready} ${req(0).bits} | resp:${resp.valid} ${resp.ready} ${resp.bits}" 578 } 579} 580 581class TlbPtwIOwithMemIdx(Width: Int = 1)(implicit p: Parameters) extends TlbBundle { 582 val req = Vec(Width, DecoupledIO(new PtwReqwithMemIdx)) 583 val resp = Flipped(DecoupledIO(new PtwRespS2withMemIdx())) 584 585 586 override def toPrintable: Printable = { 587 p"req(0):${req(0).valid} ${req(0).ready} ${req(0).bits} | resp:${resp.valid} ${resp.ready} ${resp.bits}" 588 } 589} 590 591class TlbHintReq(implicit p: Parameters) extends TlbBundle { 592 val id = Output(UInt(log2Up(loadfiltersize).W)) 593 val full = Output(Bool()) 594} 595 596class TLBHintResp(implicit p: Parameters) extends TlbBundle { 597 val id = Output(UInt(log2Up(loadfiltersize).W)) 598 // When there are multiple matching entries for PTW resp in filter 599 // e.g. vaddr 0, 0x80000000. vaddr 1, 0x80010000 600 // these two vaddrs are not in a same 4K Page, so will send to ptw twice 601 // However, when ptw resp, if they are in a 1G or 2M huge page 602 // The two entries will both hit, and both need to replay 603 val replay_all = Output(Bool()) 604} 605 606class TlbHintIO(implicit p: Parameters) extends TlbBundle { 607 val req = Vec(backendParams.LdExuCnt, new TlbHintReq) 608 val resp = ValidIO(new TLBHintResp) 609} 610 611class MMUIOBaseBundle(implicit p: Parameters) extends TlbBundle { 612 val sfence = Input(new SfenceBundle) 613 val csr = Input(new TlbCsrBundle) 614 615 def base_connect(sfence: SfenceBundle, csr: TlbCsrBundle): Unit = { 616 this.sfence <> sfence 617 this.csr <> csr 618 } 619 620 // overwrite satp. write satp will cause flushpipe but csr.priv won't 621 // satp will be dealyed several cycles from writing, but csr.priv won't 622 // so inside mmu, these two signals should be divided 623 def base_connect(sfence: SfenceBundle, csr: TlbCsrBundle, satp: TlbSatpBundle) = { 624 this.sfence <> sfence 625 this.csr <> csr 626 this.csr.satp := satp 627 } 628} 629 630class TlbRefilltoMemIO()(implicit p: Parameters) extends TlbBundle { 631 val valid = Bool() 632 val memidx = new MemBlockidxBundle 633} 634 635class TlbIO(Width: Int, nRespDups: Int = 1, q: TLBParameters)(implicit p: Parameters) extends 636 MMUIOBaseBundle { 637 val hartId = Input(UInt(hartIdLen.W)) 638 val requestor = Vec(Width, Flipped(new TlbRequestIO(nRespDups))) 639 val flushPipe = Vec(Width, Input(Bool())) 640 val redirect = Flipped(ValidIO(new Redirect)) // flush the signal need_gpa in tlb 641 val ptw = new TlbPtwIOwithMemIdx(Width) 642 val refill_to_mem = Output(new TlbRefilltoMemIO()) 643 val replace = if (q.outReplace) Flipped(new TlbReplaceIO(Width, q)) else null 644 val pmp = Vec(Width, ValidIO(new PMPReqBundle(q.lgMaxSize))) 645 val tlbreplay = Vec(Width, Output(Bool())) 646} 647 648class VectorTlbPtwIO(Width: Int)(implicit p: Parameters) extends TlbBundle { 649 val req = Vec(Width, DecoupledIO(new PtwReqwithMemIdx())) 650 val resp = Flipped(DecoupledIO(new Bundle { 651 val data = new PtwRespS2withMemIdx 652 val vector = Output(Vec(Width, Bool())) 653 val getGpa = Output(Vec(Width, Bool())) 654 })) 655 656 def connect(normal: TlbPtwIOwithMemIdx): Unit = { 657 req <> normal.req 658 resp.ready := normal.resp.ready 659 normal.resp.bits := resp.bits.data 660 normal.resp.valid := resp.valid 661 } 662} 663 664/**************************** L2TLB *************************************/ 665abstract class PtwBundle(implicit p: Parameters) extends XSBundle with HasPtwConst 666abstract class PtwModule(outer: L2TLB) extends LazyModuleImp(outer) 667 with HasXSParameter with HasPtwConst 668 669class PteBundle(implicit p: Parameters) extends PtwBundle{ 670 val n = UInt(pteNLen.W) 671 val pbmt = UInt(ptePbmtLen.W) 672 val reserved = UInt(pteResLen.W) 673 val ppn_high = UInt(ppnHignLen.W) 674 val ppn = UInt(ppnLen.W) 675 val rsw = UInt(pteRswLen.W) 676 val perm = new Bundle { 677 val d = Bool() 678 val a = Bool() 679 val g = Bool() 680 val u = Bool() 681 val x = Bool() 682 val w = Bool() 683 val r = Bool() 684 val v = Bool() 685 } 686 687 def unaligned(level: UInt) = { 688 isLeaf() && 689 !(level === 0.U || 690 level === 1.U && ppn(vpnnLen-1, 0) === 0.U || 691 level === 2.U && ppn(vpnnLen*2-1, 0) === 0.U || 692 level === 3.U && ppn(vpnnLen*3-1, 0) === 0.U) 693 } 694 695 def isLeaf() = { 696 (perm.r || perm.x || perm.w) && perm.v 697 } 698 699 def isNext() = { 700 !(perm.r || perm.x || perm.w) && perm.v 701 } 702 703 def isPf(level: UInt, pbmte: Bool) = { 704 val pf = WireInit(false.B) 705 when (reserved =/= 0.U){ 706 pf := true.B 707 }.elsewhen(pbmt === 3.U || (!pbmte && pbmt =/= 0.U)){ 708 pf := true.B 709 }.elsewhen (isNext()) { 710 pf := (perm.u || perm.a || perm.d || n =/= 0.U || pbmt =/= 0.U) 711 }.elsewhen (!perm.v || (!perm.r && perm.w)) { 712 pf := true.B 713 }.elsewhen (n =/= 0.U && ppn(3, 0) =/= 8.U) { 714 pf := true.B 715 }.otherwise{ 716 pf := unaligned(level) 717 } 718 pf 719 } 720 721 def isGpf(level: UInt, pbmte: Bool) = { 722 val gpf = WireInit(false.B) 723 when (reserved =/= 0.U){ 724 gpf := true.B 725 }.elsewhen(pbmt === 3.U || (!pbmte && pbmt =/= 0.U)){ 726 gpf := true.B 727 }.elsewhen (isNext()) { 728 gpf := (perm.u || perm.a || perm.d || n =/= 0.U || pbmt =/= 0.U) 729 }.elsewhen (!perm.v || (!perm.r && perm.w)) { 730 gpf := true.B 731 }.elsewhen (!perm.u) { 732 gpf := true.B 733 }.elsewhen (n =/= 0.U && ppn(3, 0) =/= 8.U) { 734 gpf := true.B 735 }.otherwise{ 736 gpf := unaligned(level) 737 } 738 gpf 739 } 740 741 // ppn of Xiangshan is 48 - 12 bits but ppn of sv48 is 44 bits 742 // access fault will be raised when ppn >> ppnLen is not zero 743 def isAf(): Bool = { 744 !(ppn_high === 0.U) && perm.v 745 } 746 747 def isStage1Gpf(mode: UInt) = { 748 val sv39_high = Cat(ppn_high, ppn) >> (GPAddrBitsSv39x4 - offLen) 749 val sv48_high = Cat(ppn_high, ppn) >> (GPAddrBitsSv48x4 - offLen) 750 !(Mux(mode === Sv39, sv39_high, Mux(mode === Sv48, sv48_high, 0.U)) === 0.U) && perm.v 751 } 752 753 def getPerm() = { 754 val pm = Wire(new PtePermBundle) 755 pm.d := perm.d 756 pm.a := perm.a 757 pm.g := perm.g 758 pm.u := perm.u 759 pm.x := perm.x 760 pm.w := perm.w 761 pm.r := perm.r 762 pm 763 } 764 def getPPN() = { 765 Cat(ppn_high, ppn) 766 } 767 768 def canRefill(levelUInt: UInt, s2xlate: UInt, pbmte: Bool, mode: UInt) = { 769 val canRefill = WireInit(false.B) 770 switch (s2xlate) { 771 is (allStage) { 772 canRefill := !isStage1Gpf(mode) && !isPf(levelUInt, pbmte) 773 } 774 is (onlyStage1) { 775 canRefill := !isAf() && !isPf(levelUInt, pbmte) 776 } 777 is (onlyStage2) { 778 canRefill := !isAf() && !isGpf(levelUInt, pbmte) 779 } 780 is (noS2xlate) { 781 canRefill := !isAf() && !isPf(levelUInt, pbmte) 782 } 783 } 784 canRefill 785 } 786 787 def onlyPf(levelUInt: UInt, s2xlate: UInt, pbmte: Bool) = { 788 s2xlate === noS2xlate && isPf(levelUInt, pbmte) && !isAf() 789 } 790 791 override def toPrintable: Printable = { 792 p"ppn:0x${Hexadecimal(ppn)} perm:b${Binary(perm.asUInt)}" 793 } 794} 795 796class PtwEntry(tagLen: Int, hasPerm: Boolean = false, hasLevel: Boolean = false)(implicit p: Parameters) extends PtwBundle { 797 val tag = UInt(tagLen.W) 798 val asid = UInt(asidLen.W) 799 val vmid = if (HasHExtension) Some(UInt(vmidLen.W)) else None 800 val pbmt = UInt(ptePbmtLen.W) 801 val ppn = UInt(gvpnLen.W) 802 val perm = if (hasPerm) Some(new PtePermBundle) else None 803 val level = if (hasLevel) Some(UInt(log2Up(Level + 1).W)) else None 804 val prefetch = Bool() 805 val v = Bool() 806 807 def is_normalentry(): Bool = { 808 if (!hasLevel) true.B 809 else level.get === 2.U 810 } 811 812 def genPPN(vpn: UInt): UInt = { 813 if (!hasLevel) { 814 ppn 815 } else { 816 MuxLookup(level.get, 0.U)(Seq( 817 3.U -> Cat(ppn(ppn.getWidth-1, vpnnLen*3), vpn(vpnnLen*3-1, 0)), 818 2.U -> Cat(ppn(ppn.getWidth-1, vpnnLen*2), vpn(vpnnLen*2-1, 0)), 819 1.U -> Cat(ppn(ppn.getWidth-1, vpnnLen), vpn(vpnnLen-1, 0)), 820 0.U -> ppn) 821 ) 822 } 823 } 824 825 //s2xlate control whether compare vmid or not 826 def hit(vpn: UInt, asid: UInt, vasid: UInt, vmid: UInt, allType: Boolean = false, ignoreAsid: Boolean = false, s2xlate: Bool) = { 827 require(vpn.getWidth == vpnLen) 828// require(this.asid.getWidth <= asid.getWidth) 829 val asid_value = Mux(s2xlate, vasid, asid) 830 val asid_hit = if (ignoreAsid) true.B else (this.asid === asid_value) 831 val vmid_hit = Mux(s2xlate, (this.vmid.getOrElse(0.U) === vmid), true.B) 832 if (allType) { 833 require(hasLevel) 834 val tag_match = Wire(Vec(4, Bool())) // 512GB, 1GB, 2MB or 4KB, not parameterized here 835 for (i <- 0 until 3) { 836 tag_match(i) := tag(vpnnLen * (i + 1) - 1, vpnnLen * i) === vpn(vpnnLen * (i + 1) - 1, vpnnLen * i) 837 } 838 tag_match(3) := tag(tagLen - 1, vpnnLen * 3) === vpn(tagLen - 1, vpnnLen * 3) 839 840 val level_match = MuxLookup(level.getOrElse(0.U), false.B)(Seq( 841 3.U -> tag_match(3), 842 2.U -> (tag_match(3) && tag_match(2)), 843 1.U -> (tag_match(3) && tag_match(2) && tag_match(1)), 844 0.U -> (tag_match(3) && tag_match(2) && tag_match(1) && tag_match(0))) 845 ) 846 847 asid_hit && vmid_hit && level_match 848 } else if (hasLevel) { 849 val tag_match = Wire(Vec(3, Bool())) // SuperPage, 512GB, 1GB or 2MB 850 tag_match(0) := tag(tagLen - 1, tagLen - vpnnLen - extendVpnnBits) === vpn(vpnLen - 1, vpnLen - vpnnLen - extendVpnnBits) 851 for (i <- 1 until 3) { 852 tag_match(i) := tag(tagLen - vpnnLen * i - extendVpnnBits - 1, tagLen - vpnnLen * (i + 1) - extendVpnnBits) === vpn(vpnLen - vpnnLen * i - extendVpnnBits - 1, vpnLen - vpnnLen * (i + 1) - extendVpnnBits) 853 } 854 855 val level_match = MuxLookup(level.getOrElse(0.U), false.B)(Seq( 856 3.U -> tag_match(0), 857 2.U -> (tag_match(0) && tag_match(1)), 858 1.U -> (tag_match(0) && tag_match(1) && tag_match(2))) 859 ) 860 861 asid_hit && vmid_hit && level_match 862 } else { 863 asid_hit && vmid_hit && tag === vpn(vpnLen - 1, vpnLen - tagLen) 864 } 865 } 866 867 def refill(vpn: UInt, asid: UInt, vmid: UInt, pte: UInt, level: UInt = 0.U, prefetch: Bool, valid: Bool = false.B): Unit = { 868 require(this.asid.getWidth <= asid.getWidth) // maybe equal is better, but ugly outside 869 870 tag := vpn(vpnLen - 1, vpnLen - tagLen) 871 pbmt := pte.asTypeOf(new PteBundle().cloneType).pbmt 872 ppn := pte.asTypeOf(new PteBundle().cloneType).ppn 873 perm.map(_ := pte.asTypeOf(new PteBundle().cloneType).perm) 874 this.asid := asid 875 this.vmid.map(_ := vmid) 876 this.prefetch := prefetch 877 this.v := valid 878 this.level.map(_ := level) 879 } 880 881 def genPtwEntry(vpn: UInt, asid: UInt, pte: UInt, level: UInt = 0.U, prefetch: Bool, valid: Bool = false.B) = { 882 val e = Wire(new PtwEntry(tagLen, hasPerm, hasLevel)) 883 e.refill(vpn, asid, pte, level, prefetch, valid) 884 e 885 } 886 887 888 889 override def toPrintable: Printable = { 890 // p"tag:0x${Hexadecimal(tag)} ppn:0x${Hexadecimal(ppn)} perm:${perm}" 891 p"tag:0x${Hexadecimal(tag)} pbmt: ${pbmt} ppn:0x${Hexadecimal(ppn)} " + 892 (if (hasPerm) p"perm:${perm.getOrElse(0.U.asTypeOf(new PtePermBundle))} " else p"") + 893 (if (hasLevel) p"level:${level.getOrElse(0.U)}" else p"") + 894 p"prefetch:${prefetch}" 895 } 896} 897 898class PtwSectorEntry(tagLen: Int, hasPerm: Boolean = false, hasLevel: Boolean = false)(implicit p: Parameters) extends PtwEntry(tagLen, hasPerm, hasLevel) { 899 override val ppn = UInt(sectorptePPNLen.W) 900} 901 902class PtwMergeEntry(tagLen: Int, hasPerm: Boolean = false, hasLevel: Boolean = false)(implicit p: Parameters) extends PtwSectorEntry(tagLen, hasPerm, hasLevel) { 903 val ppn_low = UInt(sectortlbwidth.W) 904 val af = Bool() 905 val pf = Bool() 906} 907 908class PtwEntries(num: Int, tagLen: Int, level: Int, hasPerm: Boolean, ReservedBits: Int)(implicit p: Parameters) extends PtwBundle { 909 require(log2Up(num)==log2Down(num)) 910 // NOTE: hasPerm means that is leaf or not. 911 912 val tag = UInt(tagLen.W) 913 val asid = UInt(asidLen.W) 914 val vmid = Some(UInt(vmidLen.W)) 915 val pbmts = Vec(num, UInt(ptePbmtLen.W)) 916 val ppns = Vec(num, UInt(gvpnLen.W)) 917 // valid or not, vs = 0 will not hit 918 val vs = Vec(num, Bool()) 919 // only pf or not, onlypf = 1 means only trigger pf when nox2late 920 val onlypf = Vec(num, Bool()) 921 val perms = if (hasPerm) Some(Vec(num, new PtePermBundle)) else None 922 val prefetch = Bool() 923 val reservedBits = if(ReservedBits > 0) Some(UInt(ReservedBits.W)) else None 924 // println(s"PtwEntries: tag:1*${tagLen} ppns:${num}*${ppnLen} vs:${num}*1") 925 // NOTE: vs is used for different usage: 926 // for l0, which store the leaf(leaves), vs is page fault or not. 927 // for l1, which shoule not store leaf, vs is valid or not, that will anticipate in hit check 928 // Because, l1 should not store leaf(no perm), it doesn't store perm. 929 // If l1 hit a leaf, the perm is still unavailble. Should still page walk. Complex but nothing helpful. 930 // TODO: divide vs into validVec and pfVec 931 // for l1: may valid but pf, so no need for page walk, return random pte with pf. 932 933 def tagClip(vpn: UInt) = { 934 require(vpn.getWidth == vpnLen) 935 vpn(vpnLen - 1, vpnLen - tagLen) 936 } 937 938 def sectorIdxClip(vpn: UInt, level: Int) = { 939 getVpnClip(vpn, level)(log2Up(num) - 1, 0) 940 } 941 942 def hit(vpn: UInt, asid: UInt, vasid: UInt, vmid:UInt, ignoreAsid: Boolean = false, s2xlate: Bool) = { 943 val asid_value = Mux(s2xlate, vasid, asid) 944 val asid_hit = if (ignoreAsid) true.B else (this.asid === asid_value) 945 val vmid_hit = Mux(s2xlate, this.vmid.getOrElse(0.U) === vmid, true.B) 946 asid_hit && vmid_hit && tag === tagClip(vpn) && vs(sectorIdxClip(vpn, level)) 947 } 948 949 def genEntries(vpn: UInt, asid: UInt, vmid: UInt, data: UInt, levelUInt: UInt, prefetch: Bool, s2xlate: UInt, pbmte: Bool, mode: UInt) = { 950 require((data.getWidth / XLEN) == num, 951 s"input data length must be multiple of pte length: data.length:${data.getWidth} num:${num}") 952 953 val ps = Wire(new PtwEntries(num, tagLen, level, hasPerm, ReservedBits)) 954 ps.tag := tagClip(vpn) 955 ps.asid := asid 956 ps.vmid.map(_ := vmid) 957 ps.prefetch := prefetch 958 for (i <- 0 until num) { 959 val pte = data((i+1)*XLEN-1, i*XLEN).asTypeOf(new PteBundle) 960 ps.pbmts(i) := pte.pbmt 961 ps.ppns(i) := pte.ppn 962 ps.vs(i) := (pte.canRefill(levelUInt, s2xlate, pbmte, mode) || (if (hasPerm) pte.onlyPf(levelUInt, s2xlate, pbmte) else false.B)) && (if (hasPerm) pte.isLeaf() else !pte.isLeaf()) 963 ps.onlypf(i) := pte.onlyPf(levelUInt, s2xlate, pbmte) 964 ps.perms.map(_(i) := pte.perm) 965 } 966 ps.reservedBits.map(_ := true.B) 967 ps 968 } 969 970 override def toPrintable: Printable = { 971 // require(num == 4, "if num is not 4, please comment this toPrintable") 972 // NOTE: if num is not 4, please comment this toPrintable 973 val permsInner = perms.getOrElse(0.U.asTypeOf(Vec(num, new PtePermBundle))) 974 p"asid: ${Hexadecimal(asid)} tag:0x${Hexadecimal(tag)} pbmt:${printVec(pbmts)} ppns:${printVec(ppns)} vs:${Binary(vs.asUInt)} " + 975 (if (hasPerm) p"perms:${printVec(permsInner)}" else p"") 976 } 977} 978 979class PTWEntriesWithEcc(eccCode: Code, num: Int, tagLen: Int, level: Int, hasPerm: Boolean, ReservedBits: Int = 0)(implicit p: Parameters) extends PtwBundle { 980 val entries = new PtwEntries(num, tagLen, level, hasPerm, ReservedBits) 981 982 val ecc_block = XLEN 983 val ecc_info = get_ecc_info() 984 val ecc = if (l2tlbParams.enablePTWECC) Some(UInt(ecc_info._1.W)) else None 985 986 def get_ecc_info(): (Int, Int, Int, Int) = { 987 val eccBits_per = eccCode.width(ecc_block) - ecc_block 988 989 val data_length = entries.getWidth 990 val data_align_num = data_length / ecc_block 991 val data_not_align = (data_length % ecc_block) != 0 // ugly code 992 val data_unalign_length = data_length - data_align_num * ecc_block 993 val eccBits_unalign = eccCode.width(data_unalign_length) - data_unalign_length 994 995 val eccBits = eccBits_per * data_align_num + eccBits_unalign 996 (eccBits, eccBits_per, data_align_num, data_unalign_length) 997 } 998 999 def encode() = { 1000 val data = entries.asUInt 1001 val ecc_slices = Wire(Vec(ecc_info._3, UInt(ecc_info._2.W))) 1002 for (i <- 0 until ecc_info._3) { 1003 ecc_slices(i) := eccCode.encode(data((i+1)*ecc_block-1, i*ecc_block)) >> ecc_block 1004 } 1005 if (ecc_info._4 != 0) { 1006 val ecc_unaligned = eccCode.encode(data(data.getWidth-1, ecc_info._3*ecc_block)) >> ecc_info._4 1007 ecc.map(_ := Cat(ecc_unaligned, ecc_slices.asUInt)) 1008 } else { ecc.map(_ := ecc_slices.asUInt)} 1009 } 1010 1011 def decode(): Bool = { 1012 val data = entries.asUInt 1013 val res = Wire(Vec(ecc_info._3 + 1, Bool())) 1014 for (i <- 0 until ecc_info._3) { 1015 res(i) := {if (ecc_info._2 != 0) eccCode.decode(Cat(ecc.get((i+1)*ecc_info._2-1, i*ecc_info._2), data((i+1)*ecc_block-1, i*ecc_block))).error else false.B} 1016 } 1017 if (ecc_info._2 != 0 && ecc_info._4 != 0) { 1018 res(ecc_info._3) := eccCode.decode( 1019 Cat(ecc.get(ecc_info._1-1, ecc_info._2*ecc_info._3), data(data.getWidth-1, ecc_info._3*ecc_block))).error 1020 } else { res(ecc_info._3) := false.B } 1021 1022 Cat(res).orR 1023 } 1024 1025 def gen(vpn: UInt, asid: UInt, vmid: UInt, data: UInt, levelUInt: UInt, prefetch: Bool, s2xlate: UInt, pbmte: Bool, mode: UInt) = { 1026 this.entries := entries.genEntries(vpn, asid, vmid, data, levelUInt, prefetch, s2xlate, pbmte, mode) 1027 this.encode() 1028 } 1029} 1030 1031class PtwReq(implicit p: Parameters) extends PtwBundle { 1032 val vpn = UInt(vpnLen.W) //vpn or gvpn 1033 val s2xlate = UInt(2.W) 1034 def hasS2xlate(): Bool = { 1035 this.s2xlate =/= noS2xlate 1036 } 1037 def isOnlyStage2: Bool = { 1038 this.s2xlate === onlyStage2 1039 } 1040 override def toPrintable: Printable = { 1041 p"vpn:0x${Hexadecimal(vpn)}" 1042 } 1043} 1044 1045class PtwReqwithMemIdx(implicit p: Parameters) extends PtwReq { 1046 val memidx = new MemBlockidxBundle 1047 val getGpa = Bool() // this req is to get gpa when having guest page fault 1048} 1049 1050class PtwResp(implicit p: Parameters) extends PtwBundle { 1051 val entry = new PtwEntry(tagLen = vpnLen, hasPerm = true, hasLevel = true) 1052 val pf = Bool() 1053 val af = Bool() 1054 1055 def apply(pf: Bool, af: Bool, level: UInt, pte: PteBundle, vpn: UInt, asid: UInt) = { 1056 this.entry.level.map(_ := level) 1057 this.entry.tag := vpn 1058 this.entry.perm.map(_ := pte.getPerm()) 1059 this.entry.ppn := pte.ppn 1060 this.entry.pbmt := pte.pbmt 1061 this.entry.prefetch := DontCare 1062 this.entry.asid := asid 1063 this.entry.v := !pf 1064 this.pf := pf 1065 this.af := af 1066 } 1067 1068 override def toPrintable: Printable = { 1069 p"entry:${entry} pf:${pf} af:${af}" 1070 } 1071} 1072 1073class HptwResp(implicit p: Parameters) extends PtwBundle { 1074 val entry = new PtwEntry(tagLen = gvpnLen, hasPerm = true, hasLevel = true) 1075 val gpf = Bool() 1076 val gaf = Bool() 1077 1078 def apply(gpf: Bool, gaf: Bool, level: UInt, pte: PteBundle, vpn: UInt, vmid: UInt) = { 1079 val resp_pte = Mux(gaf, 0.U.asTypeOf(pte), pte) 1080 this.entry.level.map(_ := level) 1081 this.entry.tag := vpn 1082 this.entry.perm.map(_ := resp_pte.getPerm()) 1083 this.entry.ppn := resp_pte.ppn 1084 this.entry.pbmt := resp_pte.pbmt 1085 this.entry.prefetch := DontCare 1086 this.entry.asid := DontCare 1087 this.entry.vmid.map(_ := vmid) 1088 this.entry.v := !gpf 1089 this.gpf := gpf 1090 this.gaf := gaf 1091 } 1092 1093 def genPPNS2(vpn: UInt): UInt = { 1094 MuxLookup(entry.level.get, 0.U)(Seq( 1095 3.U -> Cat(entry.ppn(entry.ppn.getWidth - 1, vpnnLen * 3), vpn(vpnnLen * 3 - 1, 0)), 1096 2.U -> Cat(entry.ppn(entry.ppn.getWidth - 1, vpnnLen * 2), vpn(vpnnLen * 2 - 1, 0)), 1097 1.U -> Cat(entry.ppn(entry.ppn.getWidth - 1, vpnnLen), vpn(vpnnLen - 1, 0)), 1098 0.U -> Cat(entry.ppn(entry.ppn.getWidth - 1, 0)) 1099 )) 1100 } 1101 1102 def hit(gvpn: UInt, vmid: UInt): Bool = { 1103 val vmid_hit = this.entry.vmid.getOrElse(0.U) === vmid 1104 val tag_match = Wire(Vec(4, Bool())) // 512GB, 1GB, 2MB or 4KB, not parameterized here 1105 for (i <- 0 until 3) { 1106 tag_match(i) := entry.tag(vpnnLen * (i + 1) - 1, vpnnLen * i) === gvpn(vpnnLen * (i + 1) - 1, vpnnLen * i) 1107 } 1108 tag_match(3) := entry.tag(gvpnLen - 1, vpnnLen * 3) === gvpn(gvpnLen - 1, vpnnLen * 3) 1109 1110 val level_match = MuxLookup(entry.level.getOrElse(0.U), false.B)(Seq( 1111 3.U -> tag_match(3), 1112 2.U -> (tag_match(3) && tag_match(2)), 1113 1.U -> (tag_match(3) && tag_match(2) && tag_match(1)), 1114 0.U -> (tag_match(3) && tag_match(2) && tag_match(1) && tag_match(0))) 1115 ) 1116 1117 vmid_hit && level_match 1118 } 1119} 1120 1121class PtwSectorResp(implicit p: Parameters) extends PtwBundle { 1122 val entry = new PtwSectorEntry(tagLen = sectorvpnLen, hasPerm = true, hasLevel = true) 1123 val addr_low = UInt(sectortlbwidth.W) 1124 val ppn_low = Vec(tlbcontiguous, UInt(sectortlbwidth.W)) 1125 val valididx = Vec(tlbcontiguous, Bool()) 1126 val pteidx = Vec(tlbcontiguous, Bool()) 1127 val pf = Bool() 1128 val af = Bool() 1129 1130 1131 def genPPN(vpn: UInt): UInt = { 1132 MuxLookup(entry.level.get, 0.U)(Seq( 1133 3.U -> Cat(entry.ppn(entry.ppn.getWidth - 1, vpnnLen * 3 - sectortlbwidth), vpn(vpnnLen * 3 - 1, 0)), 1134 2.U -> Cat(entry.ppn(entry.ppn.getWidth - 1, vpnnLen * 2 - sectortlbwidth), vpn(vpnnLen * 2 - 1, 0)), 1135 1.U -> Cat(entry.ppn(entry.ppn.getWidth - 1, vpnnLen - sectortlbwidth), vpn(vpnnLen - 1, 0)), 1136 0.U -> Cat(entry.ppn(entry.ppn.getWidth - 1, 0), ppn_low(vpn(sectortlbwidth - 1, 0)))) 1137 ) 1138 } 1139 1140 def genGVPN(vpn: UInt): UInt = { 1141 val isNonLeaf = !(entry.perm.get.r || entry.perm.get.x || entry.perm.get.w) && entry.v && !pf && !af 1142 Mux(isNonLeaf, Cat(entry.ppn(entry.ppn.getWidth - 1, 0), ppn_low(vpn(sectortlbwidth - 1, 0))), genPPN(vpn)) 1143 } 1144 1145 def isLeaf() = { 1146 (entry.perm.get.r || entry.perm.get.x || entry.perm.get.w) && entry.v 1147 } 1148 1149 def isFakePte() = { 1150 !pf && !entry.v && !af 1151 } 1152 1153 def hit(vpn: UInt, asid: UInt, vmid: UInt, allType: Boolean = false, ignoreAsid: Boolean = false, s2xlate: Bool): Bool = { 1154 require(vpn.getWidth == vpnLen) 1155 // require(this.asid.getWidth <= asid.getWidth) 1156 val asid_hit = if (ignoreAsid) true.B else (this.entry.asid === asid) 1157 val vmid_hit = Mux(s2xlate, this.entry.vmid.getOrElse(0.U) === vmid, true.B) 1158 if (allType) { 1159 val addr_low_hit = valididx(vpn(sectortlbwidth - 1, 0)) 1160 val tag_match = Wire(Vec(4, Bool())) // 512GB, 1GB, 2MB or 4KB, not parameterized here 1161 tag_match(0) := entry.tag(vpnnLen - sectortlbwidth - 1, 0) === vpn(vpnnLen - 1, sectortlbwidth) 1162 for (i <- 1 until 3) { 1163 tag_match(i) := entry.tag(vpnnLen * (i + 1) - sectortlbwidth - 1, vpnnLen * i - sectortlbwidth) === vpn(vpnnLen * (i + 1) - 1, vpnnLen * i) 1164 } 1165 tag_match(3) := entry.tag(sectorvpnLen - 1, vpnnLen * 3 - sectortlbwidth) === vpn(vpnLen - 1, vpnnLen * 3) 1166 1167 val level_match = MuxLookup(entry.level.getOrElse(0.U), false.B)(Seq( 1168 3.U -> tag_match(3), 1169 2.U -> (tag_match(3) && tag_match(2)), 1170 1.U -> (tag_match(3) && tag_match(2) && tag_match(1)), 1171 0.U -> (tag_match(3) && tag_match(2) && tag_match(1) && tag_match(0))) 1172 ) 1173 1174 asid_hit && vmid_hit && level_match && addr_low_hit 1175 } else { 1176 val addr_low_hit = valididx(vpn(sectortlbwidth - 1, 0)) 1177 val tag_match = Wire(Vec(3, Bool())) // SuperPage, 512GB, 1GB or 2MB 1178 for (i <- 0 until 3) { 1179 tag_match(i) := entry.tag(sectorvpnLen - vpnnLen * i - 1, sectorvpnLen - vpnnLen * (i + 1)) === vpn(vpnLen - vpnnLen * i - 1, vpnLen - vpnnLen * (i + 1)) 1180 } 1181 1182 val level_match = MuxLookup(entry.level.getOrElse(0.U), false.B)(Seq( 1183 3.U -> tag_match(0), 1184 2.U -> (tag_match(0) && tag_match(1)), 1185 1.U -> (tag_match(0) && tag_match(1) && tag_match(2))) 1186 ) 1187 1188 asid_hit && vmid_hit && level_match && addr_low_hit 1189 } 1190 } 1191} 1192 1193class PtwMergeResp(implicit p: Parameters) extends PtwBundle { 1194 val entry = Vec(tlbcontiguous, new PtwMergeEntry(tagLen = sectorvpnLen, hasPerm = true, hasLevel = true)) 1195 val pteidx = Vec(tlbcontiguous, Bool()) 1196 val not_super = Bool() 1197 val not_merge = Bool() 1198 1199 def apply(pf: Bool, af: Bool, level: UInt, pte: PteBundle, vpn: UInt, asid: UInt, vmid:UInt, addr_low : UInt, not_super : Boolean = true, not_merge: Boolean = false) = { 1200 assert(tlbcontiguous == 8, "Only support tlbcontiguous = 8!") 1201 val resp_pte = pte 1202 val ptw_resp = Wire(new PtwMergeEntry(tagLen = sectorvpnLen, hasPerm = true, hasLevel = true)) 1203 ptw_resp.ppn := resp_pte.getPPN()(ptePPNLen - 1, sectortlbwidth) 1204 ptw_resp.ppn_low := resp_pte.getPPN()(sectortlbwidth - 1, 0) 1205 ptw_resp.pbmt := resp_pte.pbmt 1206 ptw_resp.level.map(_ := level) 1207 ptw_resp.perm.map(_ := resp_pte.getPerm()) 1208 ptw_resp.tag := vpn(vpnLen - 1, sectortlbwidth) 1209 ptw_resp.pf := pf 1210 ptw_resp.af := af 1211 ptw_resp.v := resp_pte.perm.v 1212 ptw_resp.prefetch := DontCare 1213 ptw_resp.asid := asid 1214 ptw_resp.vmid.map(_ := vmid) 1215 this.pteidx := UIntToOH(addr_low).asBools 1216 this.not_super := not_super.B 1217 this.not_merge := not_merge.B 1218 1219 for (i <- 0 until tlbcontiguous) { 1220 this.entry(i) := ptw_resp 1221 } 1222 } 1223 1224 def genPPN(): UInt = { 1225 val idx = OHToUInt(pteidx) 1226 val tag = Cat(entry(idx).tag, idx(sectortlbwidth - 1, 0)) 1227 MuxLookup(entry(idx).level.get, 0.U)(Seq( 1228 3.U -> Cat(entry(idx).ppn(entry(idx).ppn.getWidth - 1, vpnnLen * 3 - sectortlbwidth), tag(vpnnLen * 3 - 1, 0)), 1229 2.U -> Cat(entry(idx).ppn(entry(idx).ppn.getWidth - 1, vpnnLen * 2 - sectortlbwidth), tag(vpnnLen * 2 - 1, 0)), 1230 1.U -> Cat(entry(idx).ppn(entry(idx).ppn.getWidth - 1, vpnnLen - sectortlbwidth), tag(vpnnLen - 1, 0)), 1231 0.U -> Cat(entry(idx).ppn(entry(idx).ppn.getWidth - 1, 0), entry(idx).ppn_low)) 1232 ) 1233 } 1234} 1235 1236class PtwRespS2(implicit p: Parameters) extends PtwBundle { 1237 val s2xlate = UInt(2.W) 1238 val s1 = new PtwSectorResp() 1239 val s2 = new HptwResp() 1240 1241 def hasS2xlate: Bool = { 1242 this.s2xlate =/= noS2xlate 1243 } 1244 1245 def isOnlyStage2: Bool = { 1246 this.s2xlate === onlyStage2 1247 } 1248 1249 def getVpn(vpn: UInt): UInt = { 1250 val level = s1.entry.level.getOrElse(0.U) min s2.entry.level.getOrElse(0.U) 1251 val s1tag = Cat(s1.entry.tag, OHToUInt(s1.pteidx)) 1252 val s1tagFix = MuxCase(s1.entry.tag, Seq( 1253 (s1.entry.level.getOrElse(0.U) === 3.U && s2.entry.level.getOrElse(0.U) === 2.U) -> Cat(s1.entry.tag(sectorvpnLen - 1, vpnnLen * 3 - sectortlbwidth), s2.entry.tag(vpnnLen * 3 - 1, vpnnLen * 2), 0.U((vpnnLen * 2 - sectortlbwidth).W)), 1254 (s1.entry.level.getOrElse(0.U) === 3.U && s2.entry.level.getOrElse(0.U) === 1.U) -> Cat(s1.entry.tag(sectorvpnLen - 1, vpnnLen * 3 - sectortlbwidth), s2.entry.tag(vpnnLen * 3 - 1, vpnnLen), 0.U((vpnnLen - sectortlbwidth).W)), 1255 (s1.entry.level.getOrElse(0.U) === 3.U && s2.entry.level.getOrElse(0.U) === 0.U) -> Cat(s1.entry.tag(sectorvpnLen - 1, vpnnLen * 3 - sectortlbwidth), s2.entry.tag(vpnnLen * 3 - 1, sectortlbwidth)), 1256 (s1.entry.level.getOrElse(0.U) === 2.U && s2.entry.level.getOrElse(0.U) === 1.U) -> Cat(s1.entry.tag(sectorvpnLen - 1, vpnnLen * 2 - sectortlbwidth), s2.entry.tag(vpnnLen * 2 - 1, vpnnLen), 0.U((vpnnLen - sectortlbwidth).W)), 1257 (s1.entry.level.getOrElse(0.U) === 2.U && s2.entry.level.getOrElse(0.U) === 0.U) -> Cat(s1.entry.tag(sectorvpnLen - 1, vpnnLen * 2 - sectortlbwidth), s2.entry.tag(vpnnLen * 2 - 1, sectortlbwidth)), 1258 (s1.entry.level.getOrElse(0.U) === 1.U && s2.entry.level.getOrElse(0.U) === 0.U) -> Cat(s1.entry.tag(sectorvpnLen - 1, vpnnLen - sectortlbwidth), s2.entry.tag(vpnnLen - 1, sectortlbwidth)) 1259 )) 1260 val s1_vpn = MuxLookup(level, s1tag)(Seq( 1261 3.U -> Cat(s1tagFix(sectorvpnLen - 1, vpnnLen * 3 - sectortlbwidth), vpn(vpnnLen * 3 - 1, 0)), 1262 2.U -> Cat(s1tagFix(sectorvpnLen - 1, vpnnLen * 2 - sectortlbwidth), vpn(vpnnLen * 2 - 1, 0)), 1263 1.U -> Cat(s1tagFix(sectorvpnLen - 1, vpnnLen - sectortlbwidth), vpn(vpnnLen - 1, 0))) 1264 ) 1265 val s2_vpn = s2.entry.tag 1266 Mux(s2xlate === onlyStage2, s2_vpn, Mux(s2xlate === allStage, s1_vpn, s1tag)) 1267 } 1268 1269 def hit(vpn: UInt, asid: UInt, vasid: UInt, vmid: UInt, allType: Boolean = false, ignoreAsid: Boolean = false): Bool = { 1270 val noS2_hit = s1.hit(vpn, Mux(this.hasS2xlate, vasid, asid), vmid, allType, ignoreAsid, this.hasS2xlate) 1271 val onlyS2_hit = s2.hit(vpn, vmid) 1272 // allstage and onlys1 hit 1273 val s1vpn = Cat(s1.entry.tag, s1.addr_low) 1274 val level = s1.entry.level.getOrElse(0.U) min s2.entry.level.getOrElse(0.U) 1275 1276 val tag_match = Wire(Vec(4, Bool())) // 512GB, 1GB, 2MB or 4KB, not parameterized here 1277 for (i <- 0 until 3) { 1278 tag_match(i) := vpn(vpnnLen * (i + 1) - 1, vpnnLen * i) === s1vpn(vpnnLen * (i + 1) - 1, vpnnLen * i) 1279 } 1280 tag_match(3) := vpn(vpnLen - 1, vpnnLen * 3) === s1vpn(vpnLen - 1, vpnnLen * 3) 1281 val level_match = MuxLookup(level, false.B)(Seq( 1282 3.U -> tag_match(3), 1283 2.U -> (tag_match(3) && tag_match(2)), 1284 1.U -> (tag_match(3) && tag_match(2) && tag_match(1)), 1285 0.U -> (tag_match(3) && tag_match(2) && tag_match(1) && tag_match(0))) 1286 ) 1287 1288 val vpn_hit = level_match 1289 val vmid_hit = Mux(this.s2xlate === allStage, s2.entry.vmid.getOrElse(0.U) === vmid, true.B) 1290 val vasid_hit = if (ignoreAsid) true.B else (s1.entry.asid === vasid) 1291 val all_onlyS1_hit = vpn_hit && vmid_hit && vasid_hit 1292 Mux(this.s2xlate === noS2xlate, noS2_hit, 1293 Mux(this.s2xlate === onlyStage2, onlyS2_hit, all_onlyS1_hit)) 1294 } 1295} 1296 1297class PtwRespS2withMemIdx(implicit p: Parameters) extends PtwRespS2 { 1298 val memidx = new MemBlockidxBundle() 1299 val getGpa = Bool() // this req is to get gpa when having guest page fault 1300} 1301 1302class L2TLBIO(implicit p: Parameters) extends PtwBundle { 1303 val hartId = Input(UInt(hartIdLen.W)) 1304 val tlb = Vec(PtwWidth, Flipped(new TlbPtwIO)) 1305 val sfence = Input(new SfenceBundle) 1306 val csr = new Bundle { 1307 val tlb = Input(new TlbCsrBundle) 1308 val distribute_csr = Flipped(new DistributedCSRIO) 1309 } 1310} 1311 1312class L2TlbMemReqBundle(implicit p: Parameters) extends PtwBundle { 1313 val addr = UInt(PAddrBits.W) 1314 val id = UInt(bMemID.W) 1315 val hptw_bypassed = Bool() 1316} 1317 1318class L2TlbInnerBundle(implicit p: Parameters) extends PtwReq { 1319 val source = UInt(bSourceWidth.W) 1320} 1321 1322class L2TlbWithHptwIdBundle(implicit p: Parameters) extends PtwBundle { 1323 val req_info = new L2TlbInnerBundle 1324 val isHptwReq = Bool() 1325 val isLLptw = Bool() 1326 val hptwId = UInt(log2Up(l2tlbParams.llptwsize).W) 1327} 1328 1329object ValidHoldBypass{ 1330 def apply(infire: Bool, outfire: Bool, flush: Bool = false.B) = { 1331 val valid = RegInit(false.B) 1332 when (infire) { valid := true.B } 1333 when (outfire) { valid := false.B } // ATTENTION: order different with ValidHold 1334 when (flush) { valid := false.B } // NOTE: the flush will flush in & out, is that ok? 1335 valid || infire 1336 } 1337} 1338 1339class L1TlbDB(implicit p: Parameters) extends TlbBundle { 1340 val vpn = UInt(vpnLen.W) 1341} 1342 1343class PageCacheDB(implicit p: Parameters) extends TlbBundle with HasPtwConst { 1344 val vpn = UInt(vpnLen.W) 1345 val source = UInt(bSourceWidth.W) 1346 val bypassed = Bool() 1347 val is_first = Bool() 1348 val prefetched = Bool() 1349 val prefetch = Bool() 1350 val l2Hit = Bool() 1351 val l1Hit = Bool() 1352 val hit = Bool() 1353} 1354 1355class PTWDB(implicit p: Parameters) extends TlbBundle with HasPtwConst { 1356 val vpn = UInt(vpnLen.W) 1357 val source = UInt(bSourceWidth.W) 1358} 1359 1360class L2TlbPrefetchDB(implicit p: Parameters) extends TlbBundle { 1361 val vpn = UInt(vpnLen.W) 1362} 1363 1364class L2TlbMissQueueDB(implicit p: Parameters) extends TlbBundle { 1365 val vpn = UInt(vpnLen.W) 1366} 1367