fix(MMU): fix gvpn generate when PTWCache Stage1Hit a napot entry (#4527)

For allStage case, when there is a PageTableCache Stage1Hit, the GVPN is
reconstructed within the PTW. However, this reconst

fix(MMU): fix gvpn generate when PTWCache Stage1Hit a napot entry (#4527)

For allStage case, when there is a PageTableCache Stage1Hit, the GVPN is
reconstructed within the PTW. However, this reconstruction process did
not account for the napot case. This commit fixes the bug.

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fix(MMU): unify vmid matching logic (#4484)

In scenarios where virtualisation is turned on, either onlyS1, onlyS2,
or allStage, vmid matching is required. Specifically:

onlyS2: s2.vmid
onlyS1 or al

fix(MMU): unify vmid matching logic (#4484)

In scenarios where virtualisation is turned on, either onlyS1, onlyS2,
or allStage, vmid matching is required. Specifically:

onlyS2: s2.vmid
onlyS1 or allStage: s1.vmid

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fix(TLB): L1 TLB will not save the high bit of PPN (#4455)

Actually, the bit-width of s1ppn is sectorppnLen, which is defined as
PaddrBits(48) - Offset(12) - TLB compression(3). In contrast, the L2

fix(TLB): L1 TLB will not save the high bit of PPN (#4455)

Actually, the bit-width of s1ppn is sectorppnLen, which is defined as
PaddrBits(48) - Offset(12) - TLB compression(3). In contrast, the L2 TLB
returns item.s1.entry.ppn with a bit-width of sectorptePPNLen, which
equals ptePaddrLen(56) - Offset(12) - TLB compression(3).

The part of the PPN beyond PaddrBits is only used to generate gpaddr
when a guest page fault occurs, so it isn’t stored in the L1 TLB entry.
Here, we simply assign the lower (sectorppnLen - 1, 0) bits. In fact,
the original implementation would also work correctly, as it
automatically truncates the lower bits of item.s1.entry.ppn and assigns
them to s1ppn.

TODO: Not storing gpaddr (the upper PPN bits) in the L1 TLB currently
provides minimal benefits and significantly increases the complexity,
scalability, and maintainability issues of the TLB. In the new
architecture, we need to store gpaddr in the L1 TLB to avoid all the
additional handling related to guest page faults (gpf).

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fix(TLB): fix a typo about napot scenario (#4454)

fix(L2TLB): Napot entries in LLPTW should not be compressed (#4396)

fix(PTWCache): Should refill full GVPN to Page Cache (#4407)

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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fix(MMU): Should consider s2xlate when calculate page level (#4253)

fix(L1TLB): Should consider s2xlate when refill Svnapot (#4252)

feat(Svnapot): support Svnapot extension (#4107)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

feat(NCld): support WMO access for NC ld

* feat(LDU): add support for NC in LoadUnit

* feat(LQ,UB): add support for NC in load queue and uncache buffer

* chore(pbmt): add xsperf for nc ld statistic

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condi

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condition is
not satisfied for prefetch and redirected requests, resulting in stuck.
This commit fixes this bug.

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fix(TLB, RVH): delete the s1tagfix which maybe cause the tag check to fail (#3685)

fix(PTW, RVH): add the check A bit in HPTW when G-stage is for VS-stage (#3660)

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

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fix(PageTableCache): fix hit & bypass logic when onlypf (#3625)

fix(TLB): Should check vmid when s2xlate in wbhit (#3623)

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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fix(PageTableCache): fix ptwcache refill logic when exception (#3588)

Since L2 Cache access width is 512 bits, 8 PTE items are refilled into
page cache together. In previous design, when an excepti

fix(PageTableCache): fix ptwcache refill logic when exception (#3588)

Since L2 Cache access width is 512 bits, 8 PTE items are refilled into
page cache together. In previous design, when an exception occurs in one
of the 8 refilled PTE entries, none of the 8 entries will be refilled.
In this case, if there is a normal entry in one of the 8 neighbouring
page tables, it will not be refillled because of the exception in the
other entries, which will lead to blocking.

This commit fixes this problem. `vs` means that if one of the 8
consecutive page tables has an exception, the corresponding `vs` will be
forced to be false when judging hit. `onlypf` means that if x2slate is
not enabled, and only pf occurs, then the pf information will be
returned. Except for the onlypf case, the rest of the exceptions will
not be refilled in page cache (none of them will hit).

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fix(TLB, RVH): fix the bug that pf happens because s1 is nonleaf (#3580)

fix(L1TLB, RVH): fix the wrong pf because the perm check of fake pte (#3553)

fix(L2TLB): Fix exception generation logic (#3453)

* fix(L2TLB): Fix exception generation logic

We may currently generate three types of exceptions, pf, gpf, and af.
There must be only one type

fix(L2TLB): Fix exception generation logic (#3453)

* fix(L2TLB): Fix exception generation logic

We may currently generate three types of exceptions, pf, gpf, and af.
There must be only one type of exception that should occur in each resp
returned by L2 TLB, which is the type of exception that occurs for the
first time during the PTW process. Among them
pf & gpf: the two cases correspond to stage1 and stage2 respectively.
**In our previous design, the error is that onlyStage1 is also
considered to need gpf checking, but in fact, onlyStage1 shouldn't
report gpf.**
af: there are two kinds of access faults, the first one is the access
fault obtained by querying pmp before PTW accesses the memory, and the
second one is the access fault obtained by the PPN high level of page
table is not 0 after PTW accesses the memory. we call these two kinds of
access faults as pmp_af and ppn_af respectively.

For allStage case: pf, gpf, af can happen. pf precedes gpf (if pf is
reported in the first stage, it should be returned directly without
checking gpf in the second stage). For af, if it's pmp_af, this af will
be reported before actually accessing memory, and will have a higher
priority than pf or gpf (actually, if pmp_af occurs, no memory will be
accessed, and there will not be a pf or gpf at the same time). In case
of ppn_af, this af should actually be checked in pmp before being
reported before using this physical address for fetch or access.
However, since our physical address will be truncated directly on
return, we need to check the af in advance, and this af will have the
lowest priority and will be lower than pf | gpf. (i.e., pf and gpf will
not occur at the same time, pf > gpf. The two kinds of pf and pmp_af
will not occur at the same time, but may occur at the same time as
ppn_af, pmp_af > {pf or gpf} > ppn_af).

For onlyStage1: only pf or af will appear, same as above.
For onlyStage2: only gpf or af will appear, same as above.
For noS2xlate: only pf or af will appear, same as above.

* fix(L2TLB): prevent L1 PTEs with PPN AF to be refilled into
PageTableCache

L0 and L1 of PageTableCache caches 8 PTEs at once. When any of 8 PTEs
have a PPN with non-zero high bits, all 8 PTEs should not be refilled
into PageTableCache. Also, GPF refill filter is moved to vs generator.

* fix(L2TLB): block L2/L3 PTEs with PPN AF to be refilled

For onlyStage2, any PTE with non-zero high bits should not be refilled
into PageTableCache.

* fix(HPTW): incorrect priority of different kinds of AF and PF

In HTPW, there is 3 kinds of AF/PF:
- accessFault: PMP check failed when accessing THIS level PTE
- pageFault: this level PTE is not valid, such as v =0.
- ppn_af: the high bits of the PPN in this level PTE is not zero, which
means accessing NEXT level PTE will raise accessFault.

The priority of the above three is accessFault > pageFault > ppn_af.
This patch ensured this.

---------

Co-authored-by: Xu, Zefan <[email protected]>

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feat(pbmt): support PBMTE in MMU (#3521)

Co-authored-by: Xuan Hu <[email protected]>