1package xiangshan.backend.fu 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import utils.EnumUtils.OHEnumeration 6import xiangshan.ExceptionNO._ 7import xiangshan.SelImm 8import xiangshan.backend.Std 9import xiangshan.backend.fu.fpu.{IntToFP, IntFPToVec} 10import xiangshan.backend.fu.wrapper._ 11import xiangshan.backend.Bundles.ExuInput 12import xiangshan.backend.datapath.DataConfig._ 13 14/** 15 * 16 * @param name [[String]] name of fuConfig 17 * @param fuType [[Int]] type of func, select from [[xiangshan.backend.fu.FuType]] 18 * @param fuGen how to create $fu 19 * @param srcData type of src data used by this $fu 20 * @param piped if the $fu is pipelined 21 * @param maybeBlock the $fu need ready signal to block internal pipeline 22 * @param writeIntRf the $fu write int regfiles 23 * @param writeFpRf the $fu write float regfiles 24 * @param writeVecRf the $fu write vector regfiles 25 * @param writeV0Rf the $fu write v0 regfiles 26 * @param writeVlRf the $fu write vl regfiles 27 * @param writeFflags the $fu write fflags csr 28 * @param writeVxsat the $fu write vxsat csr 29 * @param destDataBits the width of output data in the $fu 30 * @param srcDataBits the width of input data in the $fu, the default value is destDataBits 31 * @param latency the latency of instuction executed in the $fu 32 * @param hasInputBuffer if the $fu has input buffer 33 * @param exceptionOut the $fu can produce these exception 34 * @param hasLoadError if the $fu has load error out 35 * @param flushPipe if the instuction executed in the $fu need flush out 36 * @param replayInst if the instuction executed in the $fu can replay in some condition 37 * @param trigger if the $fu need trigger out 38 * @param needSrcFrm if the $fu need float rounding mode signal 39 * @param needSrcVxrm if the $fu need vector fixed-point rounding mode signal 40 * @param immType the immediate type of this $fu 41 * @param vconfigWakeUp 42 * @param maskWakeUp 43 * 44 * @define fu function unit 45 */ 46case class FuConfig ( 47 name : String, 48 fuType : FuType.OHType, 49 fuGen : (Parameters, FuConfig) => FuncUnit, 50 srcData : Seq[Seq[DataConfig]], 51 piped : Boolean, 52 maybeBlock : Boolean = false, 53 writeIntRf : Boolean = false, 54 writeFpRf : Boolean = false, 55 writeVecRf : Boolean = false, 56 writeV0Rf : Boolean = false, 57 writeVlRf : Boolean = false, 58 writeFakeIntRf: Boolean = false, 59 writeFflags : Boolean = false, 60 writeVxsat : Boolean = false, 61 destDataBits : Int = 64, 62 srcDataBits : Option[Int] = None, 63 latency : HasFuLatency = CertainLatency(0),// two field (base latency, extra latency(option)) 64 hasInputBuffer: (Boolean, Int, Boolean) = (false, 0, false), 65 exceptionOut : Seq[Int] = Seq(), 66 hasLoadError : Boolean = false, 67 flushPipe : Boolean = false, 68 replayInst : Boolean = false, 69 trigger : Boolean = false, 70 needSrcFrm : Boolean = false, 71 needSrcVxrm : Boolean = false, 72 writeVType : Boolean = false, 73 immType : Set[UInt] = Set(), 74 // vector 75 vconfigWakeUp : Boolean = false, 76 maskWakeUp : Boolean = false, 77) { 78 def needIntWen: Boolean = writeIntRf || writeFakeIntRf 79 def needFpWen: Boolean = writeFpRf 80 def needVecWen: Boolean = writeVecRf 81 def needV0Wen: Boolean = writeV0Rf 82 def needVlWen: Boolean = writeVlRf 83 var vconfigIdx = -1 84 var maskSrcIdx = -1 85 if (vconfigWakeUp) { 86 vconfigIdx = getSpecialSrcIdx(VlData(), "when vconfigWakeUp is true, srcData must always contains VlData()") 87 } 88 if (maskWakeUp) { 89 maskSrcIdx = getSpecialSrcIdx(V0Data(), "when maskWakeUp is true, srcData must always contains V0Data()") 90 } 91 92 require(!piped || piped && latency.latencyVal.isDefined, "The latency value must be set when piped is enable") 93 require(!vconfigWakeUp || vconfigWakeUp && vconfigIdx >= 0, "The index of vl src must be set when vlWakeUp is enable") 94 require(!maskWakeUp || maskWakeUp && maskSrcIdx >= 0, "The index of mask src must be set when vlWakeUp is enable") 95 96 def numIntSrc : Int = srcData.map(_.count(x => IntRegSrcDataSet.contains(x))).fold(0)(_ max _) 97 def numFpSrc : Int = srcData.map(_.count(x => FpRegSrcDataSet.contains(x))).fold(0)(_ max _) 98 def numVecSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 99 def numVfSrc : Int = srcData.map(_.count(x => VecRegSrcDataSet.contains(x))).fold(0)(_ max _) 100 def numV0Src : Int = srcData.map(_.count(x => V0RegSrcDataSet.contains(x))).fold(0)(_ max _) 101 def numVlSrc : Int = srcData.map(_.count(x => VlRegSrcDataSet.contains(x))).fold(0)(_ max _) 102 def numRegSrc : Int = srcData.map(_.count(x => RegSrcDataSet.contains(x))).fold(0)(_ max _) 103 def numSrc : Int = srcData.map(_.length).fold(0)(_ max _) 104 105 def readFp: Boolean = numFpSrc > 0 106 107 def fuSel(uop: ExuInput): Bool = { 108 // Don't add more shit here!!! 109 // Todo: add new FuType to distinguish f2i, f2f 110 uop.fuType === this.fuType.U 111 } 112 113 /** 114 * params(i): data type set of the ith src port 115 * @return 116 */ 117 def getRfReadDataCfgSet: Seq[Set[DataConfig]] = { 118 val numSrcMax = srcData.map(_.length).fold(0)(_ max _) 119 // make srcData is uniform sized to avoid exception when transpose 120 val alignedSrcData: Seq[Seq[DataConfig]] = srcData.map(x => x ++ Seq.fill(numSrcMax - x.length)(null)) 121 alignedSrcData.transpose.map(_.toSet.intersect(RegSrcDataSet)) 122 } 123 124 def getSrcDataType(srcIdx: Int): Set[DataConfig] = { 125 srcData 126 .map((x: Seq[DataConfig]) => if(x.isDefinedAt(srcIdx)) Some(x(srcIdx)) else None) 127 .filter(_.nonEmpty) 128 .map(_.get) 129 .toSet 130 } 131 132 def hasNoDataWB: Boolean = { 133 !(writeIntRf || writeFpRf || writeVecRf || writeV0Rf || writeVlRf) 134 } 135 136 def getSrcMaxWidthVec = { 137 getRfReadDataCfgSet.map(_.map(_.dataWidth).max) 138 } 139 140 def genSrcDataVec: Seq[UInt] = { 141 getSrcMaxWidthVec.map(w => UInt(w.W)) 142 } 143 144 // csr's redirect also uses redirect bundle 145 def hasRedirect: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 146 147 def hasPredecode: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr, FuType.ldu).contains(fuType) 148 149 def needTargetPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 150 151 // predict info 152 def needPdInfo: Boolean = Seq(FuType.jmp, FuType.brh, FuType.csr).contains(fuType) 153 154 def needPc: Boolean = Seq(FuType.jmp, FuType.brh, FuType.fence).contains(fuType) 155 156 def needFPUCtrl: Boolean = { 157 import FuType._ 158 Seq(fmac, fDivSqrt, i2f).contains(fuType) 159 } 160 161 def needVecCtrl: Boolean = { 162 import FuType._ 163 Seq(falu, fmac, fDivSqrt, fcvt, 164 vipu, vialuF, vimac, vidiv, vfpu, vppu, vfalu, vfma, vfdiv, vfcvt, vldu, vstu).contains(fuType) 165 } 166 167 def isMul: Boolean = fuType == FuType.mul 168 169 def isDiv: Boolean = fuType == FuType.div 170 171 def isCsr: Boolean = fuType == FuType.csr 172 173 def isBrh: Boolean = fuType == FuType.brh 174 175 def isJmp: Boolean = fuType == FuType.jmp 176 177 def isFence: Boolean = fuType == FuType.fence 178 179 def isVecArith: Boolean = fuType == FuType.vialuF || fuType == FuType.vimac || 180 fuType == FuType.vppu || fuType == FuType.vipu || 181 fuType == FuType.vfalu || fuType == FuType.vfma || 182 fuType == FuType.vfdiv || fuType == FuType.vfcvt || 183 fuType == FuType.vidiv 184 185 def isVecMem: Boolean = fuType == FuType.vldu || fuType == FuType.vstu || 186 fuType == FuType.vsegldu || fuType == FuType.vsegstu 187 188 def needOg2: Boolean = isVecArith || fuType == FuType.vsetfwf || isVecMem 189 190 def isSta: Boolean = name.contains("sta") 191 192 def ckAlwaysEn: Boolean = isCsr || isFence 193 194 /** 195 * Get index of special src data, like [[VlData]], [[V0Data]] 196 * 197 * @param data [[DataConfig]] 198 * @param tips tips if get failed 199 * @return the index of special src data 200 */ 201 protected def getSpecialSrcIdx(data: DataConfig, tips: String): Int = { 202 val srcIdxVec = srcData.map(x => x.indexOf(data)) 203 val idx0 = srcIdxVec.head 204 for (idx <- srcIdxVec) { 205 require(idx >= 0 && idx == idx0, tips + ", and at the same index.") 206 } 207 idx0 208 } 209 210 override def toString: String = { 211 var str = s"${this.name}: " 212 if (vconfigWakeUp) str += s"vconfigIdx($vconfigIdx), " 213 if (maskWakeUp) str += s"maskSrcIdx($maskSrcIdx), " 214 str += s"latency($latency)" 215 str += s"src($srcData)" 216 str 217 } 218} 219 220object FuConfig { 221 val JmpCfg: FuConfig = FuConfig ( 222 name = "jmp", 223 fuType = FuType.jmp, 224 fuGen = (p: Parameters, cfg: FuConfig) => Module(new JumpUnit(cfg)(p)).suggestName("jmp"), 225 srcData = Seq( 226 Seq(IntData()), // jal 227 ), 228 piped = true, 229 writeIntRf = true, 230 immType = Set(SelImm.IMM_I, SelImm.IMM_UJ, SelImm.IMM_U), 231 ) 232 233 val BrhCfg: FuConfig = FuConfig ( 234 name = "brh", 235 fuType = FuType.brh, 236 fuGen = (p: Parameters, cfg: FuConfig) => Module(new BranchUnit(cfg)(p).suggestName("brh")), 237 srcData = Seq( 238 Seq(IntData(), IntData()), 239 ), 240 piped = true, 241 immType = Set(SelImm.IMM_SB), 242 ) 243 244 val I2fCfg: FuConfig = FuConfig ( 245 name = "i2f", 246 FuType.i2f, 247 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntToFP(cfg)(p).suggestName("i2f")), 248 srcData = Seq( 249 Seq(IntData()), 250 ), 251 piped = true, 252 writeFpRf = true, 253 writeFflags = true, 254 latency = CertainLatency(2), 255 needSrcFrm = true, 256 ) 257 258 val I2vCfg: FuConfig = FuConfig ( 259 name = "i2v", 260 FuType.i2v, 261 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("i2v")), 262 srcData = Seq( 263 Seq(IntData(), IntData()), 264 ), 265 piped = true, 266 writeFpRf = true, 267 writeVecRf = true, 268 writeV0Rf = true, 269 latency = CertainLatency(0), 270 destDataBits = 128, 271 srcDataBits = Some(64), 272 immType = Set(SelImm.IMM_OPIVIU, SelImm.IMM_OPIVIS, SelImm.IMM_VRORVI), 273 ) 274 275 val F2vCfg: FuConfig = FuConfig ( 276 name = "f2v", 277 FuType.f2v, 278 fuGen = (p: Parameters, cfg: FuConfig) => Module(new IntFPToVec(cfg)(p).suggestName("f2v")), 279 srcData = Seq( 280 Seq(FpData(), FpData()), 281 Seq(FpData()), 282 ), 283 piped = true, 284 writeFpRf = true, 285 writeVecRf = true, 286 writeV0Rf = true, 287 latency = CertainLatency(0), 288 destDataBits = 128, 289 srcDataBits = Some(64), 290 ) 291 292 val CsrCfg: FuConfig = FuConfig ( 293 name = "csr", 294 fuType = FuType.csr, 295 fuGen = (p: Parameters, cfg: FuConfig) => Module(new CSR(cfg)(p).suggestName("csr")), 296 srcData = Seq( 297 Seq(IntData()), 298 ), 299 piped = false, 300 writeIntRf = true, 301 latency = UncertainLatency(), 302 exceptionOut = Seq(illegalInstr, virtualInstr, breakPoint, ecallU, ecallS, ecallVS, ecallM), 303 flushPipe = true, 304 ) 305 306 val AluCfg: FuConfig = FuConfig ( 307 name = "alu", 308 fuType = FuType.alu, 309 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")), 310 srcData = Seq( 311 Seq(IntData(), IntData()), 312 ), 313 piped = true, 314 writeIntRf = true, 315 immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32), 316 ) 317 318 val MulCfg: FuConfig = FuConfig ( 319 name = "mul", 320 fuType = FuType.mul, 321 fuGen = (p: Parameters, cfg: FuConfig) => Module(new MulUnit(cfg)(p).suggestName("Mul")), 322 srcData = Seq( 323 Seq(IntData(), IntData()), 324 ), 325 piped = true, 326 writeIntRf = true, 327 latency = CertainLatency(2), 328 ) 329 330 val DivCfg: FuConfig = FuConfig ( 331 name = "div", 332 fuType = FuType.div, 333 fuGen = (p: Parameters, cfg: FuConfig) => Module(new DivUnit(cfg)(p).suggestName("Div")), 334 srcData = Seq( 335 Seq(IntData(), IntData()), 336 ), 337 piped = false, 338 writeIntRf = true, 339 latency = UncertainLatency(), 340 hasInputBuffer = (true, 4, true) 341 ) 342 343 val FenceCfg: FuConfig = FuConfig ( 344 name = "fence", 345 FuType.fence, 346 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Fence(cfg)(p).suggestName("Fence")), 347 srcData = Seq( 348 Seq(IntData(), IntData()), 349 ), 350 piped = false, 351 latency = UncertainLatency(), 352 exceptionOut = Seq(illegalInstr, virtualInstr), 353 flushPipe = true 354 ) 355 356 // Todo: split it to simple bitmap exu and complex bku 357 val BkuCfg: FuConfig = FuConfig ( 358 name = "bku", 359 fuType = FuType.bku, 360 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Bku(cfg)(p).suggestName("Bku")), 361 srcData = Seq( 362 Seq(IntData(), IntData()), 363 ), 364 piped = true, 365 writeIntRf = true, 366 latency = CertainLatency(2), 367 ) 368 369 val VSetRvfWvfCfg: FuConfig = FuConfig( 370 name = "vsetrvfwvf", 371 fuType = FuType.vsetfwf, 372 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRvfWvf(cfg)(p).suggestName("VSetRvfWvf")), 373 srcData = Seq( 374 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 375 ), 376 piped = true, 377 writeVlRf = true, 378 writeVType = true, 379 writeIntRf = true, 380 latency = CertainLatency(0), 381 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 382 ) 383 384 val VSetRiWvfCfg: FuConfig = FuConfig( 385 name = "vsetriwvf", 386 fuType = FuType.vsetiwf, 387 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWvf(cfg)(p).suggestName("VSetRiWvf")), 388 srcData = Seq( 389 Seq(IntData(), IntData()), 390 ), 391 piped = true, 392 writeVlRf = true, 393 writeVType = true, 394 latency = CertainLatency(0), 395 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 396 ) 397 398 val VSetRiWiCfg: FuConfig = FuConfig( 399 name = "vsetriwi", 400 fuType = FuType.vsetiwi, 401 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VSetRiWi(cfg)(p).suggestName("VSetRiWi")), 402 srcData = Seq( 403 Seq(IntData(), IntData()), 404 ), 405 piped = true, 406 writeIntRf = true, 407 latency = CertainLatency(0), 408 immType = Set(SelImm.IMM_VSETVLI, SelImm.IMM_VSETIVLI), 409 ) 410 411 val LduCfg: FuConfig = FuConfig ( 412 name = "ldu", 413 fuType = FuType.ldu, 414 fuGen = null, // Todo 415 srcData = Seq( 416 Seq(IntData()), 417 ), 418 piped = false, // Todo: check it 419 writeIntRf = true, 420 writeFpRf = true, 421 latency = UncertainLatency(3), 422 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault, breakPoint), 423 flushPipe = true, 424 replayInst = true, 425 hasLoadError = true, 426 trigger = true, 427 immType = Set(SelImm.IMM_I), 428 ) 429 430 val StaCfg: FuConfig = FuConfig ( 431 name = "sta", 432 fuType = FuType.stu, 433 fuGen = null, // Todo 434 srcData = Seq( 435 Seq(IntData()), 436 ), 437 piped = false, 438 latency = UncertainLatency(), 439 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault, breakPoint), 440 flushPipe = true, 441 trigger = true, 442 immType = Set(SelImm.IMM_S), 443 ) 444 445 val StdCfg: FuConfig = FuConfig ( 446 name = "std", 447 fuType = FuType.stu, 448 fuGen = (p: Parameters, cfg: FuConfig) => Module(new Std(cfg)(p).suggestName("Std")), 449 srcData = Seq( 450 Seq(IntData()), 451 Seq(FpData()), 452 ), 453 piped = true, 454 latency = CertainLatency(0) 455 ) 456 457 val HyldaCfg = FuConfig ( 458 name = "hylda", 459 fuType = FuType.ldu, 460 fuGen = null, // Todo 461 srcData = Seq( 462 Seq(IntData()), 463 ), 464 piped = false, // Todo: check it 465 writeIntRf = true, 466 writeFpRf = true, 467 latency = UncertainLatency(3), 468 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault), 469 flushPipe = true, 470 replayInst = true, 471 hasLoadError = true, 472 immType = Set(SelImm.IMM_I), 473 ) 474 475 val HystaCfg = FuConfig ( 476 name = "hysta", 477 fuType = FuType.stu, 478 fuGen = null, // Todo 479 srcData = Seq( 480 Seq(IntData()), 481 ), 482 piped = false, 483 latency = UncertainLatency(), 484 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 485 immType = Set(SelImm.IMM_S), 486 ) 487 488 val FakeHystaCfg = FuConfig ( 489 name = "hysta", 490 fuType = FuType.stu, 491 fuGen = null, // Todo 492 srcData = Seq(), 493 piped = false, 494 latency = UncertainLatency(), 495 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault), 496 immType = Set(), 497 ) 498 499 val MouCfg: FuConfig = FuConfig ( 500 name = "mou", 501 fuType = FuType.mou, 502 fuGen = null, // Todo 503 srcData = Seq( 504 Seq(IntData()), 505 ), 506 piped = false, // Todo: check it 507 writeFakeIntRf = true, 508 latency = UncertainLatency(), 509 exceptionOut = (LduCfg.exceptionOut ++ StaCfg.exceptionOut ++ StdCfg.exceptionOut).distinct, 510 trigger = true, 511 ) 512 513 val MoudCfg: FuConfig = FuConfig ( 514 name = "moud", 515 fuType = FuType.mou, 516 fuGen = null, // Todo 517 srcData = Seq( 518 Seq(IntData()), 519 ), 520 piped = true, 521 latency = CertainLatency(0), 522 ) 523 524 val VialuCfg = FuConfig ( 525 name = "vialuFix", 526 fuType = FuType.vialuF, 527 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIAluFix(cfg)(p).suggestName("VialuFix")), 528 srcData = Seq( 529 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 530 ), 531 piped = true, 532 writeVecRf = true, 533 writeV0Rf = true, 534 writeVxsat = true, 535 needSrcVxrm = true, 536 latency = CertainLatency(1), 537 vconfigWakeUp = true, 538 maskWakeUp = true, 539 destDataBits = 128, 540 exceptionOut = Seq(illegalInstr), 541 ) 542 543 val VimacCfg = FuConfig ( 544 name = "vimac", 545 fuType = FuType.vimac, 546 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIMacU(cfg)(p).suggestName("Vimac")), 547 srcData = Seq( 548 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 549 ), 550 piped = true, 551 writeVecRf = true, 552 writeV0Rf = true, 553 writeVxsat = true, 554 needSrcVxrm = true, 555 latency = CertainLatency(2), 556 vconfigWakeUp = true, 557 maskWakeUp = true, 558 destDataBits = 128, 559 exceptionOut = Seq(illegalInstr), 560 ) 561 562 val VidivCfg = FuConfig ( 563 name = "vidiv", 564 fuType = FuType.vidiv, 565 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIDiv(cfg)(p).suggestName("Vidiv")), 566 srcData = Seq( 567 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 568 ), 569 piped = false, 570 writeVecRf = true, 571 writeV0Rf = true, 572 latency = UncertainLatency(), 573 vconfigWakeUp = true, 574 maskWakeUp = true, 575 destDataBits = 128, 576 exceptionOut = Seq(illegalInstr), 577 ) 578 579 val VppuCfg = FuConfig ( 580 name = "vppu", 581 fuType = FuType.vppu, 582 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VPPU(cfg)(p).suggestName("Vppu")), 583 srcData = Seq( 584 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 585 ), 586 piped = true, 587 writeVecRf = true, 588 writeV0Rf = true, 589 latency = CertainLatency(2), 590 vconfigWakeUp = true, 591 maskWakeUp = true, 592 destDataBits = 128, 593 exceptionOut = Seq(illegalInstr), 594 ) 595 596 val VipuCfg: FuConfig = FuConfig ( 597 name = "vipu", 598 fuType = FuType.vipu, 599 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VIPU(cfg)(p).suggestName("Vipu")), 600 srcData = Seq( 601 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0 602 ), 603 piped = true, 604 writeIntRf = true, 605 writeVecRf = true, 606 writeV0Rf = true, 607 latency = CertainLatency(2), 608 vconfigWakeUp = true, 609 maskWakeUp = true, 610 destDataBits = 128, 611 exceptionOut = Seq(illegalInstr), 612 ) 613 614 val VfaluCfg = FuConfig ( 615 name = "vfalu", 616 fuType = FuType.vfalu, 617 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFAlu(cfg)(p).suggestName("Vfalu")), 618 srcData = Seq( 619 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 620 ), 621 piped = true, 622 writeVecRf = true, 623 writeV0Rf = true, 624 writeFpRf = true, 625 writeFflags = true, 626 latency = CertainLatency(1), 627 vconfigWakeUp = true, 628 maskWakeUp = true, 629 destDataBits = 128, 630 exceptionOut = Seq(illegalInstr), 631 needSrcFrm = true, 632 ) 633 634 val VfmaCfg = FuConfig ( 635 name = "vfma", 636 fuType = FuType.vfma, 637 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFMA(cfg)(p).suggestName("Vfma")), 638 srcData = Seq( 639 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 640 ), 641 piped = true, 642 writeVecRf = true, 643 writeV0Rf = true, 644 writeFflags = true, 645 latency = CertainLatency(3), 646 vconfigWakeUp = true, 647 maskWakeUp = true, 648 destDataBits = 128, 649 exceptionOut = Seq(illegalInstr), 650 needSrcFrm = true, 651 ) 652 653 val VfdivCfg = FuConfig( 654 name = "vfdiv", 655 fuType = FuType.vfdiv, 656 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VFDivSqrt(cfg)(p).suggestName("Vfdiv")), 657 srcData = Seq( 658 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 659 ), 660 piped = false, 661 writeVecRf = true, 662 writeV0Rf = true, 663 writeFflags = true, 664 latency = UncertainLatency(), 665 vconfigWakeUp = true, 666 maskWakeUp = true, 667 destDataBits = 128, 668 exceptionOut = Seq(illegalInstr), 669 needSrcFrm = true, 670 ) 671 672 val VfcvtCfg = FuConfig( 673 name = "vfcvt", 674 fuType = FuType.vfcvt, 675 fuGen = (p: Parameters, cfg: FuConfig) => Module(new VCVT(cfg)(p).suggestName("Vfcvt")), 676 srcData = Seq( 677 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), // vs1, vs2, vd_old, v0, vtype&vl 678 ), 679 piped = true, 680 writeVecRf = true, 681 writeV0Rf = true, 682 writeFflags = true, 683 latency = CertainLatency(2), 684 vconfigWakeUp = true, 685 maskWakeUp = true, 686 destDataBits = 128, 687 exceptionOut = Seq(illegalInstr), 688 needSrcFrm = true, 689 ) 690 691 val FaluCfg = FuConfig( 692 name = "falu", 693 fuType = FuType.falu, 694 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FAlu(cfg)(p).suggestName("Falu")), 695 srcData = Seq( 696 Seq(FpData(), FpData()), 697 ), 698 piped = true, 699 writeFpRf = true, 700 writeIntRf = true, 701 writeFflags = true, 702 latency = CertainLatency(1), 703 destDataBits = 64, 704 needSrcFrm = true, 705 ) 706 707 val FmacCfg = FuConfig( 708 name = "fmac", 709 fuType = FuType.fmac, 710 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FMA(cfg)(p).suggestName("Fmac")), 711 srcData = Seq( 712 Seq(FpData(), FpData(), FpData()), 713 ), 714 piped = true, 715 writeFpRf = true, 716 writeFflags = true, 717 latency = CertainLatency(3), 718 destDataBits = 64, 719 needSrcFrm = true, 720 ) 721 722 val FdivCfg = FuConfig( 723 name = "fdiv", 724 fuType = FuType.fDivSqrt, 725 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FDivSqrt(cfg)(p).suggestName("Fdiv")), 726 srcData = Seq( 727 Seq(FpData(), FpData()), 728 ), 729 piped = false, 730 writeFpRf = true, 731 writeFflags = true, 732 latency = UncertainLatency(), 733 destDataBits = 64, 734 needSrcFrm = true, 735 ) 736 737 val FcvtCfg = FuConfig( 738 name = "fcvt", 739 fuType = FuType.fcvt, 740 fuGen = (p: Parameters, cfg: FuConfig) => Module(new FCVT(cfg)(p).suggestName("Fcvt")), 741 srcData = Seq( 742 Seq(FpData()), 743 ), 744 piped = true, 745 writeFpRf = true, 746 writeIntRf = true, 747 writeFflags = true, 748 latency = CertainLatency(2), 749 destDataBits = 64, 750 needSrcFrm = true, 751 ) 752 753 val VlduCfg: FuConfig = FuConfig ( 754 name = "vldu", 755 fuType = FuType.vldu, 756 fuGen = null, 757 srcData = Seq( 758 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 759 ), 760 piped = false, // Todo: check it 761 writeVecRf = true, 762 writeV0Rf = true, 763 writeVlRf = true, 764 latency = UncertainLatency(), 765 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, loadGuestPageFault, breakPoint), 766 flushPipe = true, 767 replayInst = true, 768 trigger = true, 769 hasLoadError = true, 770 vconfigWakeUp = true, 771 maskWakeUp = true, 772 destDataBits = 128, 773 ) 774 775 val VstuCfg: FuConfig = FuConfig ( 776 name = "vstu", 777 fuType = FuType.vstu, 778 fuGen = null, 779 srcData = Seq( 780 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 781 ), 782 piped = false, 783 latency = UncertainLatency(), 784 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, storeGuestPageFault, breakPoint), 785 flushPipe = true, 786 replayInst = true, 787 trigger = true, 788 hasLoadError = true, 789 vconfigWakeUp = true, 790 maskWakeUp = true, 791 destDataBits = 128, 792 ) 793 794 val VseglduSeg: FuConfig = FuConfig ( 795 name = "vsegldu", 796 fuType = FuType.vsegldu, 797 fuGen = null, 798 srcData = Seq( 799 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 800 ), 801 piped = false, // Todo: check it 802 writeVecRf = true, 803 writeV0Rf = true, 804 writeVlRf = true, 805 latency = UncertainLatency(), 806 exceptionOut = Seq(loadAddrMisaligned, loadAccessFault, loadPageFault, breakPoint), 807 flushPipe = true, 808 replayInst = true, 809 trigger = true, 810 hasLoadError = true, 811 vconfigWakeUp = true, 812 maskWakeUp = true, 813 destDataBits = 128, 814 ) 815 816 val VsegstuCfg: FuConfig = FuConfig( 817 name = "vsegstu", 818 fuType = FuType.vsegstu, 819 fuGen = null, 820 srcData = Seq( 821 Seq(VecData(), VecData(), VecData(), V0Data(), VlData()), //vs1, vs2, vd_old, v0, vconfig 822 ), 823 piped = false, 824 latency = UncertainLatency(), 825 exceptionOut = Seq(storeAddrMisaligned, storeAccessFault, storePageFault, breakPoint), 826 flushPipe = true, 827 replayInst = true, 828 trigger = true, 829 hasLoadError = true, 830 vconfigWakeUp = true, 831 maskWakeUp = true, 832 destDataBits = 128, 833 ) 834 835 def allConfigs = Seq( 836 JmpCfg, BrhCfg, I2fCfg, I2vCfg, F2vCfg, CsrCfg, AluCfg, MulCfg, DivCfg, FenceCfg, BkuCfg, VSetRvfWvfCfg, VSetRiWvfCfg, VSetRiWiCfg, 837 LduCfg, StaCfg, StdCfg, MouCfg, MoudCfg, VialuCfg, VipuCfg, VlduCfg, VstuCfg, VseglduSeg, VsegstuCfg, 838 FaluCfg, FmacCfg, FcvtCfg, FdivCfg, 839 VfaluCfg, VfmaCfg, VfcvtCfg, HyldaCfg, HystaCfg 840 ) 841 842 def VecArithFuConfigs = Seq( 843 VialuCfg, VimacCfg, VppuCfg, VipuCfg, VfaluCfg, VfmaCfg, VfcvtCfg 844 ) 845} 846 847