1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import device.MsiInfoBundle 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import system.HasSoCParameter 25import utility._ 26import utils.{HPerfMonitor, HasPerfEvents, PerfEvent} 27import xiangshan._ 28import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals} 29import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 30import xiangshan.backend.datapath.DataConfig.{IntData, VecData, FpData} 31import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 32import xiangshan.backend.datapath.WbConfig._ 33import xiangshan.backend.datapath.DataConfig._ 34import xiangshan.backend.datapath._ 35import xiangshan.backend.dispatch.CoreDispatchTopDownIO 36import xiangshan.backend.exu.ExuBlock 37import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 38import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, FuType, PFEvent, PerfCounterIO} 39import xiangshan.backend.issue.EntryBundles._ 40import xiangshan.backend.issue.{CancelNetwork, Scheduler, SchedulerArithImp, SchedulerImpBase, SchedulerMemImp} 41import xiangshan.backend.rob.{RobCoreTopDownIO, RobDebugRollingIO, RobLsqIO, RobPtr} 42import xiangshan.frontend.{FtqPtr, FtqRead, PreDecodeInfo} 43import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 44 45import scala.collection.mutable 46 47class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 48 with HasXSParameter { 49 override def shouldBeInlined: Boolean = false 50 val inner = LazyModule(new BackendInlined(params)) 51 lazy val module = new BackendImp(this) 52} 53 54class BackendImp(wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) { 55 val io = IO(new BackendIO()(p, wrapper.params)) 56 io <> wrapper.inner.module.io 57 if (p(DebugOptionsKey).ResetGen) { 58 ResetGen(ResetGenNode(Seq(ModuleNode(wrapper.inner.module))), reset, sim = false) 59 } 60} 61 62class BackendInlined(val params: BackendParams)(implicit p: Parameters) extends LazyModule 63 with HasXSParameter { 64 65 override def shouldBeInlined: Boolean = true 66 67 // check read & write port config 68 params.configChecks 69 70 /* Only update the idx in mem-scheduler here 71 * Idx in other schedulers can be updated the same way if needed 72 * 73 * Also note that we filter out the 'stData issue-queues' when counting 74 */ 75 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 76 ibp.updateIdx(idx) 77 } 78 79 println(params.iqWakeUpParams) 80 81 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 82 schdCfg.bindBackendParam(params) 83 } 84 85 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 86 iqCfg.bindBackendParam(params) 87 } 88 89 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 90 exuCfg.bindBackendParam(params) 91 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 92 exuCfg.updateExuIdx(i) 93 } 94 95 println("[Backend] ExuConfigs:") 96 for (exuCfg <- params.allExuParams) { 97 val fuConfigs = exuCfg.fuConfigs 98 val wbPortConfigs = exuCfg.wbPortConfigs 99 val immType = exuCfg.immType 100 101 println("[Backend] " + 102 s"${exuCfg.name}: " + 103 (if (exuCfg.fakeUnit) "fake, " else "") + 104 (if (exuCfg.hasLoadFu || exuCfg.hasHyldaFu) s"LdExuIdx(${backendParams.getLdExuIdx(exuCfg)})" else "") + 105 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 106 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 107 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 108 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " + 109 s"srcReg(${exuCfg.numRegSrc})" 110 ) 111 require( 112 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 113 fuConfigs.map(_.writeIntRf).reduce(_ || _), 114 s"${exuCfg.name} int wb port has no priority" 115 ) 116 require( 117 wbPortConfigs.collectFirst { case x: FpWB => x }.nonEmpty == 118 fuConfigs.map(x => x.writeFpRf).reduce(_ || _), 119 s"${exuCfg.name} fp wb port has no priority" 120 ) 121 require( 122 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 123 fuConfigs.map(x => x.writeVecRf).reduce(_ || _), 124 s"${exuCfg.name} vec wb port has no priority" 125 ) 126 } 127 128 println(s"[Backend] all fu configs") 129 for (cfg <- FuConfig.allConfigs) { 130 println(s"[Backend] $cfg") 131 } 132 133 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 134 for ((port, seq) <- params.getRdPortParams(IntData())) { 135 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 136 } 137 138 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 139 for ((port, seq) <- params.getWbPortParams(IntData())) { 140 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 141 } 142 143 println(s"[Backend] Fp RdConfigs: ExuName(Priority)") 144 for ((port, seq) <- params.getRdPortParams(FpData())) { 145 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 146 } 147 148 println(s"[Backend] Fp WbConfigs: ExuName(Priority)") 149 for ((port, seq) <- params.getWbPortParams(FpData())) { 150 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 151 } 152 153 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 154 for ((port, seq) <- params.getRdPortParams(VecData())) { 155 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 156 } 157 158 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 159 for ((port, seq) <- params.getWbPortParams(VecData())) { 160 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 161 } 162 163 println(s"[Backend] Dispatch Configs:") 164 println(s"[Backend] Load IQ enq width(${params.numLoadDp}), Store IQ enq width(${params.numStoreDp})") 165 println(s"[Backend] Load DP width(${LSQLdEnqWidth}), Store DP width(${LSQStEnqWidth})") 166 167 params.updateCopyPdestInfo 168 println(s"[Backend] copyPdestInfo ${params.copyPdestInfo}") 169 params.allExuParams.map(_.copyNum) 170 val ctrlBlock = LazyModule(new CtrlBlock(params)) 171 val pcTargetMem = LazyModule(new PcTargetMem(params)) 172 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 173 val fpScheduler = params.fpSchdParams.map(x => LazyModule(new Scheduler(x))) 174 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 175 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 176 val dataPath = LazyModule(new DataPath(params)) 177 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 178 val fpExuBlock = params.fpSchdParams.map(x => LazyModule(new ExuBlock(x))) 179 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 180 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 181 182 lazy val module = new BackendInlinedImp(this) 183} 184 185class BackendInlinedImp(override val wrapper: BackendInlined)(implicit p: Parameters) extends LazyModuleImp(wrapper) 186 with HasXSParameter 187 with HasPerfEvents { 188 implicit private val params: BackendParams = wrapper.params 189 190 val io = IO(new BackendIO()(p, wrapper.params)) 191 192 private val ctrlBlock = wrapper.ctrlBlock.module 193 private val pcTargetMem = wrapper.pcTargetMem.module 194 private val intScheduler: SchedulerImpBase = wrapper.intScheduler.get.module 195 private val fpScheduler = wrapper.fpScheduler.get.module 196 private val vfScheduler = wrapper.vfScheduler.get.module 197 private val memScheduler = wrapper.memScheduler.get.module 198 private val dataPath = wrapper.dataPath.module 199 private val intExuBlock = wrapper.intExuBlock.get.module 200 private val fpExuBlock = wrapper.fpExuBlock.get.module 201 private val vfExuBlock = wrapper.vfExuBlock.get.module 202 private val og2ForVector = Module(new Og2ForVector(params)) 203 private val bypassNetwork = Module(new BypassNetwork) 204 private val wbDataPath = Module(new WbDataPath(params)) 205 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 206 207 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 208 intScheduler.io.toSchedulers.wakeupVec ++ 209 fpScheduler.io.toSchedulers.wakeupVec ++ 210 vfScheduler.io.toSchedulers.wakeupVec ++ 211 memScheduler.io.toSchedulers.wakeupVec 212 ).map(x => (x.bits.exuIdx, x)).toMap 213 214 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 215 216 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 217 wbFuBusyTable.io.in.fpSchdBusyTable := fpScheduler.io.wbFuBusyTable 218 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 219 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 220 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 221 fpScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.fpRespRead 222 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 223 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 224 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 225 226 private val og1Cancel = dataPath.io.og1Cancel 227 private val og0Cancel = dataPath.io.og0Cancel 228 private val vlIsZero = intExuBlock.io.vlIsZero.get 229 private val vlIsVlmax = intExuBlock.io.vlIsVlmax.get 230 231 ctrlBlock.io.intIQValidNumVec := intScheduler.io.intIQValidNumVec 232 ctrlBlock.io.fpIQValidNumVec := fpScheduler.io.fpIQValidNumVec 233 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 234 ctrlBlock.io.frontend <> io.frontend 235 ctrlBlock.io.fromCSR.toDecode := intExuBlock.io.csrToDecode.get 236 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 237 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 238 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 239 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 240 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 241 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 242 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 243 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 244 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 245 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 246 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 247 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 248 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 249 ctrlBlock.io.debugEnqLsq.canAccept := io.mem.lsqEnqIO.canAccept 250 ctrlBlock.io.debugEnqLsq.resp := io.mem.lsqEnqIO.resp 251 ctrlBlock.io.debugEnqLsq.req := memScheduler.io.memIO.get.lsqEnqIO.req 252 ctrlBlock.io.debugEnqLsq.needAlloc := memScheduler.io.memIO.get.lsqEnqIO.needAlloc 253 ctrlBlock.io.debugEnqLsq.iqAccept := memScheduler.io.memIO.get.lsqEnqIO.iqAccept 254 255 intScheduler.io.fromTop.hartId := io.fromTop.hartId 256 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 257 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 258 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 259 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 260 intScheduler.io.fpWriteBack := 0.U.asTypeOf(intScheduler.io.fpWriteBack) 261 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 262 intScheduler.io.v0WriteBack := 0.U.asTypeOf(intScheduler.io.v0WriteBack) 263 intScheduler.io.vlWriteBack := 0.U.asTypeOf(intScheduler.io.vlWriteBack) 264 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 265 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 266 intScheduler.io.fromDataPath.og0Cancel := og0Cancel 267 intScheduler.io.fromDataPath.og1Cancel := og1Cancel 268 intScheduler.io.ldCancel := io.mem.ldCancel 269 intScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.take(params.getIntExuRCWriteSize) 270 intScheduler.io.vlWriteBackInfo.vlIsZero := false.B 271 intScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 272 273 fpScheduler.io.fromTop.hartId := io.fromTop.hartId 274 fpScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 275 fpScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 276 fpScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.fpUops 277 fpScheduler.io.intWriteBack := 0.U.asTypeOf(fpScheduler.io.intWriteBack) 278 fpScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 279 fpScheduler.io.vfWriteBack := 0.U.asTypeOf(fpScheduler.io.vfWriteBack) 280 fpScheduler.io.v0WriteBack := 0.U.asTypeOf(fpScheduler.io.v0WriteBack) 281 fpScheduler.io.vlWriteBack := 0.U.asTypeOf(fpScheduler.io.vlWriteBack) 282 fpScheduler.io.fromDataPath.resp := dataPath.io.toFpIQ 283 fpScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 284 fpScheduler.io.fromDataPath.og0Cancel := og0Cancel 285 fpScheduler.io.fromDataPath.og1Cancel := og1Cancel 286 fpScheduler.io.ldCancel := io.mem.ldCancel 287 fpScheduler.io.vlWriteBackInfo.vlIsZero := false.B 288 fpScheduler.io.vlWriteBackInfo.vlIsVlmax := false.B 289 290 memScheduler.io.fromTop.hartId := io.fromTop.hartId 291 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 292 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 293 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 294 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 295 memScheduler.io.fpWriteBack := wbDataPath.io.toFpPreg 296 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 297 memScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 298 memScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 299 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 300 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 301 memScheduler.io.fromMem.get.wakeup := io.mem.wakeup 302 memScheduler.io.fromMem.get.sqDeqPtr := io.mem.sqDeqPtr 303 memScheduler.io.fromMem.get.lqDeqPtr := io.mem.lqDeqPtr 304 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 305 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 306 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 307 require(memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.length == io.mem.stIn.length) 308 memScheduler.io.fromMem.get.memWaitUpdateReq.robIdx.zip(io.mem.stIn).foreach { case (sink, source) => 309 sink.valid := source.valid 310 sink.bits := source.bits.robIdx 311 } 312 memScheduler.io.fromMem.get.memWaitUpdateReq.sqIdx := DontCare // TODO 313 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 314 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 315 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 316 memScheduler.io.fromMem.get.hyuFeedback := io.mem.hyuIqFeedback 317 memScheduler.io.fromMem.get.vstuFeedback := io.mem.vstuIqFeedback 318 memScheduler.io.fromMem.get.vlduFeedback := io.mem.vlduIqFeedback 319 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 320 memScheduler.io.fromDataPath.og0Cancel := og0Cancel 321 memScheduler.io.fromDataPath.og1Cancel := og1Cancel 322 memScheduler.io.ldCancel := io.mem.ldCancel 323 memScheduler.io.fromDataPath.replaceRCIdx.get := dataPath.io.toWakeupQueueRCIdx.takeRight(params.getMemExuRCWriteSize) 324 memScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 325 memScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 326 memScheduler.io.fromOg2Resp.get := og2ForVector.io.toMemIQOg2Resp 327 328 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 329 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 330 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 331 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 332 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 333 vfScheduler.io.fpWriteBack := 0.U.asTypeOf(vfScheduler.io.fpWriteBack) 334 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 335 vfScheduler.io.v0WriteBack := wbDataPath.io.toV0Preg 336 vfScheduler.io.vlWriteBack := wbDataPath.io.toVlPreg 337 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 338 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 339 vfScheduler.io.fromDataPath.og0Cancel := og0Cancel 340 vfScheduler.io.fromDataPath.og1Cancel := og1Cancel 341 vfScheduler.io.ldCancel := io.mem.ldCancel 342 vfScheduler.io.vlWriteBackInfo.vlIsZero := vlIsZero 343 vfScheduler.io.vlWriteBackInfo.vlIsVlmax := vlIsVlmax 344 vfScheduler.io.fromOg2Resp.get := og2ForVector.io.toVfIQOg2Resp 345 346 dataPath.io.hartId := io.fromTop.hartId 347 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 348 349 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 350 dataPath.io.fromFpIQ <> fpScheduler.io.toDataPathAfterDelay 351 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 352 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 353 354 dataPath.io.ldCancel := io.mem.ldCancel 355 356 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 357 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 358 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 359 dataPath.io.fromFpWb := wbDataPath.io.toFpPreg 360 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 361 dataPath.io.fromV0Wb := wbDataPath.io.toV0Preg 362 dataPath.io.fromVlWb := wbDataPath.io.toVlPreg 363 dataPath.io.diffIntRat.foreach(_ := ctrlBlock.io.diff_int_rat.get) 364 dataPath.io.diffFpRat .foreach(_ := ctrlBlock.io.diff_fp_rat.get) 365 dataPath.io.diffVecRat.foreach(_ := ctrlBlock.io.diff_vec_rat.get) 366 dataPath.io.diffV0Rat .foreach(_ := ctrlBlock.io.diff_v0_rat.get) 367 dataPath.io.diffVlRat .foreach(_ := ctrlBlock.io.diff_vl_rat.get) 368 dataPath.io.fromBypassNetwork := bypassNetwork.io.toDataPath 369 370 og2ForVector.io.flush := ctrlBlock.io.toDataPath.flush 371 og2ForVector.io.ldCancel := io.mem.ldCancel 372 og2ForVector.io.fromOg1VfArith <> dataPath.io.toVecExu 373 og2ForVector.io.fromOg1VecMem.zip(dataPath.io.toMemExu.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1)) 374 .foreach { 375 case (og1Mem, datapathMem) => og1Mem <> datapathMem 376 } 377 og2ForVector.io.fromOg1ImmInfo := dataPath.io.og1ImmInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 378 379 println(s"[Backend] BypassNetwork OG1 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filterNot(_._2.needOg2Resp).size}") 380 println(s"[Backend] BypassNetwork OG2 Mem Size: ${bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).size}") 381 println(s"[Backend] bypassNetwork.io.fromDataPath.mem: ${bypassNetwork.io.fromDataPath.mem.size}, dataPath.io.toMemExu: ${dataPath.io.toMemExu.size}") 382 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 383 bypassNetwork.io.fromDataPath.fp <> dataPath.io.toFpExu 384 bypassNetwork.io.fromDataPath.vf <> og2ForVector.io.toVfArithExu 385 bypassNetwork.io.fromDataPath.mem.lazyZip(params.memSchdParams.get.issueBlockParams).lazyZip(dataPath.io.toMemExu).filterNot(_._2.needOg2Resp) 386 .map(x => (x._1, x._3)).foreach { 387 case (bypassMem, datapathMem) => bypassMem <> datapathMem 388 } 389 bypassNetwork.io.fromDataPath.mem.zip(params.memSchdParams.get.issueBlockParams).filter(_._2.needOg2Resp).map(_._1) 390 .zip(og2ForVector.io.toVecMemExu).foreach { 391 case (bypassMem, og2Mem) => bypassMem <> og2Mem 392 } 393 bypassNetwork.io.fromDataPath.immInfo := dataPath.io.og1ImmInfo 394 bypassNetwork.io.fromDataPath.immInfo.zip(params.allExuParams).filter(_._2.needOg2).map(_._1) 395 .zip(og2ForVector.io.toBypassNetworkImmInfo).foreach { 396 case (immInfo, og2ImmInfo) => immInfo := og2ImmInfo 397 } 398 bypassNetwork.io.fromDataPath.rcData := dataPath.io.toBypassNetworkRCData 399 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 400 bypassNetwork.io.fromExus.connectExuOutput(_.fp)(fpExuBlock.io.out) 401 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 402 403 require(bypassNetwork.io.fromExus.mem.flatten.size == io.mem.writeBack.size, 404 s"bypassNetwork.io.fromExus.mem.flatten.size(${bypassNetwork.io.fromExus.mem.flatten.size}: ${bypassNetwork.io.fromExus.mem.map(_.size)}, " + 405 s"io.mem.writeback(${io.mem.writeBack.size})" 406 ) 407 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 408 sink.valid := source.valid 409 sink.bits.intWen := source.bits.uop.rfWen && FuType.isLoad(source.bits.uop.fuType) 410 sink.bits.pdest := source.bits.uop.pdest 411 sink.bits.data := source.bits.data 412 } 413 414 415 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 416 for (i <- 0 until intExuBlock.io.in.length) { 417 for (j <- 0 until intExuBlock.io.in(i).length) { 418 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 419 NewPipelineConnect( 420 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 421 Mux( 422 bypassNetwork.io.toExus.int(i)(j).fire, 423 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 424 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 425 ), 426 Option("bypassNetwork2intExuBlock") 427 ) 428 } 429 } 430 431 pcTargetMem.io.fromFrontendFtq := io.frontend.fromFtq 432 pcTargetMem.io.toDataPath <> dataPath.io.fromPcTargetMem 433 434 private val csrin = intExuBlock.io.csrin.get 435 csrin.hartId := io.fromTop.hartId 436 csrin.msiInfo.valid := RegNext(io.fromTop.msiInfo.valid) 437 csrin.msiInfo.bits := RegEnable(io.fromTop.msiInfo.bits, io.fromTop.msiInfo.valid) 438 csrin.clintTime.valid := RegNext(io.fromTop.clintTime.valid) 439 csrin.clintTime.bits := RegEnable(io.fromTop.clintTime.bits, io.fromTop.clintTime.valid) 440 csrin.trapInstInfo := ctrlBlock.io.toCSR.trapInstInfo 441 442 private val csrio = intExuBlock.io.csrio.get 443 csrio.hartId := io.fromTop.hartId 444 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 445 csrio.fpu.isIllegal := false.B // Todo: remove it 446 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 447 csrio.vpu <> WireDefault(0.U.asTypeOf(csrio.vpu)) // Todo 448 449 val fromIntExuVsetVType = intExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 450 val fromVfExuVsetVType = vfExuBlock.io.vtype.getOrElse(0.U.asTypeOf((Valid(new VType)))) 451 val fromVsetVType = Mux(fromIntExuVsetVType.valid, fromIntExuVsetVType.bits, fromVfExuVsetVType.bits) 452 val vsetvlVType = RegEnable(fromVsetVType, 0.U.asTypeOf(new VType), fromIntExuVsetVType.valid || fromVfExuVsetVType.valid) 453 ctrlBlock.io.toDecode.vsetvlVType := vsetvlVType 454 455 val commitVType = ctrlBlock.io.robio.commitVType.vtype 456 val hasVsetvl = ctrlBlock.io.robio.commitVType.hasVsetvl 457 val vtype = VType.toVtypeStruct(Mux(hasVsetvl, vsetvlVType, commitVType.bits)).asUInt 458 459 // csr not store the value of vl, so when using difftest we assign the value of vl to debugVl 460 val debugVl_s0 = WireInit(UInt(VlData().dataWidth.W), 0.U) 461 val debugVl_s1 = WireInit(UInt(VlData().dataWidth.W), 0.U) 462 debugVl_s0 := dataPath.io.diffVl.getOrElse(0.U.asTypeOf(UInt(VlData().dataWidth.W))) 463 debugVl_s1 := RegNext(debugVl_s0) 464 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 465 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vstart.valid 466 csrio.vpu.set_vstart.bits := ctrlBlock.io.robio.csr.vstart.bits 467 ctrlBlock.io.toDecode.vstart := csrio.vpu.vstart 468 //Todo here need change design 469 csrio.vpu.set_vtype.valid := commitVType.valid 470 csrio.vpu.set_vtype.bits := ZeroExt(vtype, XLEN) 471 csrio.vpu.vl := ZeroExt(debugVl_s1, XLEN) 472 csrio.vpu.dirty_vs := ctrlBlock.io.robio.csr.dirty_vs 473 csrio.exception := ctrlBlock.io.robio.exception 474 csrio.robDeqPtr := ctrlBlock.io.robio.robDeqPtr 475 csrio.memExceptionVAddr := io.mem.exceptionAddr.vaddr 476 csrio.memExceptionGPAddr := io.mem.exceptionAddr.gpaddr 477 csrio.memExceptionIsForVSnonLeafPTE := io.mem.exceptionAddr.isForVSnonLeafPTE 478 csrio.externalInterrupt := RegNext(io.fromTop.externalInterrupt) 479 csrio.perf <> io.perf 480 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 481 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 482 private val fenceio = intExuBlock.io.fenceio.get 483 io.fenceio <> fenceio 484 485 // to fpExuBlock 486 fpExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 487 for (i <- 0 until fpExuBlock.io.in.length) { 488 for (j <- 0 until fpExuBlock.io.in(i).length) { 489 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.fp(i)(j).bits.loadDependency, io.mem.ldCancel) 490 NewPipelineConnect( 491 bypassNetwork.io.toExus.fp(i)(j), fpExuBlock.io.in(i)(j), fpExuBlock.io.in(i)(j).fire, 492 Mux( 493 bypassNetwork.io.toExus.fp(i)(j).fire, 494 bypassNetwork.io.toExus.fp(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 495 fpExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 496 ), 497 Option("bypassNetwork2fpExuBlock") 498 ) 499 } 500 } 501 502 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 503 for (i <- 0 until vfExuBlock.io.in.size) { 504 for (j <- 0 until vfExuBlock.io.in(i).size) { 505 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 506 NewPipelineConnect( 507 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 508 Mux( 509 bypassNetwork.io.toExus.vf(i)(j).fire, 510 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 511 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 512 ), 513 Option("bypassNetwork2vfExuBlock") 514 ) 515 516 } 517 } 518 519 intExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 520 fpExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 521 fpExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 522 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 523 vfExuBlock.io.vxrm.foreach(_ := csrio.vpu.vxrm) 524 525 wbDataPath.io.flush := ctrlBlock.io.redirect 526 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 527 wbDataPath.io.fromIntExu <> intExuBlock.io.out 528 wbDataPath.io.fromFpExu <> fpExuBlock.io.out 529 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 530 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 531 sink.valid := source.valid 532 source.ready := sink.ready 533 sink.bits.data := VecInit(Seq.fill(sink.bits.params.wbPathNum)(source.bits.data)) 534 sink.bits.pdest := source.bits.uop.pdest 535 sink.bits.robIdx := source.bits.uop.robIdx 536 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 537 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 538 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 539 sink.bits.v0Wen.foreach(_ := source.bits.uop.v0Wen) 540 sink.bits.vlWen.foreach(_ := source.bits.uop.vlWen) 541 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 542 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 543 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 544 sink.bits.debug := source.bits.debug 545 sink.bits.debugInfo := source.bits.uop.debugInfo 546 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 547 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 548 sink.bits.predecodeInfo.foreach(_ := source.bits.uop.preDecodeInfo) 549 sink.bits.vls.foreach(x => { 550 x.vdIdx := source.bits.vdIdx.get 551 x.vdIdxInField := source.bits.vdIdxInField.get 552 x.vpu := source.bits.uop.vpu 553 x.oldVdPsrc := source.bits.uop.psrc(2) 554 x.isIndexed := VlduType.isIndexed(source.bits.uop.fuOpType) 555 x.isMasked := VlduType.isMasked(source.bits.uop.fuOpType) 556 }) 557 sink.bits.trigger.foreach(_ := source.bits.uop.trigger) 558 } 559 560 // to mem 561 private val memIssueParams = params.memSchdParams.get.issueBlockParams 562 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(x => x.hasLoadFu || x.hasHyldaFu)) 563 private val memExuBlocksHasVecLoad = memIssueParams.map(_.exuBlockParams.map(x => x.hasVLoadFu)) 564 println(s"[Backend] memExuBlocksHasLDU: $memExuBlocksHasLDU") 565 println(s"[Backend] memExuBlocksHasVecLoad: $memExuBlocksHasVecLoad") 566 567 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 568 for (i <- toMem.indices) { 569 for (j <- toMem(i).indices) { 570 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 571 val issueTimeout = 572 if (memExuBlocksHasLDU(i)(j)) 573 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 574 else 575 false.B 576 577 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 578 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 579 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 580 memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block 581 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 582 memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) 583 memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 584 memScheduler.io.loadFinalIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 585 } 586 587 NewPipelineConnect( 588 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 589 Mux( 590 bypassNetwork.io.toExus.mem(i)(j).fire, 591 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 592 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 593 ), 594 Option("bypassNetwork2toMemExus") 595 ) 596 597 if (memScheduler.io.memAddrIssueResp(i).nonEmpty && memExuBlocksHasLDU(i)(j)) { 598 memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) 599 memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 600 memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 601 memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) 602 memScheduler.io.memAddrIssueResp(i)(j).bits.lqIdx.foreach(_ := toMem(i)(j).bits.lqIdx.get) 603 memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully 604 } 605 606 if (memScheduler.io.vecLoadIssueResp(i).nonEmpty && memExuBlocksHasVecLoad(i)(j)) { 607 memScheduler.io.vecLoadIssueResp(i)(j) match { 608 case resp => 609 resp.valid := toMem(i)(j).fire && VlduType.isVecLd(toMem(i)(j).bits.fuOpType) 610 resp.bits.fuType := toMem(i)(j).bits.fuType 611 resp.bits.robIdx := toMem(i)(j).bits.robIdx 612 resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx 613 resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get 614 resp.bits.lqIdx.get := toMem(i)(j).bits.lqIdx.get 615 resp.bits.resp := RespType.success 616 } 617 if (backendParams.debugEn){ 618 dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) 619 } 620 } 621 } 622 } 623 624 io.mem.redirect := ctrlBlock.io.redirect 625 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 626 val enableMdp = Constantin.createRecord("EnableMdp", true) 627 sink.valid := source.valid 628 source.ready := sink.ready 629 sink.bits.iqIdx := source.bits.iqIdx 630 sink.bits.isFirstIssue := source.bits.isFirstIssue 631 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 632 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 633 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 634 sink.bits.uop.fuType := source.bits.fuType 635 sink.bits.uop.fuOpType := source.bits.fuOpType 636 sink.bits.uop.imm := source.bits.imm 637 sink.bits.uop.robIdx := source.bits.robIdx 638 sink.bits.uop.pdest := source.bits.pdest 639 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 640 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 641 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 642 sink.bits.uop.v0Wen := source.bits.v0Wen.getOrElse(false.B) 643 sink.bits.uop.vlWen := source.bits.vlWen.getOrElse(false.B) 644 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 645 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 646 sink.bits.uop.loadWaitBit := Mux(enableMdp, source.bits.loadWaitBit.getOrElse(false.B), false.B) 647 sink.bits.uop.waitForRobIdx := Mux(enableMdp, source.bits.waitForRobIdx.getOrElse(0.U.asTypeOf(new RobPtr)), 0.U.asTypeOf(new RobPtr)) 648 sink.bits.uop.storeSetHit := Mux(enableMdp, source.bits.storeSetHit.getOrElse(false.B), false.B) 649 sink.bits.uop.loadWaitStrict := Mux(enableMdp, source.bits.loadWaitStrict.getOrElse(false.B), false.B) 650 sink.bits.uop.ssid := Mux(enableMdp, source.bits.ssid.getOrElse(0.U(SSIDWidth.W)), 0.U(SSIDWidth.W)) 651 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 652 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 653 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 654 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 655 sink.bits.uop.debugInfo := source.bits.perfDebugInfo 656 sink.bits.uop.vpu := source.bits.vpu.getOrElse(0.U.asTypeOf(new VPUCtrlSignals)) 657 sink.bits.uop.preDecodeInfo := source.bits.preDecode.getOrElse(0.U.asTypeOf(new PreDecodeInfo)) 658 sink.bits.uop.numLsElem := source.bits.numLsElem.getOrElse(0.U) // Todo: remove this bundle, keep only the one below 659 sink.bits.flowNum.foreach(_ := source.bits.numLsElem.get) 660 } 661 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 662 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 663 io.mem.tlbCsr := csrio.tlb 664 io.mem.csrCtrl := csrio.customCtrl 665 io.mem.sfence := fenceio.sfence 666 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 667 io.mem.isVlsException := ctrlBlock.io.robio.exception.bits.vls 668 require(io.mem.loadPcRead.size == params.LduCnt) 669 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 670 loadPcRead := ctrlBlock.io.memLdPcRead(i).data 671 ctrlBlock.io.memLdPcRead(i).valid := io.mem.issueLda(i).valid 672 ctrlBlock.io.memLdPcRead(i).ptr := io.mem.issueLda(i).bits.uop.ftqPtr 673 ctrlBlock.io.memLdPcRead(i).offset := io.mem.issueLda(i).bits.uop.ftqOffset 674 } 675 676 io.mem.storePcRead.zipWithIndex.foreach { case (storePcRead, i) => 677 storePcRead := ctrlBlock.io.memStPcRead(i).data 678 ctrlBlock.io.memStPcRead(i).valid := io.mem.issueSta(i).valid 679 ctrlBlock.io.memStPcRead(i).ptr := io.mem.issueSta(i).bits.uop.ftqPtr 680 ctrlBlock.io.memStPcRead(i).offset := io.mem.issueSta(i).bits.uop.ftqOffset 681 } 682 683 io.mem.hyuPcRead.zipWithIndex.foreach( { case (hyuPcRead, i) => 684 hyuPcRead := ctrlBlock.io.memHyPcRead(i).data 685 ctrlBlock.io.memHyPcRead(i).valid := io.mem.issueHylda(i).valid 686 ctrlBlock.io.memHyPcRead(i).ptr := io.mem.issueHylda(i).bits.uop.ftqPtr 687 ctrlBlock.io.memHyPcRead(i).offset := io.mem.issueHylda(i).bits.uop.ftqOffset 688 }) 689 690 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 691 692 // mem io 693 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 694 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 695 696 io.frontendSfence := fenceio.sfence 697 io.frontendTlbCsr := csrio.tlb 698 io.frontendCsrCtrl := csrio.customCtrl 699 700 io.tlb <> csrio.tlb 701 702 io.csrCustomCtrl := csrio.customCtrl 703 704 io.toTop.cpuHalted := false.B // TODO: implement cpu halt 705 706 io.debugTopDown.fromRob := ctrlBlock.io.debugTopDown.fromRob 707 ctrlBlock.io.debugTopDown.fromCore := io.debugTopDown.fromCore 708 709 io.debugRolling := ctrlBlock.io.debugRolling 710 711 if(backendParams.debugEn) { 712 dontTouch(memScheduler.io) 713 dontTouch(dataPath.io.toMemExu) 714 dontTouch(wbDataPath.io.fromMemExu) 715 } 716 717 // reset tree 718 if (p(DebugOptionsKey).ResetGen) { 719 val rightResetTree = ResetGenNode(Seq( 720 ModuleNode(dataPath), 721 ModuleNode(intExuBlock), 722 ModuleNode(fpExuBlock), 723 ModuleNode(vfExuBlock), 724 ModuleNode(bypassNetwork), 725 ModuleNode(wbDataPath) 726 )) 727 val leftResetTree = ResetGenNode(Seq( 728 ModuleNode(pcTargetMem), 729 ModuleNode(intScheduler), 730 ModuleNode(fpScheduler), 731 ModuleNode(vfScheduler), 732 ModuleNode(memScheduler), 733 ModuleNode(og2ForVector), 734 ModuleNode(wbFuBusyTable), 735 ResetGenNode(Seq( 736 ModuleNode(ctrlBlock), 737 // ResetGenNode(Seq( 738 CellNode(io.frontendReset) 739 // )) 740 )) 741 )) 742 ResetGen(leftResetTree, reset, sim = false) 743 ResetGen(rightResetTree, reset, sim = false) 744 } else { 745 io.frontendReset := DontCare 746 } 747 748 // perf events 749 val pfevent = Module(new PFEvent) 750 pfevent.io.distribute_csr := RegNext(csrio.customCtrl.distribute_csr) 751 val csrevents = pfevent.io.hpmevent.slice(8,16) 752 753 val ctrlBlockPerf = ctrlBlock.getPerfEvents 754 val intSchedulerPerf = intScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 755 val fpSchedulerPerf = fpScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 756 val vecSchedulerPerf = vfScheduler.asInstanceOf[SchedulerArithImp].getPerfEvents 757 val memSchedulerPerf = memScheduler.asInstanceOf[SchedulerMemImp].getPerfEvents 758 759 val perfBackend = Seq() 760 // let index = 0 be no event 761 val allPerfEvents = Seq(("noEvent", 0.U)) ++ ctrlBlockPerf ++ intSchedulerPerf ++ fpSchedulerPerf ++ vecSchedulerPerf ++ memSchedulerPerf ++ perfBackend 762 763 764 if (printEventCoding) { 765 for (((name, inc), i) <- allPerfEvents.zipWithIndex) { 766 println("backend perfEvents Set", name, inc, i) 767 } 768 } 769 770 val allPerfInc = allPerfEvents.map(_._2.asTypeOf(new PerfEvent)) 771 val perfEvents = HPerfMonitor(csrevents, allPerfInc).getPerfEvents 772 csrio.perf.perfEventsBackend := VecInit(perfEvents.map(_._2.asTypeOf(new PerfEvent))) 773 generatePerfEvent() 774} 775 776class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 777 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts 778 val flippedLda = true 779 // params alias 780 private val LoadQueueSize = VirtualLoadQueueSize 781 // In/Out // Todo: split it into one-direction bundle 782 val lsqEnqIO = Flipped(new LsqEnqIO) 783 val robLsqIO = new RobLsqIO 784 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 785 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 786 val hyuIqFeedback = Vec(params.HyuCnt, Flipped(new MemRSFeedbackIO)) 787 val vstuIqFeedback = Flipped(Vec(params.VstuCnt, new MemRSFeedbackIO(isVector = true))) 788 val vlduIqFeedback = Flipped(Vec(params.VlduCnt, new MemRSFeedbackIO(isVector = true))) 789 val ldCancel = Vec(params.LdExuCnt, Input(new LoadCancelIO)) 790 val wakeup = Vec(params.LdExuCnt, Flipped(Valid(new DynInst))) 791 val loadPcRead = Vec(params.LduCnt, Output(UInt(VAddrBits.W))) 792 val storePcRead = Vec(params.StaCnt, Output(UInt(VAddrBits.W))) 793 val hyuPcRead = Vec(params.HyuCnt, Output(UInt(VAddrBits.W))) 794 // Input 795 val writebackLda = Vec(params.LduCnt, Flipped(DecoupledIO(new MemExuOutput))) 796 val writebackSta = Vec(params.StaCnt, Flipped(DecoupledIO(new MemExuOutput))) 797 val writebackStd = Vec(params.StdCnt, Flipped(DecoupledIO(new MemExuOutput))) 798 val writebackHyuLda = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 799 val writebackHyuSta = Vec(params.HyuCnt, Flipped(DecoupledIO(new MemExuOutput))) 800 val writebackVldu = Vec(params.VlduCnt, Flipped(DecoupledIO(new MemExuOutput(true)))) 801 802 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 803 val stIn = Input(Vec(params.StaExuCnt, ValidIO(new DynInst()))) 804 val memoryViolation = Flipped(ValidIO(new Redirect)) 805 val exceptionAddr = Input(new Bundle { 806 val vaddr = UInt(XLEN.W) 807 val gpaddr = UInt(XLEN.W) 808 val isForVSnonLeafPTE = Bool() 809 }) 810 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 811 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 812 val sqDeqPtr = Input(new SqPtr) 813 val lqDeqPtr = Input(new LqPtr) 814 815 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 816 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 817 818 val lqCanAccept = Input(Bool()) 819 val sqCanAccept = Input(Bool()) 820 821 val otherFastWakeup = Flipped(Vec(params.LduCnt + params.HyuCnt, ValidIO(new DynInst))) 822 val stIssuePtr = Input(new SqPtr()) 823 824 val debugLS = Flipped(Output(new DebugLSIO)) 825 826 val lsTopdownInfo = Vec(params.LduCnt + params.HyuCnt, Flipped(Output(new LsTopdownInfo))) 827 // Output 828 val redirect = ValidIO(new Redirect) // rob flush MemBlock 829 val issueLda = MixedVec(Seq.fill(params.LduCnt)(DecoupledIO(new MemExuInput()))) 830 val issueSta = MixedVec(Seq.fill(params.StaCnt)(DecoupledIO(new MemExuInput()))) 831 val issueStd = MixedVec(Seq.fill(params.StdCnt)(DecoupledIO(new MemExuInput()))) 832 val issueHylda = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 833 val issueHysta = MixedVec(Seq.fill(params.HyuCnt)(DecoupledIO(new MemExuInput()))) 834 val issueVldu = MixedVec(Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 835 836 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 837 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 838 839 val tlbCsr = Output(new TlbCsrBundle) 840 val csrCtrl = Output(new CustomCSRCtrlIO) 841 val sfence = Output(new SfenceBundle) 842 val isStoreException = Output(Bool()) 843 val isVlsException = Output(Bool()) 844 845 // ATTENTION: The issue ports' sequence order should be the same as IQs' deq config 846 private [backend] def issueUops: Seq[DecoupledIO[MemExuInput]] = { 847 issueSta ++ 848 issueHylda ++ issueHysta ++ 849 issueLda ++ 850 issueVldu ++ 851 issueStd 852 }.toSeq 853 854 // ATTENTION: The writeback ports' sequence order should be the same as IQs' deq config 855 private [backend] def writeBack: Seq[DecoupledIO[MemExuOutput]] = { 856 writebackSta ++ 857 writebackHyuLda ++ writebackHyuSta ++ 858 writebackLda ++ 859 writebackVldu ++ 860 writebackStd 861 } 862} 863 864class TopToBackendBundle(implicit p: Parameters) extends XSBundle { 865 val hartId = Output(UInt(hartIdLen.W)) 866 val externalInterrupt = Output(new ExternalInterruptIO) 867 val msiInfo = Output(ValidIO(new MsiInfoBundle)) 868 val clintTime = Output(ValidIO(UInt(64.W))) 869} 870 871class BackendToTopBundle extends Bundle { 872 val cpuHalted = Output(Bool()) 873} 874 875class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter { 876 val fromTop = Flipped(new TopToBackendBundle) 877 878 val toTop = new BackendToTopBundle 879 880 val fenceio = new FenceIO 881 // Todo: merge these bundles into BackendFrontendIO 882 val frontend = Flipped(new FrontendToCtrlIO) 883 val frontendSfence = Output(new SfenceBundle) 884 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 885 val frontendTlbCsr = Output(new TlbCsrBundle) 886 val frontendReset = Output(Reset()) 887 888 val mem = new BackendMemIO 889 890 val perf = Input(new PerfCounterIO) 891 892 val tlb = Output(new TlbCsrBundle) 893 894 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 895 896 val debugTopDown = new Bundle { 897 val fromRob = new RobCoreTopDownIO 898 val fromCore = new CoreDispatchTopDownIO 899 } 900 val debugRolling = new RobDebugRollingIO 901} 902