xref: /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala (revision 46e9ee74b05bff567ec23c58a1dde7151176258f) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:
9*          http://license.coscl.org.cn/MulanPSL2
10*
11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
14*
15* See the Mulan PSL v2 for more details.
16***************************************************************************************/
17
18package xiangshan.mem
19
20
21import org.chipsalliance.cde.config.Parameters
22import chisel3._
23import chisel3.util._
24import utility._
25import utils._
26import xiangshan._
27import xiangshan.backend.Bundles.{DynInst, MemExuInput}
28import xiangshan.backend.rob.RobPtr
29import xiangshan.cache._
30import xiangshan.backend.fu.FenceToSbuffer
31import xiangshan.cache.wpu.ReplayCarry
32import xiangshan.mem.prefetch.PrefetchReqBundle
33import math._
34
35object genWmask {
36  def apply(addr: UInt, sizeEncode: UInt): UInt = {
37    (LookupTree(sizeEncode, List(
38      "b00".U -> 0x1.U, //0001 << addr(2:0)
39      "b01".U -> 0x3.U, //0011
40      "b10".U -> 0xf.U, //1111
41      "b11".U -> 0xff.U //11111111
42    )) << addr(2, 0)).asUInt
43  }
44}
45
46object genVWmask {
47  def apply(addr: UInt, sizeEncode: UInt): UInt = {
48    (LookupTree(sizeEncode, List(
49      "b00".U -> 0x1.U, //0001 << addr(2:0)
50      "b01".U -> 0x3.U, //0011
51      "b10".U -> 0xf.U, //1111
52      "b11".U -> 0xff.U //11111111
53    )) << addr(3, 0)).asUInt
54  }
55}
56
57object genWdata {
58  def apply(data: UInt, sizeEncode: UInt): UInt = {
59    LookupTree(sizeEncode, List(
60      "b00".U -> Fill(16, data(7, 0)),
61      "b01".U -> Fill(8, data(15, 0)),
62      "b10".U -> Fill(4, data(31, 0)),
63      "b11".U -> Fill(2, data(63,0))
64    ))
65  }
66}
67
68object shiftDataToLow {
69  def apply(addr: UInt,data : UInt): UInt = {
70    Mux(addr(3), (data >> 64).asUInt,data)
71  }
72}
73object shiftMaskToLow {
74  def apply(addr: UInt,mask: UInt): UInt = {
75    Mux(addr(3),(mask >> 8).asUInt,mask)
76  }
77}
78
79class LsPipelineBundle(implicit p: Parameters) extends XSBundle
80  with HasDCacheParameters
81  with HasVLSUParameters {
82  val uop = new DynInst
83  val vaddr = UInt(VAddrBits.W)
84  // For exception vaddr generate
85  val fullva = UInt(XLEN.W)
86  val vaNeedExt = Bool()
87  val isHyper = Bool()
88  val paddr = UInt(PAddrBits.W)
89  val gpaddr = UInt(XLEN.W)
90  val isForVSnonLeafPTE = Bool()
91  // val func = UInt(6.W)
92  val mask = UInt((VLEN/8).W)
93  val data = UInt((VLEN+1).W)
94  val wlineflag = Bool() // store write the whole cache line
95
96  val miss = Bool()
97  val tlbMiss = Bool()
98  val ptwBack = Bool()
99  val af = Bool()
100  val mmio = Bool()
101  val atomic = Bool()
102
103  val forwardMask = Vec(VLEN/8, Bool())
104  val forwardData = Vec(VLEN/8, UInt(8.W))
105
106  // prefetch
107  val isPrefetch = Bool()
108  val isHWPrefetch = Bool()
109  def isSWPrefetch = isPrefetch && !isHWPrefetch
110
111  // misalignBuffer
112  val isFrmMisAlignBuf = Bool()
113
114  // vector
115  val isvec = Bool()
116  val isLastElem = Bool()
117  val is128bit = Bool()
118  val uop_unit_stride_fof = Bool()
119  val usSecondInv = Bool()
120  val elemIdx = UInt(elemIdxBits.W)
121  val alignedType = UInt(alignTypeBits.W)
122  val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W)
123  // val rob_idx_valid = Vec(2,Bool())
124  // val inner_idx = Vec(2,UInt(3.W))
125  // val rob_idx = Vec(2,new RobPtr)
126  val reg_offset = UInt(vOffsetBits.W)
127  val elemIdxInsideVd = UInt(elemIdxBits.W)
128  // val offset = Vec(2,UInt(4.W))
129  val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element
130  val is_first_ele = Bool()
131  // val flowPtr = new VlflowPtr() // VLFlowQueue ptr
132  // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr
133
134  // For debug usage
135  val isFirstIssue = Bool()
136  val hasROBEntry = Bool()
137
138  // For load replay
139  val isLoadReplay = Bool()
140  val isFastPath = Bool()
141  val isFastReplay = Bool()
142  val replayCarry = new ReplayCarry(nWays)
143
144  // For dcache miss load
145  val mshrid = UInt(log2Up(cfg.nMissEntries).W)
146  val handledByMSHR = Bool()
147  val replacementUpdated = Bool()
148  val missDbUpdated = Bool()
149
150  val forward_tlDchannel = Bool()
151  val dcacheRequireReplay = Bool()
152  val delayedLoadError = Bool()
153  val lateKill = Bool()
154  val feedbacked = Bool()
155  val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W))
156  // loadQueueReplay index.
157  val schedIndex = UInt(log2Up(LoadQueueReplaySize).W)
158  // hardware prefetch and fast replay no need to query tlb
159  val tlbNoQuery = Bool()
160}
161
162class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle {
163  val meta_prefetch = UInt(L1PfSourceBits.W)
164  val meta_access = Bool()
165
166  def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = {
167    if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr
168    if (latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva
169    if (latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt
170    if (latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper
171    if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr
172    if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr
173    if (latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE
174    if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask
175    if (latch) data := RegEnable(input.data, enable) else data := input.data
176    if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop
177    if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag
178    if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss
179    if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss
180    if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack
181    if (latch) af := RegEnable(input.af, enable) else af := input.af
182    if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio
183    if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask
184    if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData
185    if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch
186    if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch
187    if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf
188    if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue
189    if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry
190    if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay
191    if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex
192    if (latch) tlbNoQuery := RegEnable(input.tlbNoQuery, enable) else tlbNoQuery := input.tlbNoQuery
193    if (latch) isvec               := RegEnable(input.isvec, enable)               else isvec               := input.isvec
194    if (latch) isLastElem          := RegEnable(input.isLastElem, enable)          else isLastElem          := input.isLastElem
195    if (latch) is128bit            := RegEnable(input.is128bit, enable)            else is128bit            := input.is128bit
196    if (latch) vecActive           := RegEnable(input.vecActive, enable)           else vecActive           := input.vecActive
197    if (latch) is_first_ele        := RegEnable(input.is_first_ele, enable)        else is_first_ele        := input.is_first_ele
198    if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof
199    if (latch) usSecondInv         := RegEnable(input.usSecondInv, enable)         else usSecondInv         := input.usSecondInv
200    if (latch) reg_offset          := RegEnable(input.reg_offset, enable)          else reg_offset          := input.reg_offset
201    if (latch) elemIdx             := RegEnable(input.elemIdx, enable)             else elemIdx             := input.elemIdx
202    if (latch) alignedType         := RegEnable(input.alignedType, enable)         else alignedType         := input.alignedType
203    if (latch) mbIndex             := RegEnable(input.mbIndex, enable)             else mbIndex             := input.mbIndex
204    if (latch) elemIdxInsideVd     := RegEnable(input.elemIdxInsideVd, enable)     else elemIdxInsideVd     := input.elemIdxInsideVd
205    // if (latch) flowPtr             := RegEnable(input.flowPtr, enable)             else flowPtr             := input.flowPtr
206    // if (latch) sflowPtr            := RegEnable(input.sflowPtr, enable)            else sflowPtr            := input.sflowPtr
207
208    meta_prefetch := DontCare
209    meta_access := DontCare
210    forward_tlDchannel := DontCare
211    mshrid := DontCare
212    replayCarry := DontCare
213    atomic := DontCare
214    isLoadReplay := DontCare
215    isFastPath := DontCare
216    isFastReplay := DontCare
217    handledByMSHR := DontCare
218    replacementUpdated := DontCare
219    missDbUpdated := DontCare
220    delayedLoadError := DontCare
221    lateKill := DontCare
222    feedbacked := DontCare
223    ldCancel := DontCare
224  }
225
226  def asPrefetchReqBundle(): PrefetchReqBundle = {
227    val res = Wire(new PrefetchReqBundle)
228    res.vaddr       := this.vaddr
229    res.paddr       := this.paddr
230    res.pc          := this.uop.pc
231    res.miss        := this.miss
232    res.pfHitStream := isFromStream(this.meta_prefetch)
233
234    res
235  }
236}
237
238class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {}
239
240class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle {
241  // load inst replay informations
242  val rep_info = new LoadToLsqReplayIO
243  // queue entry data, except flag bits, will be updated if writeQueue is true,
244  // valid bit in LqWriteBundle will be ignored
245  val data_wen_dup = Vec(6, Bool()) // dirty reg dup
246
247
248  def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = {
249    if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr
250    if(latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva
251    if(latch) vaNeedExt := RegEnable(input.vaNeedExt, enable) else vaNeedExt := input.vaNeedExt
252    if(latch) isHyper := RegEnable(input.isHyper, enable) else isHyper := input.isHyper
253    if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr
254    if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr
255    if(latch) isForVSnonLeafPTE := RegEnable(input.isForVSnonLeafPTE, enable) else isForVSnonLeafPTE := input.isForVSnonLeafPTE
256    if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask
257    if(latch) data := RegEnable(input.data, enable) else data := input.data
258    if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop
259    if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag
260    if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss
261    if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss
262    if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack
263    if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio
264    if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic
265    if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask
266    if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData
267    if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch
268    if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch
269    if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf
270    if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue
271    if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry
272    if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay
273    if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath
274    if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay
275    if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid
276    if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel
277    if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry
278    if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay
279    if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex
280    if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR
281    if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated
282    if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated
283    if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError
284    if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill
285    if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked
286    if(latch) isvec               := RegEnable(input.isvec, enable)               else isvec               := input.isvec
287    if(latch) is128bit            := RegEnable(input.is128bit, enable)            else is128bit            := input.is128bit
288    if(latch) vecActive           := RegEnable(input.vecActive, enable)           else vecActive           := input.vecActive
289    if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof
290    if(latch) reg_offset          := RegEnable(input.reg_offset, enable)          else reg_offset          := input.reg_offset
291    if(latch) mbIndex             := RegEnable(input.mbIndex, enable)             else mbIndex             := input.mbIndex
292    if(latch) elemIdxInsideVd     := RegEnable(input.elemIdxInsideVd, enable)     else elemIdxInsideVd     := input.elemIdxInsideVd
293
294    rep_info := DontCare
295    data_wen_dup := DontCare
296  }
297}
298
299class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle {
300  val need_rep = Bool()
301}
302
303class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle {
304  val vaddr = Output(UInt(VAddrBits.W))
305  val paddr = Output(UInt(PAddrBits.W))
306  val mask = Output(UInt((VLEN/8).W))
307  val uop = Output(new DynInst) // for replay
308  val pc = Output(UInt(VAddrBits.W)) //for debug
309  val valid = Output(Bool())
310
311  val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1
312  val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2
313  val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2
314
315  // val lqIdx = Output(UInt(LoadQueueIdxWidth.W))
316  val sqIdx = Output(new SqPtr)
317
318  // dataInvalid suggests store to load forward found forward should happen,
319  // but data is not available for now. If dataInvalid, load inst should
320  // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid
321  val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now
322
323  // matchInvalid suggests in store to load forward logic, paddr cam result does
324  // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception
325  // should be raised to flush SQ and committed sbuffer.
326  val matchInvalid = Input(Bool()) // resp to load_s2
327
328  // addrInvalid suggests store to load forward found forward should happen,
329  // but address (SSID) is not available for now. If addrInvalid, load inst should
330  // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid
331  val addrInvalid = Input(Bool())
332}
333
334// LoadForwardQueryIO used in load pipeline
335//
336// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO:
337// PipeIO use predecoded sqIdxMask for better forward timing
338class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO {
339  // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons
340  // sqIdxMask is calcuated in earlier stage for better timing
341  val sqIdxMask = Output(UInt(StoreQueueSize.W))
342
343  // dataInvalid: addr match, but data is not valid for now
344  val dataInvalidFast = Input(Bool()) // resp to load_s1
345  // val dataInvalid = Input(Bool()) // resp to load_s2
346  val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx
347  val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx
348}
349
350// Query load queue for ld-ld violation
351//
352// Req should be send in load_s1
353// Resp will be generated 1 cycle later
354//
355// Note that query req may be !ready, as dcache is releasing a block
356// If it happens, a replay from rs is needed.
357class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx
358  val uop = new DynInst
359  // mask: load's data mask.
360  val mask = UInt((VLEN/8).W)
361
362  // paddr: load's paddr.
363  val paddr      = UInt(PAddrBits.W)
364  // dataInvalid: load data is invalid.
365  val data_valid = Bool()
366}
367
368class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle {
369  // rep_frm_fetch: ld-ld violation check success, replay from fetch.
370  val rep_frm_fetch = Bool()
371}
372
373class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle {
374  val req    = Decoupled(new LoadNukeQueryReq)
375  val resp   = Flipped(Valid(new LoadNukeQueryResp))
376  val revoke = Output(Bool())
377}
378
379class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle {
380  //  robIdx: Requestor's (a store instruction) rob index for match logic.
381  val robIdx = new RobPtr
382
383  //  paddr: requestor's (a store instruction) physical address for match logic.
384  val paddr  = UInt(PAddrBits.W)
385
386  //  mask: requestor's (a store instruction) data width mask for match logic.
387  val mask = UInt((VLEN/8).W)
388
389  // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr.
390  val matchLine = Bool()
391}
392
393class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle {
394  // from storeMisalignBuffer to storeQueue, control it's sbuffer write
395  val control = Output(new XSBundle {
396    // control sq to write-into sb
397    val writeSb = Bool()
398    val wdata = UInt(VLEN.W)
399    val wmask = UInt((VLEN / 8).W)
400    val paddr = UInt(PAddrBits.W)
401    val vaddr = UInt(VAddrBits.W)
402    val last  = Bool()
403    val hasException = Bool()
404    // remove this entry in sq
405    val removeSq = Bool()
406  })
407  // from storeQueue to storeMisalignBuffer, provide detail info of this store
408  val storeInfo = Input(new XSBundle {
409    val data = UInt(VLEN.W)
410    // is the data of the unaligned store ready at sq?
411    val dataReady = Bool()
412    // complete a data transfer from sq to sb
413    val completeSbTrans = Bool()
414  })
415}
416
417// Store byte valid mask write bundle
418//
419// Store byte valid mask write to SQ takes 2 cycles
420class StoreMaskBundle(implicit p: Parameters) extends XSBundle {
421  val sqIdx = new SqPtr
422  val mask = UInt((VLEN/8).W)
423}
424
425class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle {
426  // old dcache: optimize data sram read fanout
427  // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W))
428  // val bank_oh = UInt(DCacheBanks.W)
429
430  // new dcache
431  val respDcacheData = UInt(VLEN.W)
432  val forwardMask = Vec(VLEN/8, Bool())
433  val forwardData = Vec(VLEN/8, UInt(8.W))
434  val uop = new DynInst // for data selection, only fwen and fuOpType are used
435  val addrOffset = UInt(4.W) // for data selection
436
437  // forward tilelink D channel
438  val forward_D = Bool()
439  val forwardData_D = Vec(VLEN/8, UInt(8.W))
440
441  // forward mshr data
442  val forward_mshr = Bool()
443  val forwardData_mshr = Vec(VLEN/8, UInt(8.W))
444
445  val forward_result_valid = Bool()
446
447  def mergeTLData(): UInt = {
448    // merge TL D or MSHR data at load s2
449    val dcache_data = respDcacheData
450    val use_D = forward_D && forward_result_valid
451    val use_mshr = forward_mshr && forward_result_valid
452    Mux(
453      use_D || use_mshr,
454      Mux(
455        use_D,
456        forwardData_D.asUInt,
457        forwardData_mshr.asUInt
458      ),
459      dcache_data
460    )
461  }
462
463  def mergeLsqFwdData(dcacheData: UInt): UInt = {
464    // merge dcache and lsq forward data at load s3
465    val rdataVec = VecInit((0 until VLEN / 8).map(j =>
466      Mux(forwardMask(j), forwardData(j), dcacheData(8*(j+1)-1, 8*j))
467    ))
468    rdataVec.asUInt
469  }
470}
471
472// Load writeback data from load queue (refill)
473class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle {
474  val lqData = UInt(64.W) // load queue has merged data
475  val uop = new DynInst // for data selection, only fwen and fuOpType are used
476  val addrOffset = UInt(3.W) // for data selection
477
478  def mergedData(): UInt = {
479    lqData
480  }
481}
482
483// Bundle for load / store wait waking up
484class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle {
485  val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr))
486  val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr))
487}
488
489object AddPipelineReg {
490  class PipelineRegModule[T <: Data](gen: T) extends Module {
491    val io = IO(new Bundle() {
492      val in = Flipped(DecoupledIO(gen.cloneType))
493      val out = DecoupledIO(gen.cloneType)
494      val isFlush = Input(Bool())
495    })
496
497    val valid = RegInit(false.B)
498    valid.suggestName("pipeline_reg_valid")
499    when (io.out.fire) { valid := false.B }
500    when (io.in.fire) { valid := true.B }
501    when (io.isFlush) { valid := false.B }
502
503    io.in.ready := !valid || io.out.ready
504    io.out.bits := RegEnable(io.in.bits, io.in.fire)
505    io.out.valid := valid //&& !isFlush
506  }
507
508  def apply[T <: Data]
509  (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool,
510   moduleName: Option[String] = None
511  ): Unit = {
512    val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType))
513    if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get)
514    pipelineReg.io.in <> left
515    right <> pipelineReg.io.out
516    pipelineReg.io.isFlush := isFlush
517  }
518}