1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package xiangshan.mem 19 20 21import org.chipsalliance.cde.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import utility._ 25import utils._ 26import xiangshan._ 27import xiangshan.backend.Bundles.{DynInst, MemExuInput} 28import xiangshan.backend.rob.RobPtr 29import xiangshan.cache._ 30import xiangshan.backend.fu.FenceToSbuffer 31import xiangshan.cache.wpu.ReplayCarry 32import xiangshan.mem.prefetch.PrefetchReqBundle 33import math._ 34 35object genWmask { 36 def apply(addr: UInt, sizeEncode: UInt): UInt = { 37 (LookupTree(sizeEncode, List( 38 "b00".U -> 0x1.U, //0001 << addr(2:0) 39 "b01".U -> 0x3.U, //0011 40 "b10".U -> 0xf.U, //1111 41 "b11".U -> 0xff.U //11111111 42 )) << addr(2, 0)).asUInt 43 } 44} 45 46object genVWmask { 47 def apply(addr: UInt, sizeEncode: UInt): UInt = { 48 (LookupTree(sizeEncode, List( 49 "b00".U -> 0x1.U, //0001 << addr(2:0) 50 "b01".U -> 0x3.U, //0011 51 "b10".U -> 0xf.U, //1111 52 "b11".U -> 0xff.U //11111111 53 )) << addr(3, 0)).asUInt 54 } 55} 56 57object genWdata { 58 def apply(data: UInt, sizeEncode: UInt): UInt = { 59 LookupTree(sizeEncode, List( 60 "b00".U -> Fill(16, data(7, 0)), 61 "b01".U -> Fill(8, data(15, 0)), 62 "b10".U -> Fill(4, data(31, 0)), 63 "b11".U -> Fill(2, data(63,0)) 64 )) 65 } 66} 67 68object shiftDataToLow { 69 def apply(addr: UInt,data : UInt): UInt = { 70 Mux(addr(3), (data >> 64).asUInt,data) 71 } 72} 73object shiftMaskToLow { 74 def apply(addr: UInt,mask: UInt): UInt = { 75 Mux(addr(3),(mask >> 8).asUInt,mask) 76 } 77} 78 79class LsPipelineBundle(implicit p: Parameters) extends XSBundle 80 with HasDCacheParameters 81 with HasVLSUParameters { 82 val uop = new DynInst 83 val vaddr = UInt(VAddrBits.W) 84 val fullva = UInt(XLEN.W) 85 val paddr = UInt(PAddrBits.W) 86 val gpaddr = UInt(XLEN.W) 87 // val func = UInt(6.W) 88 val mask = UInt((VLEN/8).W) 89 val data = UInt((VLEN+1).W) 90 val wlineflag = Bool() // store write the whole cache line 91 92 val miss = Bool() 93 val tlbMiss = Bool() 94 val ptwBack = Bool() 95 val af = Bool() 96 val mmio = Bool() 97 val atomic = Bool() 98 99 val forwardMask = Vec(VLEN/8, Bool()) 100 val forwardData = Vec(VLEN/8, UInt(8.W)) 101 102 // prefetch 103 val isPrefetch = Bool() 104 val isHWPrefetch = Bool() 105 def isSWPrefetch = isPrefetch && !isHWPrefetch 106 107 // misalignBuffer 108 val isFrmMisAlignBuf = Bool() 109 110 // vector 111 val isvec = Bool() 112 val isLastElem = Bool() 113 val is128bit = Bool() 114 val uop_unit_stride_fof = Bool() 115 val usSecondInv = Bool() 116 val elemIdx = UInt(elemIdxBits.W) 117 val alignedType = UInt(alignTypeBits.W) 118 val mbIndex = UInt(max(vlmBindexBits, vsmBindexBits).W) 119 // val rob_idx_valid = Vec(2,Bool()) 120 // val inner_idx = Vec(2,UInt(3.W)) 121 // val rob_idx = Vec(2,new RobPtr) 122 val reg_offset = UInt(vOffsetBits.W) 123 val elemIdxInsideVd = UInt(elemIdxBits.W) 124 // val offset = Vec(2,UInt(4.W)) 125 val vecActive = Bool() // 1: vector active element or scala mem operation, 0: vector not active element 126 val is_first_ele = Bool() 127 // val flowPtr = new VlflowPtr() // VLFlowQueue ptr 128 // val sflowPtr = new VsFlowPtr() // VSFlowQueue ptr 129 130 // For debug usage 131 val isFirstIssue = Bool() 132 val hasROBEntry = Bool() 133 134 // For load replay 135 val isLoadReplay = Bool() 136 val isFastPath = Bool() 137 val isFastReplay = Bool() 138 val replayCarry = new ReplayCarry(nWays) 139 140 // For dcache miss load 141 val mshrid = UInt(log2Up(cfg.nMissEntries).W) 142 val handledByMSHR = Bool() 143 val replacementUpdated = Bool() 144 val missDbUpdated = Bool() 145 146 val forward_tlDchannel = Bool() 147 val dcacheRequireReplay = Bool() 148 val delayedLoadError = Bool() 149 val lateKill = Bool() 150 val feedbacked = Bool() 151 val ldCancel = ValidUndirectioned(UInt(log2Ceil(LoadPipelineWidth).W)) 152 // loadQueueReplay index. 153 val schedIndex = UInt(log2Up(LoadQueueReplaySize).W) 154 // hardware prefetch and fast replay no need to query tlb 155 val tlbNoQuery = Bool() 156} 157 158class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { 159 val meta_prefetch = UInt(L1PfSourceBits.W) 160 val meta_access = Bool() 161 162 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 163 if (latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 164 if (latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 165 if (latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 166 if (latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 167 if (latch) mask := RegEnable(input.mask, enable) else mask := input.mask 168 if (latch) data := RegEnable(input.data, enable) else data := input.data 169 if (latch) uop := RegEnable(input.uop, enable) else uop := input.uop 170 if (latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 171 if (latch) miss := RegEnable(input.miss, enable) else miss := input.miss 172 if (latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 173 if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 174 if (latch) af := RegEnable(input.af, enable) else af := input.af 175 if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 176 if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 177 if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 178 if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 179 if (latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 180 if (latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 181 if (latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 182 if (latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 183 if (latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 184 if (latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 185 if (latch) tlbNoQuery := RegEnable(input.tlbNoQuery, enable) else tlbNoQuery := input.tlbNoQuery 186 if (latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 187 if (latch) isLastElem := RegEnable(input.isLastElem, enable) else isLastElem := input.isLastElem 188 if (latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 189 if (latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 190 if (latch) is_first_ele := RegEnable(input.is_first_ele, enable) else is_first_ele := input.is_first_ele 191 if (latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 192 if (latch) usSecondInv := RegEnable(input.usSecondInv, enable) else usSecondInv := input.usSecondInv 193 if (latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 194 if (latch) elemIdx := RegEnable(input.elemIdx, enable) else elemIdx := input.elemIdx 195 if (latch) alignedType := RegEnable(input.alignedType, enable) else alignedType := input.alignedType 196 if (latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 197 if (latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 198 // if (latch) flowPtr := RegEnable(input.flowPtr, enable) else flowPtr := input.flowPtr 199 // if (latch) sflowPtr := RegEnable(input.sflowPtr, enable) else sflowPtr := input.sflowPtr 200 201 meta_prefetch := DontCare 202 meta_access := DontCare 203 forward_tlDchannel := DontCare 204 mshrid := DontCare 205 replayCarry := DontCare 206 atomic := DontCare 207 isLoadReplay := DontCare 208 isFastPath := DontCare 209 isFastReplay := DontCare 210 handledByMSHR := DontCare 211 replacementUpdated := DontCare 212 missDbUpdated := DontCare 213 delayedLoadError := DontCare 214 lateKill := DontCare 215 feedbacked := DontCare 216 ldCancel := DontCare 217 } 218 219 def asPrefetchReqBundle(): PrefetchReqBundle = { 220 val res = Wire(new PrefetchReqBundle) 221 res.vaddr := this.vaddr 222 res.paddr := this.paddr 223 res.pc := this.uop.pc 224 res.miss := this.miss 225 res.pfHitStream := isFromStream(this.meta_prefetch) 226 227 res 228 } 229} 230 231class StPrefetchTrainBundle(implicit p: Parameters) extends LdPrefetchTrainBundle {} 232 233class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 234 // load inst replay informations 235 val rep_info = new LoadToLsqReplayIO 236 // queue entry data, except flag bits, will be updated if writeQueue is true, 237 // valid bit in LqWriteBundle will be ignored 238 val data_wen_dup = Vec(6, Bool()) // dirty reg dup 239 240 241 def fromLsPipelineBundle(input: LsPipelineBundle, latch: Boolean = false, enable: Bool = true.B) = { 242 if(latch) vaddr := RegEnable(input.vaddr, enable) else vaddr := input.vaddr 243 if(latch) fullva := RegEnable(input.fullva, enable) else fullva := input.fullva 244 if(latch) paddr := RegEnable(input.paddr, enable) else paddr := input.paddr 245 if(latch) gpaddr := RegEnable(input.gpaddr, enable) else gpaddr := input.gpaddr 246 if(latch) mask := RegEnable(input.mask, enable) else mask := input.mask 247 if(latch) data := RegEnable(input.data, enable) else data := input.data 248 if(latch) uop := RegEnable(input.uop, enable) else uop := input.uop 249 if(latch) wlineflag := RegEnable(input.wlineflag, enable) else wlineflag := input.wlineflag 250 if(latch) miss := RegEnable(input.miss, enable) else miss := input.miss 251 if(latch) tlbMiss := RegEnable(input.tlbMiss, enable) else tlbMiss := input.tlbMiss 252 if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack 253 if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio 254 if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic 255 if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask 256 if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData 257 if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch 258 if(latch) isHWPrefetch := RegEnable(input.isHWPrefetch, enable) else isHWPrefetch := input.isHWPrefetch 259 if(latch) isFrmMisAlignBuf := RegEnable(input.isFrmMisAlignBuf, enable) else isFrmMisAlignBuf := input.isFrmMisAlignBuf 260 if(latch) isFirstIssue := RegEnable(input.isFirstIssue, enable) else isFirstIssue := input.isFirstIssue 261 if(latch) hasROBEntry := RegEnable(input.hasROBEntry, enable) else hasROBEntry := input.hasROBEntry 262 if(latch) isLoadReplay := RegEnable(input.isLoadReplay, enable) else isLoadReplay := input.isLoadReplay 263 if(latch) isFastPath := RegEnable(input.isFastPath, enable) else isFastPath := input.isFastPath 264 if(latch) isFastReplay := RegEnable(input.isFastReplay, enable) else isFastReplay := input.isFastReplay 265 if(latch) mshrid := RegEnable(input.mshrid, enable) else mshrid := input.mshrid 266 if(latch) forward_tlDchannel := RegEnable(input.forward_tlDchannel, enable) else forward_tlDchannel := input.forward_tlDchannel 267 if(latch) replayCarry := RegEnable(input.replayCarry, enable) else replayCarry := input.replayCarry 268 if(latch) dcacheRequireReplay := RegEnable(input.dcacheRequireReplay, enable) else dcacheRequireReplay := input.dcacheRequireReplay 269 if(latch) schedIndex := RegEnable(input.schedIndex, enable) else schedIndex := input.schedIndex 270 if(latch) handledByMSHR := RegEnable(input.handledByMSHR, enable) else handledByMSHR := input.handledByMSHR 271 if(latch) replacementUpdated := RegEnable(input.replacementUpdated, enable) else replacementUpdated := input.replacementUpdated 272 if(latch) missDbUpdated := RegEnable(input.missDbUpdated, enable) else missDbUpdated := input.missDbUpdated 273 if(latch) delayedLoadError := RegEnable(input.delayedLoadError, enable) else delayedLoadError := input.delayedLoadError 274 if(latch) lateKill := RegEnable(input.lateKill, enable) else lateKill := input.lateKill 275 if(latch) feedbacked := RegEnable(input.feedbacked, enable) else feedbacked := input.feedbacked 276 if(latch) isvec := RegEnable(input.isvec, enable) else isvec := input.isvec 277 if(latch) is128bit := RegEnable(input.is128bit, enable) else is128bit := input.is128bit 278 if(latch) vecActive := RegEnable(input.vecActive, enable) else vecActive := input.vecActive 279 if(latch) uop_unit_stride_fof := RegEnable(input.uop_unit_stride_fof, enable) else uop_unit_stride_fof := input.uop_unit_stride_fof 280 if(latch) reg_offset := RegEnable(input.reg_offset, enable) else reg_offset := input.reg_offset 281 if(latch) mbIndex := RegEnable(input.mbIndex, enable) else mbIndex := input.mbIndex 282 if(latch) elemIdxInsideVd := RegEnable(input.elemIdxInsideVd, enable) else elemIdxInsideVd := input.elemIdxInsideVd 283 284 rep_info := DontCare 285 data_wen_dup := DontCare 286 } 287} 288 289class SqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { 290 val need_rep = Bool() 291} 292 293class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle { 294 val vaddr = Output(UInt(VAddrBits.W)) 295 val paddr = Output(UInt(PAddrBits.W)) 296 val mask = Output(UInt((VLEN/8).W)) 297 val uop = Output(new DynInst) // for replay 298 val pc = Output(UInt(VAddrBits.W)) //for debug 299 val valid = Output(Bool()) 300 301 val forwardMaskFast = Input(Vec((VLEN/8), Bool())) // resp to load_s1 302 val forwardMask = Input(Vec((VLEN/8), Bool())) // resp to load_s2 303 val forwardData = Input(Vec((VLEN/8), UInt(8.W))) // resp to load_s2 304 305 // val lqIdx = Output(UInt(LoadQueueIdxWidth.W)) 306 val sqIdx = Output(new SqPtr) 307 308 // dataInvalid suggests store to load forward found forward should happen, 309 // but data is not available for now. If dataInvalid, load inst should 310 // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid 311 val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now 312 313 // matchInvalid suggests in store to load forward logic, paddr cam result does 314 // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception 315 // should be raised to flush SQ and committed sbuffer. 316 val matchInvalid = Input(Bool()) // resp to load_s2 317 318 // addrInvalid suggests store to load forward found forward should happen, 319 // but address (SSID) is not available for now. If addrInvalid, load inst should 320 // be replayed from RS. Feedback type should be RSFeedbackType.addrInvalid 321 val addrInvalid = Input(Bool()) 322} 323 324// LoadForwardQueryIO used in load pipeline 325// 326// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO: 327// PipeIO use predecoded sqIdxMask for better forward timing 328class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO { 329 // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons 330 // sqIdxMask is calcuated in earlier stage for better timing 331 val sqIdxMask = Output(UInt(StoreQueueSize.W)) 332 333 // dataInvalid: addr match, but data is not valid for now 334 val dataInvalidFast = Input(Bool()) // resp to load_s1 335 // val dataInvalid = Input(Bool()) // resp to load_s2 336 val dataInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 337 val addrInvalidSqIdx = Input(new SqPtr) // resp to load_s2, sqIdx 338} 339 340// Query load queue for ld-ld violation 341// 342// Req should be send in load_s1 343// Resp will be generated 1 cycle later 344// 345// Note that query req may be !ready, as dcache is releasing a block 346// If it happens, a replay from rs is needed. 347class LoadNukeQueryReq(implicit p: Parameters) extends XSBundle { // provide lqIdx 348 val uop = new DynInst 349 // mask: load's data mask. 350 val mask = UInt((VLEN/8).W) 351 352 // paddr: load's paddr. 353 val paddr = UInt(PAddrBits.W) 354 // dataInvalid: load data is invalid. 355 val data_valid = Bool() 356} 357 358class LoadNukeQueryResp(implicit p: Parameters) extends XSBundle { 359 // rep_frm_fetch: ld-ld violation check success, replay from fetch. 360 val rep_frm_fetch = Bool() 361} 362 363class LoadNukeQueryIO(implicit p: Parameters) extends XSBundle { 364 val req = Decoupled(new LoadNukeQueryReq) 365 val resp = Flipped(Valid(new LoadNukeQueryResp)) 366 val revoke = Output(Bool()) 367} 368 369class StoreNukeQueryIO(implicit p: Parameters) extends XSBundle { 370 // robIdx: Requestor's (a store instruction) rob index for match logic. 371 val robIdx = new RobPtr 372 373 // paddr: requestor's (a store instruction) physical address for match logic. 374 val paddr = UInt(PAddrBits.W) 375 376 // mask: requestor's (a store instruction) data width mask for match logic. 377 val mask = UInt((VLEN/8).W) 378 379 // matchLine: if store is vector 128-bits, load unit need to compare 128-bits vaddr. 380 val matchLine = Bool() 381} 382 383class StoreMaBufToSqControlIO(implicit p: Parameters) extends XSBundle { 384 // from storeMisalignBuffer to storeQueue, control it's sbuffer write 385 val control = Output(new XSBundle { 386 // control sq to write-into sb 387 val writeSb = Bool() 388 val wdata = UInt(VLEN.W) 389 val wmask = UInt((VLEN / 8).W) 390 val paddr = UInt(PAddrBits.W) 391 val vaddr = UInt(VAddrBits.W) 392 val last = Bool() 393 val hasException = Bool() 394 // remove this entry in sq 395 val removeSq = Bool() 396 }) 397 // from storeQueue to storeMisalignBuffer, provide detail info of this store 398 val storeInfo = Input(new XSBundle { 399 val data = UInt(VLEN.W) 400 // is the data of the unaligned store ready at sq? 401 val dataReady = Bool() 402 // complete a data transfer from sq to sb 403 val completeSbTrans = Bool() 404 }) 405} 406 407// Store byte valid mask write bundle 408// 409// Store byte valid mask write to SQ takes 2 cycles 410class StoreMaskBundle(implicit p: Parameters) extends XSBundle { 411 val sqIdx = new SqPtr 412 val mask = UInt((VLEN/8).W) 413} 414 415class LoadDataFromDcacheBundle(implicit p: Parameters) extends DCacheBundle { 416 // old dcache: optimize data sram read fanout 417 // val bankedDcacheData = Vec(DCacheBanks, UInt(64.W)) 418 // val bank_oh = UInt(DCacheBanks.W) 419 420 // new dcache 421 val respDcacheData = UInt(VLEN.W) 422 val forwardMask = Vec(VLEN/8, Bool()) 423 val forwardData = Vec(VLEN/8, UInt(8.W)) 424 val uop = new DynInst // for data selection, only fwen and fuOpType are used 425 val addrOffset = UInt(4.W) // for data selection 426 427 // forward tilelink D channel 428 val forward_D = Bool() 429 val forwardData_D = Vec(VLEN/8, UInt(8.W)) 430 431 // forward mshr data 432 val forward_mshr = Bool() 433 val forwardData_mshr = Vec(VLEN/8, UInt(8.W)) 434 435 val forward_result_valid = Bool() 436 437 def mergeTLData(): UInt = { 438 // merge TL D or MSHR data at load s2 439 val dcache_data = respDcacheData 440 val use_D = forward_D && forward_result_valid 441 val use_mshr = forward_mshr && forward_result_valid 442 Mux( 443 use_D || use_mshr, 444 Mux( 445 use_D, 446 forwardData_D.asUInt, 447 forwardData_mshr.asUInt 448 ), 449 dcache_data 450 ) 451 } 452 453 def mergeLsqFwdData(dcacheData: UInt): UInt = { 454 // merge dcache and lsq forward data at load s3 455 val rdataVec = VecInit((0 until VLEN / 8).map(j => 456 Mux(forwardMask(j), forwardData(j), dcacheData(8*(j+1)-1, 8*j)) 457 )) 458 rdataVec.asUInt 459 } 460} 461 462// Load writeback data from load queue (refill) 463class LoadDataFromLQBundle(implicit p: Parameters) extends XSBundle { 464 val lqData = UInt(64.W) // load queue has merged data 465 val uop = new DynInst // for data selection, only fwen and fuOpType are used 466 val addrOffset = UInt(3.W) // for data selection 467 468 def mergedData(): UInt = { 469 lqData 470 } 471} 472 473// Bundle for load / store wait waking up 474class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle { 475 val robIdx = Vec(backendParams.StaExuCnt, ValidIO(new RobPtr)) 476 val sqIdx = Vec(backendParams.StdCnt, ValidIO(new SqPtr)) 477} 478 479object AddPipelineReg { 480 class PipelineRegModule[T <: Data](gen: T) extends Module { 481 val io = IO(new Bundle() { 482 val in = Flipped(DecoupledIO(gen.cloneType)) 483 val out = DecoupledIO(gen.cloneType) 484 val isFlush = Input(Bool()) 485 }) 486 487 val valid = RegInit(false.B) 488 valid.suggestName("pipeline_reg_valid") 489 when (io.out.fire) { valid := false.B } 490 when (io.in.fire) { valid := true.B } 491 when (io.isFlush) { valid := false.B } 492 493 io.in.ready := !valid || io.out.ready 494 io.out.bits := RegEnable(io.in.bits, io.in.fire) 495 io.out.valid := valid //&& !isFlush 496 } 497 498 def apply[T <: Data] 499 (left: DecoupledIO[T], right: DecoupledIO[T], isFlush: Bool, 500 moduleName: Option[String] = None 501 ): Unit = { 502 val pipelineReg = Module(new PipelineRegModule[T](left.bits.cloneType)) 503 if(moduleName.nonEmpty) pipelineReg.suggestName(moduleName.get) 504 pipelineReg.io.in <> left 505 right <> pipelineReg.io.out 506 pipelineReg.io.isFlush := isFlush 507 } 508}