History log of /XiangShan/src/main/scala/xiangshan/mem/prefetch/ (Results 1 – 25 of 79)
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30f3571714-Apr-2025 cz4e <[email protected]>

refactor(DFT): refactor `DFT` IO (#4530)


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/.gitmodules
/XiangShan/ChiselAIA
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scalastyle-config.xml
/XiangShan/scalastyle-test-config.xml
/XiangShan/scripts/constantHelper.py
/XiangShan/scripts/perfcct.py
/XiangShan/scripts/requirements.txt
/XiangShan/scripts/rolling/.gitignore
/XiangShan/scripts/rolling/rollingplot.py
/XiangShan/scripts/top-down/configs.py
/XiangShan/scripts/top-down/draw.py
/XiangShan/scripts/top-down/top_down.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/MemEncrypt.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
/XiangShan/src/main/scala/utils/LowPowerState.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSROoORead.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PFEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/Bundles.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/xiangshan/frontend/FrontTrigger.scala
/XiangShan/utility
4b2c87ba27-Feb-2025 梁森 Liang Sen <[email protected]>

feat(dfx): integerate dfx components (#4312)


/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/ready-to-run
/XiangShan/scripts/top-down/configs.py
/XiangShan/src/main/scala/device/MemEncrypt.scala
/XiangShan/src/main/scala/device/MemEncryptUtil.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/BitmapCheck.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
99ce557620-Feb-2025 cz4e <[email protected]>

style(Bundles): rewrite bundles with new style (#4274)


/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSROoORead.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/mem/Bundles.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
BasePrefecher.scala
L1PrefetchComponent.scala
L1StreamPrefetcher.scala
L1StridePrefetcher.scala
PrefetcherMonitor.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
9e12e8ed08-Feb-2025 cz4e <[email protected]>

style(Bundles): move bundles to Bundles.scala (#4247)


/XiangShan/.github/workflows/artifacts.yml
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/Bundles.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
BasePrefecher.scala
L1PrefetchComponent.scala
L1StreamPrefetcher.scala
L1StridePrefetcher.scala
PrefetcherMonitor.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
881e32f522-Jan-2025 Zifei Zhang <[email protected]>

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement fo

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement for CHI port width check
- add prefetch control by custom csr
- optimize timing in CoupledL2, mainly paths from SRAM to ICG
- add clock gate to each of the splitted SRAMs in CoupledL2
- fix several bugs concerning WriteEvictOrEvict, SnpQuery,
SnpCleanShared, SnpStash*, etc

---------

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Yanqin Li <[email protected]>

show more ...


/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/openLLC
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/yunsuan
25a80bce16-Jan-2025 Yanqin Li <[email protected]>

fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to

fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to process the response of TLB (got in s2) and
PMP(got in s3)

show more ...

5bd65c5614-Jan-2025 Tang Haojin <[email protected]>

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

show more ...


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/device/AXI4SlaveModule.scala
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/device/TLTimer.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
/XiangShan/src/main/scala/utils/DebugIdentityNode.scala
/XiangShan/src/main/scala/utils/TLDump.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheCtrlUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
L1PrefetchComponent.scala
L1PrefetchInterface.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
452b584319-Dec-2024 Huijin Li <[email protected]>

power(MemBlock): power optimization in MemBlock (#4059)

power optimization:
(1) use “withClockGate” instead of ClockGate in DCache
(2) reduce LSQ entries


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/format.yml
/XiangShan/.gitignore
/XiangShan/.mill-version
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/images/xs-arch-kunminghu.svg
/XiangShan/openLLC
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4IntrGenerator.scala
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/XiangShanStage.scala
/XiangShan/src/main/scala/utils/SeqUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/README.md
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala
/XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/CtrlUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AMOALU.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/README.md
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
/XiangShan/yunsuan
c49ebec818-Nov-2024 Haoyuan Feng <[email protected]>

docs: add acknowledgements (#3861)


/XiangShan/.github/workflows/emu.yml
/XiangShan/README.md
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
FDP.scala
L1StridePrefetcher.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/yunsuan
b32e951808-Nov-2024 Huijin Li <[email protected]>

power(MemBlock): add ClockGate for DCache SRAM (#3824)

By using ClockGate for DCache SRAM, memory Power has 64% reduction,
MemBlock total power has 23.38% reduction.

a982a3c907-Nov-2024 happy-lx <[email protected]>

sms: update pht when act update (#3821)

when the bits update in act,it will be update in pht at the same time.

---------

Co-authored-by: jueshiwenli <[email protected]>


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/format.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/.scalafmt.conf
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/utils/AXI4Lite.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/VecExcpDataMergeModule.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CommitIDModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Bim.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/RAS.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimMMIO.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
8a4dab4d04-Oct-2024 Haoyuan Feng <[email protected]>

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condi

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condition is
not satisfied for prefetch and redirected requests, resulting in stuck.
This commit fixes this bug.

show more ...


/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/VecExcpDataMergeModule.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
L1PrefetchComponent.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VfofBuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
4a2e3bec26-Sep-2024 Tang Haojin <[email protected]>

fix(Pmem): memory range should be 'or'ed rather than 'and'ed (#3651)


/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
L1PrefetchComponent.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/utility
45def85621-Sep-2024 Tang Haojin <[email protected]>

refactor(Pmem): use `Seq` for physical memory ranges (#3622)


/XiangShan/coupledL2
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
L1PrefetchComponent.scala
L1PrefetchInterface.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/test/scala/xiangshan/backend/dispatch/Dispatch2IqMain.scala
af95bc3220-Sep-2024 Haoyuan Feng <[email protected]>

fix(prefetch): MMIO address should not send prefetch requests (#3615)

TODO: Prefetcher should check pmp & pma in order to decide whether to
send requests

db6cfb5a19-Sep-2024 Haoyuan Feng <[email protected]>

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

show more ...


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/parser.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/DbEntry.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapTvalMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/MEFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
L1PrefetchComponent.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimMMIO.scala
f422188306-Sep-2024 happy-lx <[email protected]>

perf(L1PF): Stream only pf at miss/pfHit (#3508)

Perf Bug Description:
<img
src="https://github.com/user-attachments/assets/3d1a7105-088b-467a-9c93-833f534bb4e6"
width="300"/>
Stream Prefetcher

perf(L1PF): Stream only pf at miss/pfHit (#3508)

Perf Bug Description:
<img
src="https://github.com/user-attachments/assets/3d1a7105-088b-467a-9c93-833f534bb4e6"
width="300"/>
Stream Prefetcher is **trained and triggered in all memory access
traces**. If the program(As shown above) repeatedly accesses an 8K space
in a loop, the first loop can be prefetched normally, but in the
subsequent loop the data has been fetched back to Dcache already. In
theory, there is no need to prefetch again, since the Stream Prefetcher
is triggered in all memory access traces, which will cause subsequent
prefetching requests to be triggered and preempt the pipeline which may
cause performance loss.

FIX:
Let the Stream prefetcher only trigger prefetching when **miss and
Prefetch hit** (training still uses all memory access traces).

show more ...


/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/scripts/generate_all.sh
/XiangShan/scripts/parser.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/AsynchronousMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
BasePrefecher.scala
L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/utility
/XiangShan/yunsuan
6070f1e903-Sep-2024 happy-lx <[email protected]>

fix(L1PF): fix good_prefetch Counting logic (#3474)

Previous design:
When a demand load hits a Cache block fetched by the prefetcher, the
`PrefetchSource` of this block will be cleared,
causing i

fix(L1PF): fix good_prefetch Counting logic (#3474)

Previous design:
When a demand load hits a Cache block fetched by the prefetcher, the
`PrefetchSource` of this block will be cleared,
causing it to be mistakenly believed that it was not fetched by the
prefetcher initially when it is subsequently replaced from the cache,
resulting in not increasing the `good_prefetch` counter

Fix:
Now add a new cache block status(L1_HW_PREFETCH_CLEAR): indicating that
this block was originally fetched by the prefetcher

show more ...


/XiangShan/.github/workflows/check_verilog.py
/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/AXI4Flash.scala
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/device/IMSICAsync.scala
/XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/device/standalone/StandAlonePLIC.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/utils/NamedUInt.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/Instructions.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FliTable.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
L1PrefetchInterface.scala
PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
/XiangShan/yunsuan
149a232618-Jul-2024 weiding liu <[email protected]>

LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need t

LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need to do pmp check, so we also need to send signal of `no_translate`.

show more ...


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala
/XiangShan/src/main/scala/device/standalone/standalone_device.mk
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Generator.scala
/XiangShan/src/main/scala/top/XiangShanStage.scala
/XiangShan/src/main/scala/utils/DebugMem.scala
/XiangShan/src/main/scala/utils/MapUtils.scala
/XiangShan/src/main/scala/utils/SeqUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/implicitCast.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/AgeDetector.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCache.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheAgeTimer.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheDataModule.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagModule.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/VictimList.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/FreeList.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
L1PrefetchComponent.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/main/scala/xiangshan/transforms/Helpers.scala
/XiangShan/src/main/scala/xiangshan/transforms/NestedPrefixModulesAnnotation.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintControl.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/test/scala/fu/IntDiv.scala
/XiangShan/src/test/scala/xiangshan/DecodeTest.scala
/XiangShan/src/test/scala/xiangshan/XSTester.scala
/XiangShan/yunsuan
70eea12320-Jul-2024 Yanqin Li <[email protected]>

fanout: change entry reset into async-reset (#3229)


/XiangShan/.github/workflows/check_verilog.py
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.gitmodules
/XiangShan/.mill-version
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/macros/src/main/scala/CSRMacros.scala
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/chisel/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/chisel3/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/AXI4Plic.scala
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/device/TLTimer.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneCLINT.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/device/standalone/StandAlonePLIC.scala
/XiangShan/src/main/scala/device/standalone/standalone_device.mk
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/BusPerfMonitor.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/utils/AXI4Lite.scala
/XiangShan/src/main/scala/utils/DebugIdentityNode.scala
/XiangShan/src/main/scala/utils/PerfCounterUtils.scala
/XiangShan/src/main/scala/utils/TLDump.scala
/XiangShan/src/main/scala/utils/Trigger.scala
/XiangShan/src/main/scala/utils/VerilogAXI4LiteRecord.scala
/XiangShan/src/main/scala/utils/VerilogAXI4Record.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/Og2ForVector.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/PseudoInstruction.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Bku.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FunctionUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAnnotation.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRNamedConstant.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/StateEnBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/ByteMaskTailGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Snapshot.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/WPU.scala
/XiangShan/src/main/scala/xiangshan/cache/wpu/WPUWrapper.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
L1PrefetchComponent.scala
L1StreamPrefetcher.scala
L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/src/test/scala/xiangshan/XSTester.scala
/XiangShan/src/test/scala/xiangshan/backend/BackendMain.scala
/XiangShan/utility
/XiangShan/yunsuan
255bd5b106-Dec-2023 lixin <[email protected]>

Prefetcher: use reg instead of wire when reordering for 3ld

5adc482916-Jun-2024 Yanqin Li <[email protected]>

memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <

memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: CharlieLiu <[email protected]>

show more ...


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.yml
/XiangShan/.github/ISSUE_TEMPLATE/2-feature_request.yaml
/XiangShan/.github/ISSUE_TEMPLATE/3-problem.yaml
/XiangShan/.github/ISSUE_TEMPLATE/4-other_question.yml
/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.mill-version
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataSource.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/DispatchQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntFPToVec.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/VecPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/DivUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/MulUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIDiv.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIMacU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VPPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/MultiWakeupQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/BaseFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
/XiangShan/yunsuan
4ccb2e8b28-May-2024 Yanqin Li <[email protected]>

prefetch & utility: add clockgate control (#3005)


/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4UART.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/utils/LogUtils.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/PipeGroupConnect.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFReadArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RFWBConflictChecker.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/RdConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiterParams.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbFuBusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuType.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Vsetu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpNonPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Mgu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIPU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/PregParams.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rename/freelist/StdFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheInstruction.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/FakeDCache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
FDP.scala
L1PrefetchComponent.scala
L1StreamPrefetcher.scala
L1StridePrefetcher.scala
SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
/XiangShan/yunsuan
c686adcd10-May-2024 Yinan Xu <[email protected]>

Bump utility and disable ConstantIn by default (#2955)

* use BigInt for initValue of Constantin.createRecord
* use WITH_CONSTANTIN=1 to enable the ConstantIn plugin

20e09ab109-May-2024 happy-lx <[email protected]>

fix bug of stream (#2756)

Bug Description:
(1) Increase the way of Dcache to 8 to reduce the problem of running on the bwaves test caused by too many addresses mapped to the same set.
(2) Set ldu0

fix bug of stream (#2756)

Bug Description:
(1) Increase the way of Dcache to 8 to reduce the problem of running on the bwaves test caused by too many addresses mapped to the same set.
(2) Set ldu0 to a high-confidence prefetch request channel to increase the probability that the prefetch request will be accepted by Dcache's MSHR.
(3) Fix the issue that ldu sends an error ready back to the prefetcher to prevent the prefetch request from being dropped.
(4) Dont let the prefetch request access Dcache's DataArray.
(5) Add a extra port in Muti-level prefetch Queue to accept more pf req from stream&stride
(6) Larger Stream bit vector Array 16 -> 32 to cover muti Stream access pattern in Bwaves and GemsFDTD.

In addition, the decline in libquantum is a bit strange.

show more ...


/XiangShan/.github/workflows/check_verilog.py
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.gitignore
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/DbEntry.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/FuBusyTableWrite.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/ImmExtractor.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
BasePrefecher.scala
L1PrefetchComponent.scala
L1StreamPrefetcher.scala
L1StridePrefetcher.scala
PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility

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