refactor(DFT): refactor `DFT` IO (#4530)

feat(dfx): integerate dfx components (#4312)

style(Bundles): rewrite bundles with new style (#4274)

style(Bundles): move bundles to Bundles.scala (#4247)

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement fo

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement for CHI port width check
- add prefetch control by custom csr
- optimize timing in CoupledL2, mainly paths from SRAM to ICG
- add clock gate to each of the splitted SRAMs in CoupledL2
- fix several bugs concerning WriteEvictOrEvict, SnpQuery,
SnpCleanShared, SnpStash*, etc

---------

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Yanqin Li <[email protected]>

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fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to

fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to process the response of TLB (got in s2) and
PMP(got in s3)

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feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

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power(MemBlock): power optimization in MemBlock (#4059)

power optimization：
(1) use “withClockGate” instead of ClockGate in DCache
(2) reduce LSQ entries

docs: add acknowledgements (#3861)

power(MemBlock): add ClockGate for DCache SRAM (#3824)

By using ClockGate for DCache SRAM, memory Power has 64% reduction,
MemBlock total power has 23.38% reduction.

sms: update pht when act update (#3821)

when the bits update in act,it will be update in pht at the same time.

---------

Co-authored-by: jueshiwenli <[email protected]>

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condi

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condition is
not satisfied for prefetch and redirected requests, resulting in stuck.
This commit fixes this bug.

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fix(Pmem): memory range should be 'or'ed rather than 'and'ed (#3651)

refactor(Pmem): use `Seq` for physical memory ranges (#3622)

fix(prefetch): MMIO address should not send prefetch requests (#3615)

TODO: Prefetcher should check pmp & pma in order to decide whether to
send requests

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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perf(L1PF): Stream only pf at miss/pfHit (#3508)

Perf Bug Description:
<img
src="https://github.com/user-attachments/assets/3d1a7105-088b-467a-9c93-833f534bb4e6"
width="300"/>
Stream Prefetcher

perf(L1PF): Stream only pf at miss/pfHit (#3508)

Perf Bug Description:
<img
src="https://github.com/user-attachments/assets/3d1a7105-088b-467a-9c93-833f534bb4e6"
width="300"/>
Stream Prefetcher is **trained and triggered in all memory access
traces**. If the program(As shown above) repeatedly accesses an 8K space
in a loop, the first loop can be prefetched normally, but in the
subsequent loop the data has been fetched back to Dcache already. In
theory, there is no need to prefetch again, since the Stream Prefetcher
is triggered in all memory access traces, which will cause subsequent
prefetching requests to be triggered and preempt the pipeline which may
cause performance loss.

FIX:
Let the Stream prefetcher only trigger prefetching when **miss and
Prefetch hit** (training still uses all memory access traces).

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fix(L1PF): fix good_prefetch Counting logic (#3474)

Previous design:
When a demand load hits a Cache block fetched by the prefetcher, the
`PrefetchSource` of this block will be cleared,
causing i

fix(L1PF): fix good_prefetch Counting logic (#3474)

Previous design:
When a demand load hits a Cache block fetched by the prefetcher, the
`PrefetchSource` of this block will be cleared,
causing it to be mistakenly believed that it was not fetched by the
prefetcher initially when it is subsequently replaced from the cache,
resulting in not increasing the `good_prefetch` counter

Fix:
Now add a new cache block status(L1_HW_PREFETCH_CLEAR): indicating that
this block was originally fetched by the prefetcher

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LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need t

LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need to do pmp check, so we also need to send signal of `no_translate`.

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fanout: change entry reset into async-reset (#3229)

Prefetcher: use reg instead of wire when reordering for 3ld

memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <

memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: CharlieLiu <[email protected]>

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prefetch & utility: add clockgate control (#3005)

Bump utility and disable ConstantIn by default (#2955)

* use BigInt for initValue of Constantin.createRecord
* use WITH_CONSTANTIN=1 to enable the ConstantIn plugin

fix bug of stream (#2756)

Bug Description：
(1) Increase the way of Dcache to 8 to reduce the problem of running on the bwaves test caused by too many addresses mapped to the same set.
(2) Set ldu0

fix bug of stream (#2756)

Bug Description：
(1) Increase the way of Dcache to 8 to reduce the problem of running on the bwaves test caused by too many addresses mapped to the same set.
(2) Set ldu0 to a high-confidence prefetch request channel to increase the probability that the prefetch request will be accepted by Dcache's MSHR.
(3) Fix the issue that ldu sends an error ready back to the prefetcher to prevent the prefetch request from being dropped.
(4) Dont let the prefetch request access Dcache's DataArray.
(5) Add a extra port in Muti-level prefetch Queue to accept more pf req from stream&stride
(6) Larger Stream bit vector Array 16 -> 32 to cover muti Stream access pattern in Bwaves and GemsFDTD.

In addition, the decline in libquantum is a bit strange.

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