xref: /XiangShan/src/main/scala/system/SoC.scala (revision af95bc32d01e4c3190244795837729cf6e205392) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package system
18
19import org.chipsalliance.cde.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import device.{DebugModule, TLPMA, TLPMAIO}
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.devices.tilelink._
25import freechips.rocketchip.diplomacy.{AddressSet, IdRange, InModuleBody, LazyModule, LazyModuleImp, MemoryDevice, RegionType, SimpleDevice, TransferSizes}
26import freechips.rocketchip.interrupts.{IntSourceNode, IntSourcePortSimple}
27import freechips.rocketchip.regmapper.{RegField, RegFieldDesc, RegFieldGroup}
28import freechips.rocketchip.tilelink._
29import freechips.rocketchip.util.AsyncQueueParams
30import huancun._
31import top.BusPerfMonitor
32import utility.{ReqSourceKey, TLClientsMerger, TLEdgeBuffer, TLLogger}
33import xiangshan.backend.fu.PMAConst
34import xiangshan.{DebugOptionsKey, XSTileKey}
35import coupledL2.EnableCHI
36import coupledL2.tl2chi.CHIIssue
37
38case object SoCParamsKey extends Field[SoCParameters]
39
40case class SoCParameters
41(
42  EnableILA: Boolean = false,
43  PAddrBits: Int = 48,
44  PmemLowBound: Long = 0x80000000L,
45  PmemHighBound: Long = 0x80000000000L,
46  extIntrs: Int = 64,
47  L3NBanks: Int = 4,
48  L3CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
49    name = "L3",
50    level = 3,
51    ways = 8,
52    sets = 2048 // 1MB per bank
53  )),
54  XSTopPrefix: Option[String] = None,
55  NodeIDWidthList: Map[String, Int] = Map(
56    "B" -> 7,
57    "E.b" -> 11
58  ),
59  NumHart: Int = 64,
60  NumIRFiles: Int = 7,
61  NumIRSrc: Int = 256,
62  UseXSNoCTop: Boolean = false,
63  IMSICUseTL: Boolean = false,
64  EnableCHIAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 4, sync = 3, safe = false)),
65  EnableClintAsyncBridge: Option[AsyncQueueParams] = Some(AsyncQueueParams(depth = 1, sync = 3, safe = false))
66){
67  // L3 configurations
68  val L3InnerBusWidth = 256
69  val L3BlockSize = 64
70  // on chip network configurations
71  val L3OuterBusWidth = 256
72}
73
74trait HasSoCParameter {
75  implicit val p: Parameters
76
77  val soc = p(SoCParamsKey)
78  val debugOpts = p(DebugOptionsKey)
79  val tiles = p(XSTileKey)
80  val enableCHI = p(EnableCHI)
81  val issue = p(CHIIssue)
82
83  val NumCores = tiles.size
84  val EnableILA = soc.EnableILA
85
86  // L3 configurations
87  val L3InnerBusWidth = soc.L3InnerBusWidth
88  val L3BlockSize = soc.L3BlockSize
89  val L3NBanks = soc.L3NBanks
90
91  // on chip network configurations
92  val L3OuterBusWidth = soc.L3OuterBusWidth
93
94  val NrExtIntr = soc.extIntrs
95
96  val SetIpNumValidSize = soc.NumHart * soc.NumIRFiles
97
98  val NumIRSrc = soc.NumIRSrc
99
100  val EnableCHIAsyncBridge = if (enableCHI && soc.EnableCHIAsyncBridge.isDefined)
101    soc.EnableCHIAsyncBridge else None
102  val EnableClintAsyncBridge = soc.EnableClintAsyncBridge
103}
104
105class ILABundle extends Bundle {}
106
107
108abstract class BaseSoC()(implicit p: Parameters) extends LazyModule with HasSoCParameter {
109  val bankedNode = Option.when(!enableCHI)(BankBinder(L3NBanks, L3BlockSize))
110  val peripheralXbar = Option.when(!enableCHI)(TLXbar())
111  val l3_xbar = Option.when(!enableCHI)(TLXbar())
112  val l3_banked_xbar = Option.when(!enableCHI)(TLXbar())
113
114  val soc_xbar = Option.when(enableCHI)(AXI4Xbar())
115}
116
117// We adapt the following three traits from rocket-chip.
118// Source: rocket-chip/src/main/scala/subsystem/Ports.scala
119trait HaveSlaveAXI4Port {
120  this: BaseSoC =>
121
122  val idBits = 14
123
124  val l3FrontendAXI4Node = AXI4MasterNode(Seq(AXI4MasterPortParameters(
125    Seq(AXI4MasterParameters(
126      name = "dma",
127      id = IdRange(0, 1 << idBits)
128    ))
129  )))
130
131  if (l3_xbar.isDefined) {
132    val errorDevice = LazyModule(new TLError(
133      params = DevNullParams(
134        address = Seq(AddressSet(0x0, 0x7fffffffL)),
135        maxAtomic = 8,
136        maxTransfer = 64),
137      beatBytes = L3InnerBusWidth / 8
138    ))
139    errorDevice.node :=
140      l3_xbar.get :=
141      TLFIFOFixer() :=
142      TLWidthWidget(32) :=
143      AXI4ToTL() :=
144      AXI4UserYanker(Some(1)) :=
145      AXI4Fragmenter() :=
146      AXI4Buffer() :=
147      AXI4Buffer() :=
148      AXI4IdIndexer(1) :=
149      l3FrontendAXI4Node
150  }
151
152  val dma = InModuleBody {
153    l3FrontendAXI4Node.makeIOs()
154  }
155}
156
157trait HaveAXI4MemPort {
158  this: BaseSoC =>
159  val device = new MemoryDevice
160  // 48-bit physical address
161  val memRange = AddressSet(0x00000000L, 0xffffffffffffL).subtract(AddressSet(0x0L, 0x7fffffffL))
162  val memAXI4SlaveNode = AXI4SlaveNode(Seq(
163    AXI4SlavePortParameters(
164      slaves = Seq(
165        AXI4SlaveParameters(
166          address = memRange,
167          regionType = RegionType.UNCACHED,
168          executable = true,
169          supportsRead = TransferSizes(1, L3BlockSize),
170          supportsWrite = TransferSizes(1, L3BlockSize),
171          interleavedId = Some(0),
172          resources = device.reg("mem")
173        )
174      ),
175      beatBytes = L3OuterBusWidth / 8,
176      requestKeys = if (debugOpts.FPGAPlatform) Seq() else Seq(ReqSourceKey),
177    )
178  ))
179
180  val mem_xbar = TLXbar()
181  val l3_mem_pmu = BusPerfMonitor(name = "L3_Mem", enable = !debugOpts.FPGAPlatform && !enableCHI, stat_latency = true)
182  val axi4mem_node = AXI4IdentityNode()
183
184  if (enableCHI) {
185    axi4mem_node :=
186      soc_xbar.get
187  } else {
188    mem_xbar :=*
189      TLBuffer.chainNode(2) :=
190      TLCacheCork() :=
191      l3_mem_pmu :=
192      TLClientsMerger() :=
193      TLXbar() :=*
194      bankedNode.get
195
196    mem_xbar :=
197      TLWidthWidget(8) :=
198      TLBuffer.chainNode(3, name = Some("PeripheralXbar_to_MemXbar_buffer")) :=
199      peripheralXbar.get
200
201    axi4mem_node :=
202      TLToAXI4() :=
203      TLSourceShrinker(64) :=
204      TLWidthWidget(L3OuterBusWidth / 8) :=
205      TLBuffer.chainNode(2) :=
206      mem_xbar
207  }
208
209  memAXI4SlaveNode :=
210    AXI4Buffer() :=
211    AXI4Buffer() :=
212    AXI4Buffer() :=
213    AXI4IdIndexer(idBits = 14) :=
214    AXI4UserYanker() :=
215    AXI4Deinterleaver(L3BlockSize) :=
216    axi4mem_node
217
218  val memory = InModuleBody {
219    memAXI4SlaveNode.makeIOs()
220  }
221}
222
223trait HaveAXI4PeripheralPort { this: BaseSoC =>
224  // on-chip devices: 0x3800_0000 - 0x3fff_ffff 0x0000_0000 - 0x0000_0fff
225  val onChipPeripheralRange = AddressSet(0x38000000L, 0x07ffffffL)
226  val uartRange = AddressSet(0x40600000, 0x3f)
227  val uartDevice = new SimpleDevice("serial", Seq("xilinx,uartlite"))
228  val uartParams = AXI4SlaveParameters(
229    address = Seq(uartRange),
230    regionType = RegionType.UNCACHED,
231    supportsRead = TransferSizes(1, 32),
232    supportsWrite = TransferSizes(1, 32),
233    resources = uartDevice.reg
234  )
235  val peripheralRange = AddressSet(
236    0x0, 0x7fffffff
237  ).subtract(onChipPeripheralRange).flatMap(x => x.subtract(uartRange))
238  val peripheralNode = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
239    Seq(AXI4SlaveParameters(
240      address = peripheralRange,
241      regionType = RegionType.UNCACHED,
242      supportsRead = TransferSizes(1, 32),
243      supportsWrite = TransferSizes(1, 32),
244      interleavedId = Some(0)
245    ), uartParams),
246    beatBytes = 8
247  )))
248
249  val axi4peripheral_node = AXI4IdentityNode()
250  val error_xbar = Option.when(enableCHI)(TLXbar())
251
252  peripheralNode :=
253    AXI4UserYanker() :=
254    AXI4IdIndexer(idBits = 2) :=
255    AXI4Buffer() :=
256    AXI4Buffer() :=
257    AXI4Buffer() :=
258    AXI4Buffer() :=
259    AXI4UserYanker() :=
260    // AXI4Deinterleaver(8) :=
261    axi4peripheral_node
262
263  if (enableCHI) {
264    val error = LazyModule(new TLError(
265      params = DevNullParams(
266        address = Seq(AddressSet(0x1000000000000L, 0xffffffffffffL)),
267        maxAtomic = 8,
268        maxTransfer = 64),
269      beatBytes = 8
270    ))
271    error.node := error_xbar.get
272    axi4peripheral_node :=
273      AXI4Deinterleaver(8) :=
274      TLToAXI4() :=
275      error_xbar.get :=
276      TLBuffer.chainNode(2, Some("llc_to_peripheral_buffer")) :=
277      TLFIFOFixer() :=
278      TLWidthWidget(L3OuterBusWidth / 8) :=
279      AXI4ToTL() :=
280      AXI4UserYanker() :=
281      soc_xbar.get
282  } else {
283    axi4peripheral_node :=
284      AXI4Deinterleaver(8) :=
285      TLToAXI4() :=
286      TLBuffer.chainNode(3) :=
287      peripheralXbar.get
288  }
289
290  val peripheral = InModuleBody {
291    peripheralNode.makeIOs()
292  }
293
294}
295
296class MemMisc()(implicit p: Parameters) extends BaseSoC
297  with HaveAXI4MemPort
298  with PMAConst
299  with HaveAXI4PeripheralPort
300{
301
302  val peripheral_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
303  val core_to_l3_ports = Option.when(!enableCHI)(Array.fill(NumCores) { TLTempNode() })
304
305  val l3_in = TLTempNode()
306  val l3_out = TLTempNode()
307
308  val device_xbar = Option.when(enableCHI)(TLXbar())
309  device_xbar.foreach(_ := error_xbar.get)
310
311  if (l3_banked_xbar.isDefined) {
312    l3_in :*= TLEdgeBuffer(_ => true, Some("L3_in_buffer")) :*= l3_banked_xbar.get
313    l3_banked_xbar.get := TLBuffer.chainNode(2) := l3_xbar.get
314  }
315  bankedNode match {
316    case Some(bankBinder) =>
317      bankBinder :*= TLLogger("MEM_L3", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :*= l3_out
318    case None =>
319  }
320
321  if(soc.L3CacheParamsOpt.isEmpty){
322    l3_out :*= l3_in
323  }
324
325  if (!enableCHI) {
326    for (port <- peripheral_ports.get) {
327      peripheralXbar.get := TLBuffer.chainNode(2, Some("L2_to_L3_peripheral_buffer")) := port
328    }
329  }
330
331  core_to_l3_ports.foreach { case _ =>
332    for ((core_out, i) <- core_to_l3_ports.get.zipWithIndex){
333      l3_banked_xbar.get :=*
334        TLLogger(s"L3_L2_$i", !debugOpts.FPGAPlatform && debugOpts.AlwaysBasicDB) :=*
335        TLBuffer() :=
336        core_out
337    }
338  }
339
340  val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
341  if (enableCHI) { clint.node := device_xbar.get }
342  else { clint.node := peripheralXbar.get }
343
344  class IntSourceNodeToModule(val num: Int)(implicit p: Parameters) extends LazyModule {
345    val sourceNode = IntSourceNode(IntSourcePortSimple(num, ports = 1, sources = 1))
346    class IntSourceNodeToModuleImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
347      val in = IO(Input(Vec(num, Bool())))
348      in.zip(sourceNode.out.head._1).foreach{ case (i, s) => s := i }
349    }
350    lazy val module = new IntSourceNodeToModuleImp(this)
351  }
352
353  val plic = LazyModule(new TLPLIC(PLICParams(0x3c000000L), 8))
354  val plicSource = LazyModule(new IntSourceNodeToModule(NrExtIntr))
355
356  plic.intnode := plicSource.sourceNode
357  if (enableCHI) { plic.node := device_xbar.get }
358  else { plic.node := peripheralXbar.get }
359
360  val pll_node = TLRegisterNode(
361    address = Seq(AddressSet(0x3a000000L, 0xfff)),
362    device = new SimpleDevice("pll_ctrl", Seq()),
363    beatBytes = 8,
364    concurrency = 1
365  )
366  if (enableCHI) { pll_node := device_xbar.get }
367  else { pll_node := peripheralXbar.get }
368
369  val debugModule = LazyModule(new DebugModule(NumCores)(p))
370  if (enableCHI) {
371    debugModule.debug.node := device_xbar.get
372    // TODO: l3_xbar
373    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl =>
374      error_xbar.get := sb2tl.node
375    }
376  } else {
377    debugModule.debug.node := peripheralXbar.get
378    debugModule.debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
379      l3_xbar.get := TLBuffer() := sb2tl.node
380    }
381  }
382
383  val pma = LazyModule(new TLPMA)
384  if (enableCHI) {
385    pma.node := TLBuffer.chainNode(4) := device_xbar.get
386  } else {
387    pma.node := TLBuffer.chainNode(4) := peripheralXbar.get
388  }
389
390  class SoCMiscImp(wrapper: LazyModule) extends LazyModuleImp(wrapper) {
391
392    val debug_module_io = IO(new debugModule.DebugModuleIO)
393    val ext_intrs = IO(Input(UInt(NrExtIntr.W)))
394    val rtc_clock = IO(Input(Bool()))
395    val pll0_lock = IO(Input(Bool()))
396    val pll0_ctrl = IO(Output(Vec(6, UInt(32.W))))
397    val cacheable_check = IO(new TLPMAIO)
398    val clintTime = IO(Output(ValidIO(UInt(64.W))))
399
400    debugModule.module.io <> debug_module_io
401
402    // sync external interrupts
403    require(plicSource.module.in.length == ext_intrs.getWidth)
404    for ((plic_in, interrupt) <- plicSource.module.in.zip(ext_intrs.asBools)) {
405      val ext_intr_sync = RegInit(0.U(3.W))
406      ext_intr_sync := Cat(ext_intr_sync(1, 0), interrupt)
407      plic_in := ext_intr_sync(2)
408    }
409
410    pma.module.io <> cacheable_check
411
412    // positive edge sampling of the lower-speed rtc_clock
413    val rtcTick = RegInit(0.U(3.W))
414    rtcTick := Cat(rtcTick(1, 0), rtc_clock)
415    clint.module.io.rtcTick := rtcTick(1) && !rtcTick(2)
416
417    val pll_ctrl_regs = Seq.fill(6){ RegInit(0.U(32.W)) }
418    val pll_lock = RegNext(next = pll0_lock, init = false.B)
419
420    clintTime := clint.module.io.time
421
422    pll0_ctrl <> VecInit(pll_ctrl_regs)
423
424    pll_node.regmap(
425      0x000 -> RegFieldGroup(
426        "Pll", Some("PLL ctrl regs"),
427        pll_ctrl_regs.zipWithIndex.map{
428          case (r, i) => RegField(32, r, RegFieldDesc(
429            s"PLL_ctrl_$i",
430            desc = s"PLL ctrl register #$i"
431          ))
432        } :+ RegField.r(32, Cat(0.U(31.W), pll_lock), RegFieldDesc(
433          "PLL_lock",
434          "PLL lock register"
435        ))
436      )
437    )
438  }
439
440  lazy val module = new SoCMiscImp(this)
441}
442
443class SoCMisc()(implicit p: Parameters) extends MemMisc
444  with HaveSlaveAXI4Port
445
446