1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.frontend.FtqPtr 19 20class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 21 with HasCircularQueuePtrHelper 22{ 23 val csrIn = io.csrio.get 24 val csrOut = io.csrio.get 25 val csrToDecode = io.csrToDecode.get 26 27 val setFsDirty = csrIn.fpu.dirty_fs 28 val setFflags = csrIn.fpu.fflags 29 30 val setVsDirty = csrIn.vpu.dirty_vs 31 val setVstart = csrIn.vpu.set_vstart 32 val setVtype = csrIn.vpu.set_vtype 33 val setVxsat = csrIn.vpu.set_vxsat 34 val vlFromPreg = csrIn.vpu.vl 35 36 val flushPipe = Wire(Bool()) 37 val flush = io.flush.valid 38 39 /** Alias of input signals */ 40 val (valid, src1, imm, func) = ( 41 io.in.valid, 42 io.in.bits.data.src(0), 43 io.in.bits.data.imm(Imm_Z().len - 1, 0), 44 io.in.bits.ctrl.fuOpType 45 ) 46 47 // split imm/src1/rd from IMM_Z: src1/rd for tval 48 val addr = Imm_Z().getCSRAddr(imm) 49 val rd = Imm_Z().getRD(imm) 50 val rs1 = Imm_Z().getRS1(imm) 51 val imm5 = Imm_Z().getImm5(imm) 52 val csri = ZeroExt(imm5, XLEN) 53 54 import CSRConst._ 55 56 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 57 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 58 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 59 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 60 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 61 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 62 private val isWfi = CSROpType.isWfi(func) 63 private val isCSRAcc = CSROpType.isCsrAccess(func) 64 65 val csrMod = Module(new NewCSR) 66 val trapInstMod = Module(new TrapInstMod) 67 val trapTvalMod = Module(new TrapTvalMod) 68 69 private val privState = csrMod.io.status.privState 70 // The real reg value in CSR, with no read mask 71 private val regOut = csrMod.io.out.bits.regOut 72 private val src = Mux(CSROpType.needImm(func), csri, src1) 73 private val wdata = LookupTree(func, Seq( 74 CSROpType.wrt -> src1, 75 CSROpType.set -> (regOut | src1), 76 CSROpType.clr -> (regOut & (~src1).asUInt), 77 CSROpType.wrti -> csri, 78 CSROpType.seti -> (regOut | csri), 79 CSROpType.clri -> (regOut & (~csri).asUInt), 80 )) 81 82 private val csrAccess = valid && CSROpType.isCsrAccess(func) 83 private val csrWen = valid && ( 84 CSROpType.isCSRRW(func) || 85 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 86 ) 87 private val csrRen = valid && ( 88 CSROpType.isCSRRW(func) && rd =/= 0.U || 89 CSROpType.isCSRRSorRC(func) 90 ) 91 92 csrMod.io.in match { 93 case in => 94 in.valid := valid 95 in.bits.wen := csrWen 96 in.bits.ren := csrRen 97 in.bits.op := CSROpType.getCSROp(func) 98 in.bits.addr := addr 99 in.bits.src := src 100 in.bits.wdata := wdata 101 in.bits.mret := isMret 102 in.bits.mnret := isMNret 103 in.bits.sret := isSret 104 in.bits.dret := isDret 105 } 106 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 107 csrMod.io.fetchMalTval := trapTvalMod.io.tval 108 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 109 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 110 csrMod.io.fromMem.excpIsForVSnonLeafPTE := csrIn.memExceptionIsForVSnonLeafPTE 111 112 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 113 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 114 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 115 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 116 // Todo: shrink the width of trap vector. 117 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 118 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 119 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 120 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 121 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 122 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 123 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 124 csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr 125 csrMod.io.fromRob.trap.bits.isForVSnonLeafPTE := csrIn.exception.bits.isForVSnonLeafPTE 126 127 csrMod.io.fromRob.commit.fflags := setFflags 128 csrMod.io.fromRob.commit.fsDirty := setFsDirty 129 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 130 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 131 csrMod.io.fromRob.commit.vsDirty := setVsDirty 132 csrMod.io.fromRob.commit.vstart := setVstart 133 csrMod.io.fromRob.commit.vl := vlFromPreg 134 // Todo: correct vtype 135 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 136 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 137 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 138 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 139 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 140 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 141 142 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 143 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 144 145 csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr 146 147 csrMod.io.perf := csrIn.perf 148 149 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 150 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 151 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 152 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 153 csrMod.platformIRP.STIP := false.B 154 csrMod.platformIRP.VSEIP := false.B // Todo 155 csrMod.platformIRP.VSTIP := false.B // Todo 156 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 157 csrMod.nonMaskableIRP.NMI := csrIn.externalInterrupt.nmi.nmi 158 159 csrMod.io.fromTop.hartId := io.csrin.get.hartId 160 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 161 private val csrModOutValid = csrMod.io.out.valid 162 private val csrModOut = csrMod.io.out.bits 163 164 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 165 trapInstMod.io.fromRob.flush.valid := io.flush.valid 166 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 167 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 168 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 169 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 170 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 171 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 172 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 173 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 174 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 175 case t => 176 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 177 }) 178 179 trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate 180 trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc 181 trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr 182 trapTvalMod.io.fromCtrlBlock.flush := io.flush 183 trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr 184 185 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 186 imsic.i.hartId := io.csrin.get.hartId 187 imsic.i.msiInfo := io.csrin.get.msiInfo 188 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 189 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 190 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 191 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 192 imsic.i.csr.vgein := csrMod.toAIA.vgein 193 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 194 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 195 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 196 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 197 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 198 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 199 200 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 201 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 202 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 203 csrMod.fromAIA.meip := imsic.o.meip 204 csrMod.fromAIA.seip := imsic.o.seip 205 csrMod.fromAIA.vseip := imsic.o.vseip 206 csrMod.fromAIA.mtopei := imsic.o.mtopei 207 csrMod.fromAIA.stopei := imsic.o.stopei 208 csrMod.fromAIA.vstopei := imsic.o.vstopei 209 210 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 211 212 exceptionVec(EX_BP ) := isEbreak 213 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 214 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 215 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 216 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 217 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 218 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 219 220 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 221 222 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 223 val isXRetFlag = RegInit(false.B) 224 isXRetFlag := Mux1H(Seq( 225 DelayN(flush, 5) -> false.B, 226 isXRet -> true.B, 227 )) 228 229 flushPipe := csrMod.io.out.bits.flushPipe 230 231 // tlb 232 val tlb = Wire(new TlbCsrBundle) 233 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 234 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 235 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 236 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 237 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 238 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 239 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 240 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 241 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 242 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 243 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 244 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 245 246 // expose several csr bits for tlb 247 tlb.priv.mxr := csrMod.io.tlb.mxr 248 tlb.priv.sum := csrMod.io.tlb.sum 249 tlb.priv.vmxr := csrMod.io.tlb.vmxr 250 tlb.priv.vsum := csrMod.io.tlb.vsum 251 tlb.priv.spvp := csrMod.io.tlb.spvp 252 tlb.priv.virt := csrMod.io.tlb.dvirt 253 tlb.priv.imode := csrMod.io.tlb.imode 254 tlb.priv.dmode := csrMod.io.tlb.dmode 255 256 // Svpbmt extension enable 257 tlb.mPBMTE := csrMod.io.tlb.mPBMTE 258 tlb.hPBMTE := csrMod.io.tlb.hPBMTE 259 260 /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */ 261 io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR 262 io.out.valid := csrModOutValid 263 io.out.bits.ctrl.exceptionVec.get := exceptionVec 264 io.out.bits.ctrl.flushPipe.get := flushPipe 265 io.out.bits.res.data := csrMod.io.out.bits.rData 266 267 /** initialize NewCSR's io_out_ready from wrapper's io */ 268 csrMod.io.out.ready := io.out.ready 269 270 io.out.bits.res.redirect.get.valid := isXRet 271 val redirect = io.out.bits.res.redirect.get.bits 272 redirect := 0.U.asTypeOf(redirect) 273 redirect.level := RedirectLevel.flushAfter 274 redirect.robIdx := io.in.bits.ctrl.robIdx 275 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 276 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 277 redirect.cfiUpdate.predTaken := true.B 278 redirect.cfiUpdate.taken := true.B 279 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc 280 redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF 281 redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF 282 redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF 283 // Only mispred will send redirect to frontend 284 redirect.cfiUpdate.isMisPred := true.B 285 286 connect0LatencyCtrlSingal 287 288 // Todo: summerize all difftest skip condition 289 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 290 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 291 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 292 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 293 294 csrOut.isXRet := isXRetFlag 295 296 csrOut.trapTarget := csrMod.io.out.bits.targetPc 297 csrOut.interrupt := csrMod.io.status.interrupt 298 csrOut.wfi_event := csrMod.io.status.wfiEvent 299 300 csrOut.tlb := tlb 301 302 csrOut.debugMode := csrMod.io.status.debugMode 303 304 csrOut.customCtrl match { 305 case custom => 306 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 307 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 308 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 309 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 310 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 311 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 312 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 313 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 314 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 315 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 316 // ICache 317 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 318 // Load violation predictor 319 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 320 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 321 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 322 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 323 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 324 // Branch predictor 325 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 326 // Memory Block 327 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 328 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 329 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 330 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 331 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 332 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 333 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 334 // Rename 335 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 336 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 337 // distribute csr write signal 338 // write to frontend and memory 339 custom.distribute_csr.w.valid := csrWen 340 custom.distribute_csr.w.bits.addr := addr 341 custom.distribute_csr.w.bits.data := wdata 342 // rename single step 343 custom.singlestep := csrMod.io.status.singleStepFlag 344 // trigger 345 custom.frontend_trigger := csrMod.io.status.frontendTrigger 346 custom.mem_trigger := csrMod.io.status.memTrigger 347 // virtual mode 348 custom.virtMode := csrMod.io.status.privState.V.asBool 349 } 350 351 csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType 352 353 csrToDecode := csrMod.io.toDecode 354} 355 356class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 357 val hartId = Input(UInt(8.W)) 358 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 359 val clintTime = Input(ValidIO(UInt(64.W))) 360 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 361} 362 363class CSRToDecode(implicit p: Parameters) extends XSBundle { 364 val illegalInst = new Bundle { 365 /** 366 * illegal sfence.vma, sinval.vma 367 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 368 */ 369 val sfenceVMA = Bool() 370 371 /** 372 * illegal sfence.w.inval sfence.inval.ir 373 * raise EX_II when isModeHU 374 */ 375 val sfencePart = Bool() 376 377 /** 378 * illegal hfence.gvma, hinval.gvma 379 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 380 * the condition is the same as sfenceVMA 381 */ 382 val hfenceGVMA = Bool() 383 384 /** 385 * illegal hfence.vvma, hinval.vvma 386 * raise EX_II when isModeHU 387 */ 388 val hfenceVVMA = Bool() 389 390 /** 391 * illegal hlv, hlvx, and hsv 392 * raise EX_II when isModeHU && hstatus.HU=0 393 */ 394 val hlsv = Bool() 395 396 /** 397 * decode all fp inst or all vecfp inst 398 * raise EX_II when FS=Off 399 */ 400 val fsIsOff = Bool() 401 402 /** 403 * decode all vec inst 404 * raise EX_II when VS=Off 405 */ 406 val vsIsOff = Bool() 407 408 /** 409 * illegal wfi 410 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 411 */ 412 val wfi = Bool() 413 414 /** 415 * frm reserved 416 * raise EX_II when frm.data > 4 417 */ 418 val frm = Bool() 419 420 /** 421 * illegal CBO.ZERO 422 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE 423 */ 424 val cboZ = Bool() 425 426 /** 427 * illegal CBO.CLEAN/FLUSH 428 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE 429 */ 430 val cboCF = Bool() 431 432 /** 433 * illegal CBO.INVAL 434 * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off 435 */ 436 val cboI = Bool() 437 } 438 439 val virtualInst = new Bundle { 440 /** 441 * illegal sfence.vma, svinval.vma 442 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 443 */ 444 val sfenceVMA = Bool() 445 446 /** 447 * illegal sfence.w.inval sfence.inval.ir 448 * raise EX_VI when isModeVU 449 */ 450 val sfencePart = Bool() 451 452 /** 453 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 454 * raise EX_VI when isModeVS || isModeVU 455 */ 456 val hfence = Bool() 457 458 /** 459 * illegal hlv, hlvx, and hsv 460 * raise EX_VI when isModeVS || isModeVU 461 */ 462 val hlsv = Bool() 463 464 /** 465 * illegal wfi 466 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 467 */ 468 val wfi = Bool() 469 470 /** 471 * illegal CBO.ZERO 472 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE)) 473 */ 474 val cboZ = Bool() 475 476 /** 477 * illegal CBO.CLEAN/FLUSH 478 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE)) 479 */ 480 val cboCF = Bool() 481 482 /** 483 * illegal CBO.INVAL <br/> 484 * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/> 485 * isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/> 486 * isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/> 487 * ) <br/> 488 */ 489 val cboI = Bool() 490 } 491 492 val special = new Bundle { 493 /** 494 * execute CBO.INVAL and perform flush operation when <br/> 495 * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/> 496 * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 497 * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/> 498 * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 499 */ 500 val cboI2F = Bool() 501 } 502}