1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import utility._ 24import system._ 25import org.chipsalliance.cde.config._ 26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 27import xiangshan.frontend.icache.ICacheParameters 28import freechips.rocketchip.devices.debug._ 29import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 30import system._ 31import utility._ 32import utils._ 33import huancun._ 34import xiangshan._ 35import xiangshan.backend.dispatch.DispatchParameters 36import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 37import xiangshan.cache.DCacheParameters 38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 39import device.{EnableJtag, XSDebugModuleParams} 40import huancun._ 41import coupledL2._ 42import coupledL2.prefetch._ 43import xiangshan.frontend.icache.ICacheParameters 44 45class BaseConfig(n: Int) extends Config((site, here, up) => { 46 case XLen => 64 47 case DebugOptionsKey => DebugOptions() 48 case SoCParamsKey => SoCParameters() 49 case PMParameKey => PMParameters() 50 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 51 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 52 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 53 case JtagDTMKey => JtagDTMKey 54 case MaxHartIdBits => log2Up(n) max 6 55 case EnableJtag => true.B 56}) 57 58// Synthesizable minimal XiangShan 59// * It is still an out-of-order, super-scalaer arch 60// * L1 cache included 61// * L2 cache NOT included 62// * L3 cache included 63class MinimalConfig(n: Int = 1) extends Config( 64 new BaseConfig(n).alter((site, here, up) => { 65 case XSTileKey => up(XSTileKey).map( 66 p => p.copy( 67 DecodeWidth = 6, 68 RenameWidth = 6, 69 RobCommitWidth = 8, 70 FetchWidth = 4, 71 VirtualLoadQueueSize = 24, 72 LoadQueueRARSize = 24, 73 LoadQueueRAWSize = 12, 74 LoadQueueReplaySize = 24, 75 LoadUncacheBufferSize = 8, 76 LoadQueueNWriteBanks = 4, // NOTE: make sure that LoadQueue{RAR, RAW, Replay}Size is divided by LoadQueueNWriteBanks. 77 RollbackGroupSize = 8, 78 StoreQueueSize = 20, 79 StoreQueueNWriteBanks = 4, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 80 StoreQueueForwardWithMask = true, 81 // ============ VLSU ============ 82 VlMergeBufferSize = 8, 83 VsMergeBufferSize = 8, 84 UopWritebackWidth = 2, 85 SplitBufferSize = 8, 86 // ============================== 87 RobSize = 48, 88 RabSize = 96, 89 FtqSize = 8, 90 IBufSize = 24, 91 IBufNBank = 6, 92 StoreBufferSize = 4, 93 StoreBufferThreshold = 3, 94 IssueQueueSize = 10, 95 IssueQueueCompEntrySize = 4, 96 dpParams = DispatchParameters( 97 IntDqSize = 12, 98 FpDqSize = 12, 99 LsDqSize = 12, 100 IntDqDeqWidth = 8, 101 FpDqDeqWidth = 6, 102 VecDqDeqWidth = 6, 103 LsDqDeqWidth = 6 104 ), 105 intPreg = IntPregParams( 106 numEntries = 64, 107 numRead = None, 108 numWrite = None, 109 ), 110 vfPreg = VfPregParams( 111 numEntries = 160, 112 numRead = None, 113 numWrite = None, 114 ), 115 icacheParameters = ICacheParameters( 116 nSets = 64, // 16KB ICache 117 tagECC = Some("parity"), 118 dataECC = Some("parity"), 119 replacer = Some("setplru"), 120 nMissEntries = 2, 121 nReleaseEntries = 1, 122 nProbeEntries = 2, 123 // fdip 124 enableICachePrefetch = true, 125 prefetchToL1 = false, 126 ), 127 dcacheParametersOpt = Some(DCacheParameters( 128 nSets = 64, // 32KB DCache 129 nWays = 8, 130 tagECC = Some("secded"), 131 dataECC = Some("secded"), 132 replacer = Some("setplru"), 133 nMissEntries = 4, 134 nProbeEntries = 4, 135 nReleaseEntries = 8, 136 nMaxPrefetchEntry = 2, 137 )), 138 EnableBPD = false, // disable TAGE 139 EnableLoop = false, 140 itlbParameters = TLBParameters( 141 name = "itlb", 142 fetchi = true, 143 useDmode = false, 144 NWays = 4, 145 ), 146 ldtlbParameters = TLBParameters( 147 name = "ldtlb", 148 NWays = 4, 149 partialStaticPMP = true, 150 outsideRecvFlush = true, 151 outReplace = false, 152 lgMaxSize = 4 153 ), 154 sttlbParameters = TLBParameters( 155 name = "sttlb", 156 NWays = 4, 157 partialStaticPMP = true, 158 outsideRecvFlush = true, 159 outReplace = false, 160 lgMaxSize = 4 161 ), 162 hytlbParameters = TLBParameters( 163 name = "hytlb", 164 NWays = 4, 165 partialStaticPMP = true, 166 outsideRecvFlush = true, 167 outReplace = false, 168 lgMaxSize = 4 169 ), 170 pftlbParameters = TLBParameters( 171 name = "pftlb", 172 NWays = 4, 173 partialStaticPMP = true, 174 outsideRecvFlush = true, 175 outReplace = false, 176 lgMaxSize = 4 177 ), 178 btlbParameters = TLBParameters( 179 name = "btlb", 180 NWays = 4, 181 ), 182 l2tlbParameters = L2TLBParameters( 183 l1Size = 4, 184 l2nSets = 4, 185 l2nWays = 4, 186 l3nSets = 4, 187 l3nWays = 8, 188 spSize = 2, 189 ), 190 L2CacheParamsOpt = Some(L2Param( 191 name = "L2", 192 ways = 8, 193 sets = 128, 194 echoField = Seq(huancun.DirtyField()), 195 prefetch = Nil, 196 clientCaches = Seq(L1Param( 197 "dcache", 198 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 199 )), 200 )), 201 L2NBanks = 2, 202 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 203 ) 204 ) 205 case SoCParamsKey => 206 val tiles = site(XSTileKey) 207 up(SoCParamsKey).copy( 208 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 209 sets = 1024, 210 inclusive = false, 211 clientCaches = tiles.map{ core => 212 val clientDirBytes = tiles.map{ t => 213 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 214 }.sum 215 val l2params = core.L2CacheParamsOpt.get.toCacheParams 216 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 217 }, 218 simulation = !site(DebugOptionsKey).FPGAPlatform, 219 prefetch = None 220 )), 221 L3NBanks = 1 222 ) 223 }) 224) 225 226// Non-synthesizable MinimalConfig, for fast simulation only 227class MinimalSimConfig(n: Int = 1) extends Config( 228 new MinimalConfig(n).alter((site, here, up) => { 229 case XSTileKey => up(XSTileKey).map(_.copy( 230 dcacheParametersOpt = None, 231 softPTW = true 232 )) 233 case SoCParamsKey => up(SoCParamsKey).copy( 234 L3CacheParamsOpt = None 235 ) 236 }) 237) 238 239class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 240 case XSTileKey => 241 val sets = n * 1024 / ways / 64 242 up(XSTileKey).map(_.copy( 243 dcacheParametersOpt = Some(DCacheParameters( 244 nSets = sets, 245 nWays = ways, 246 tagECC = Some("secded"), 247 dataECC = Some("secded"), 248 replacer = Some("setplru"), 249 nMissEntries = 16, 250 nProbeEntries = 8, 251 nReleaseEntries = 18, 252 nMaxPrefetchEntry = 6, 253 )) 254 )) 255}) 256 257class WithNKBL2 258( 259 n: Int, 260 ways: Int = 8, 261 inclusive: Boolean = true, 262 banks: Int = 1, 263 tp: Boolean = true 264) extends Config((site, here, up) => { 265 case XSTileKey => 266 require(inclusive, "L2 must be inclusive") 267 val upParams = up(XSTileKey) 268 val l2sets = n * 1024 / banks / ways / 64 269 upParams.map(p => p.copy( 270 L2CacheParamsOpt = Some(L2Param( 271 name = "L2", 272 ways = ways, 273 sets = l2sets, 274 clientCaches = Seq(L1Param( 275 "dcache", 276 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 277 ways = p.dcacheParametersOpt.get.nWays + 2, 278 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 279 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 280 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 281 )), 282 reqField = Seq(utility.ReqSourceField()), 283 echoField = Seq(huancun.DirtyField()), 284 prefetch = Seq(PrefetchReceiverParams(), BOPParameters()) ++ (if (tp) Seq(TPParameters()) else Nil), 285 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 286 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 287 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 288 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 289 )), 290 L2NBanks = banks 291 )) 292}) 293 294class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 295 case SoCParamsKey => 296 val sets = n * 1024 / banks / ways / 64 297 val tiles = site(XSTileKey) 298 val clientDirBytes = tiles.map{ t => 299 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 300 }.sum 301 up(SoCParamsKey).copy( 302 L3NBanks = banks, 303 L3CacheParamsOpt = Some(HCCacheParameters( 304 name = "L3", 305 level = 3, 306 ways = ways, 307 sets = sets, 308 inclusive = inclusive, 309 clientCaches = tiles.map{ core => 310 val l2params = core.L2CacheParamsOpt.get.toCacheParams 311 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2) 312 }, 313 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 314 ctrl = Some(CacheCtrl( 315 address = 0x39000000, 316 numCores = tiles.size 317 )), 318 reqField = Seq(utility.ReqSourceField()), 319 sramClkDivBy2 = true, 320 sramDepthDiv = 4, 321 tagECC = Some("secded"), 322 dataECC = Some("secded"), 323 simulation = !site(DebugOptionsKey).FPGAPlatform, 324 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()), 325 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters()) 326 )) 327 ) 328}) 329 330class WithL3DebugConfig extends Config( 331 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 332) 333 334class MinimalL3DebugConfig(n: Int = 1) extends Config( 335 new WithL3DebugConfig ++ new MinimalConfig(n) 336) 337 338class DefaultL3DebugConfig(n: Int = 1) extends Config( 339 new WithL3DebugConfig ++ new BaseConfig(n) 340) 341 342class WithFuzzer extends Config((site, here, up) => { 343 case DebugOptionsKey => up(DebugOptionsKey).copy( 344 EnablePerfDebug = false, 345 ) 346 case SoCParamsKey => up(SoCParamsKey).copy( 347 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 348 enablePerf = false, 349 )), 350 ) 351 case XSTileKey => up(XSTileKey).zipWithIndex.map{ case (p, i) => 352 p.copy( 353 L2CacheParamsOpt = Some(up(XSTileKey)(i).L2CacheParamsOpt.get.copy( 354 enablePerf = false, 355 )), 356 ) 357 } 358}) 359 360class MinimalAliasDebugConfig(n: Int = 1) extends Config( 361 new WithNKBL3(512, inclusive = false) ++ 362 new WithNKBL2(256, inclusive = true) ++ 363 new WithNKBL1D(128) ++ 364 new MinimalConfig(n) 365) 366 367class MediumConfig(n: Int = 1) extends Config( 368 new WithNKBL3(4096, inclusive = false, banks = 4) 369 ++ new WithNKBL2(512, inclusive = true) 370 ++ new WithNKBL1D(128) 371 ++ new BaseConfig(n) 372) 373 374class FuzzConfig(dummy: Int = 0) extends Config( 375 new WithFuzzer 376 ++ new DefaultConfig(1) 377) 378 379class DefaultConfig(n: Int = 1) extends Config( 380 new WithNKBL3(16 * 1024, inclusive = false, banks = 4, ways = 16) 381 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4) 382 ++ new WithNKBL1D(64, ways = 8) 383 ++ new BaseConfig(n) 384) 385 386class WithCHI extends Config((_, _, _) => { 387 case EnableCHI => true 388}) 389 390class KunminghuV2Config(n: Int = 1) extends Config( 391 new WithCHI 392 ++ new Config((site, here, up) => { 393 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 394 }) 395 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 396 ++ new WithNKBL1D(64, ways = 8) 397 ++ new BaseConfig(n) 398)