1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.dispatch 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import chisel3.util.experimental.decode._ 23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 24import utility._ 25import xiangshan.ExceptionNO._ 26import xiangshan._ 27import xiangshan.backend.rob.{RobDispatchTopDownIO, RobEnqIO} 28import xiangshan.backend.Bundles.{DecodedInst, DynInst, ExuVec, IssueQueueIQWakeUpBundle} 29import xiangshan.backend.fu.{FuConfig, FuType} 30import xiangshan.backend.rename.{BusyTable, VlBusyTable} 31import xiangshan.backend.fu.{FuConfig, FuType} 32import xiangshan.backend.rename.BusyTableReadIO 33import xiangshan.backend.datapath.DataConfig._ 34import xiangshan.backend.datapath.WbConfig._ 35import xiangshan.backend.datapath.DataSource 36import xiangshan.backend.datapath.WbConfig.VfWB 37import xiangshan.backend.fu.FuType.FuTypeOrR 38import xiangshan.backend.dispatch.Dispatch2IqFpImp 39import xiangshan.backend.regcache.{RCTagTableReadPort, RegCacheTagTable} 40import xiangshan.mem.MemCoreTopDownIO 41import xiangshan.mem.mdp._ 42import xiangshan.mem.{HasVLSUParameters, _} 43 44 45// TODO delete trigger message from frontend to iq 46class NewDispatch(implicit p: Parameters) extends XSModule with HasPerfEvents with HasVLSUParameters { 47 // std IQ donot need dispatch, only copy sta IQ, but need sta IQ's ready && std IQ's ready 48 val allIssueParams = backendParams.allIssueParams.filter(_.StdCnt == 0) 49 val allExuParams = allIssueParams.map(_.exuBlockParams).flatten 50 val allFuConfigs = allExuParams.map(_.fuConfigs).flatten.toSet.toSeq 51 val sortedFuConfigs = allFuConfigs.sortBy(_.fuType.id) 52 println(s"[NewDispatch] ${allExuParams.map(_.name)}") 53 println(s"[NewDispatch] ${allFuConfigs.map(_.name)}") 54 println(s"[NewDispatch] ${allFuConfigs.map(_.fuType.id)}") 55 println(s"[NewDispatch] ${sortedFuConfigs.map(_.name)}") 56 println(s"[NewDispatch] ${sortedFuConfigs.map(_.fuType.id)}") 57 val fuConfigsInIssueParams = allIssueParams.map(_.allExuParams.map(_.fuConfigs).flatten.toSet.toSeq) 58 val fuMapIQIdx = sortedFuConfigs.map( fu => { 59 val fuInIQIdx = fuConfigsInIssueParams.zipWithIndex.filter { case (f, i) => f.contains(fu) }.map(_._2) 60 (fu -> fuInIQIdx) 61 } 62 ) 63 fuMapIQIdx.map { case (fu, iqidx) => 64 println(s"[NewDispatch] ${fu.name} $iqidx") 65 } 66 val sameIQIdxFus = fuMapIQIdx.map{ case (fu, iqidx) => 67 fuMapIQIdx.filter(_._2 == iqidx).map(_._1) -> iqidx 68 }.toSet.toSeq 69 val needMultiIQ = sameIQIdxFus.sortBy(_._1.head.fuType.id).filter(_._2.size > 1) 70 val needSingleIQ = sameIQIdxFus.sortBy(_._1.head.fuType.id).filter(_._2.size == 1) 71 needMultiIQ.map { case (fus, iqidx) => 72 println(s"[NewDispatch] needMultiIQ: ${fus.map(_.name)} $iqidx") 73 } 74 needSingleIQ.map { case (fus, iqidx) => 75 println(s"[NewDispatch] needSingleIQ: ${fus.map(_.name)} $iqidx") 76 } 77 val fuConfigsInExuParams = allExuParams.map(_.fuConfigs) 78 val fuMapExuIdx = sortedFuConfigs.map { case fu => { 79 val fuInExuIdx = fuConfigsInExuParams.zipWithIndex.filter { case (f, i) => f.contains(fu) }.map(_._2) 80 (fu -> fuInExuIdx) 81 } 82 } 83 val sameExuIdxFus = fuMapExuIdx.map { case (fu, exuidx) => 84 fuMapExuIdx.filter(_._2 == exuidx).map(_._1) -> exuidx 85 }.toSet.toSeq 86 val needMultiExu = sameExuIdxFus.sortBy(_._1.head.fuType.id).filter(_._2.size > 1).filter{ x => 87 x._1.map(y => fuMapIQIdx.filter(_._1 == y).head._2.size > 1).reduce(_ && _) 88 } 89 90 val exuNum = allExuParams.size 91 val maxIQSize = allIssueParams.map(_.numEntries).max 92 val IQEnqSum = allIssueParams.map(_.numEnq).sum 93 94 val io = IO(new Bundle { 95 // from rename 96 val renameIn = Vec(RenameWidth, Flipped(ValidIO(new DecodedInst))) 97 val fromRename = Vec(RenameWidth, Flipped(DecoupledIO(new DynInst))) 98 val toRenameAllFire = Output(Bool()) 99 // enq Rob 100 val enqRob = Flipped(new RobEnqIO) 101 // IssueQueues 102 val IQValidNumVec = Vec(exuNum, Input(UInt(maxIQSize.U.getWidth.W))) 103 val toIssueQueues = Vec(IQEnqSum, DecoupledIO(new DynInst)) 104 // to busyTable 105 // set preg state to ready (write back regfile) 106 val wbPregsInt = Vec(backendParams.numPregWb(IntData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 107 val wbPregsFp = Vec(backendParams.numPregWb(FpData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 108 val wbPregsVec = Vec(backendParams.numPregWb(VecData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 109 val wbPregsV0 = Vec(backendParams.numPregWb(V0Data()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 110 val wbPregsVl = Vec(backendParams.numPregWb(VlData()), Flipped(ValidIO(UInt(PhyRegIdxWidth.W)))) 111 val wakeUpAll = new Bundle { 112 val wakeUpInt: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.intSchdParams.get.genIQWakeUpOutValidBundle) 113 val wakeUpFp: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.fpSchdParams.get.genIQWakeUpOutValidBundle) 114 val wakeUpVec: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.vfSchdParams.get.genIQWakeUpOutValidBundle) 115 val wakeUpMem: MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = Flipped(backendParams.memSchdParams.get.genIQWakeUpOutValidBundle) 116 } 117 val og0Cancel = Input(ExuVec()) 118 val ldCancel = Vec(backendParams.LdExuCnt, Flipped(new LoadCancelIO)) 119 // to vlbusytable 120 val vlWriteBackInfo = new Bundle { 121 val vlFromIntIsZero = Input(Bool()) 122 val vlFromIntIsVlmax = Input(Bool()) 123 val vlFromVfIsZero = Input(Bool()) 124 val vlFromVfIsVlmax = Input(Bool()) 125 } 126 // from MemBlock 127 val fromMem = new Bundle { 128 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 129 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 130 val lqDeqPtr = Input(new LqPtr) 131 val sqDeqPtr = Input(new SqPtr) 132 // from lsq 133 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 134 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 135 } 136 //toMem 137 val toMem = new Bundle { 138 val lsqEnqIO = Flipped(new LsqEnqIO) 139 } 140 // redirect 141 val redirect = Flipped(ValidIO(new Redirect)) 142 // singleStep 143 val singleStep = Input(Bool()) 144 // lfst 145 val lfst = new DispatchLFSTIO 146 147 // perf only 148 val robHead = Input(new DynInst) 149 val stallReason = Flipped(new StallReasonIO(RenameWidth)) 150 val lqCanAccept = Input(Bool()) 151 val sqCanAccept = Input(Bool()) 152 val robHeadNotReady = Input(Bool()) 153 val robFull = Input(Bool()) 154 val debugTopDown = new Bundle { 155 val fromRob = Flipped(new RobDispatchTopDownIO) 156 val fromCore = new CoreDispatchTopDownIO 157 } 158 }) 159 // Deq for std's IQ is not assigned in Dispatch2Iq, so add one more src for it. 160 val issueBlockParams = backendParams.allIssueParams 161 val renameIn = io.renameIn 162 val fromRename = io.fromRename 163 io.toRenameAllFire := io.fromRename.map(x => !x.valid || x.fire).reduce(_ && _) 164 val fromRenameUpdate = Wire(Vec(RenameWidth, Flipped(ValidIO(new DynInst)))) 165 fromRenameUpdate := fromRename 166 val renameWidth = io.fromRename.size 167 val issueQueueCount = io.IQValidNumVec 168 val issueQueueNum = allIssueParams.size 169 // int fp vec v0 vl 170 val numRegType = 5 171 val idxRegTypeInt = allFuConfigs.map(x => { 172 x.srcData.map(xx => { 173 xx.zipWithIndex.filter(y => IntRegSrcDataSet.contains(y._1)).map(_._2) 174 }).flatten 175 }).flatten.toSet.toSeq.sorted 176 val idxRegTypeFp = allFuConfigs.map(x => { 177 x.srcData.map(xx => { 178 xx.zipWithIndex.filter(y => FpRegSrcDataSet.contains(y._1)).map(_._2) 179 }).flatten 180 }).flatten.toSet.toSeq.sorted 181 val idxRegTypeVec = allFuConfigs.map(x => { 182 x.srcData.map(xx => { 183 xx.zipWithIndex.filter(y => VecRegSrcDataSet.contains(y._1)).map(_._2) 184 }).flatten 185 }).flatten.toSet.toSeq.sorted 186 val idxRegTypeV0 = allFuConfigs.map(x => { 187 x.srcData.map(xx => { 188 xx.zipWithIndex.filter(y => V0RegSrcDataSet.contains(y._1)).map(_._2) 189 }).flatten 190 }).flatten.toSet.toSeq.sorted 191 val idxRegTypeVl = allFuConfigs.map(x => { 192 x.srcData.map(xx => { 193 xx.zipWithIndex.filter(y => VlRegSrcDataSet.contains(y._1)).map(_._2) 194 }).flatten 195 }).flatten.toSet.toSeq.sorted 196 println(s"[NewDispatch] idxRegTypeInt: $idxRegTypeInt") 197 println(s"[NewDispatch] idxRegTypeFp: $idxRegTypeFp") 198 println(s"[NewDispatch] idxRegTypeVec: $idxRegTypeVec") 199 println(s"[NewDispatch] idxRegTypeV0: $idxRegTypeV0") 200 println(s"[NewDispatch] idxRegTypeVl: $idxRegTypeVl") 201 val numRegSrc: Int = issueBlockParams.map(_.exuBlockParams.map( 202 x => if (x.hasStdFu) x.numRegSrc + 1 else x.numRegSrc 203 ).max).max 204 205 val numRegSrcInt: Int = issueBlockParams.map(_.exuBlockParams.map( 206 x => if (x.hasStdFu) x.numIntSrc + 1 else x.numIntSrc 207 ).max).max 208 val numRegSrcFp: Int = issueBlockParams.map(_.exuBlockParams.map( 209 x => if (x.hasStdFu) x.numFpSrc + 1 else x.numFpSrc 210 ).max).max 211 val numRegSrcVf: Int = issueBlockParams.map(_.exuBlockParams.map( 212 x => x.numVecSrc 213 ).max).max 214 val numRegSrcV0: Int = issueBlockParams.map(_.exuBlockParams.map( 215 x => x.numV0Src 216 ).max).max 217 val numRegSrcVl: Int = issueBlockParams.map(_.exuBlockParams.map( 218 x => x.numVlSrc 219 ).max).max 220 221 println(s"[Dispatch2Iq] numRegSrc: ${numRegSrc}, numRegSrcInt: ${numRegSrcInt}, numRegSrcFp: ${numRegSrcFp}, " + 222 s"numRegSrcVf: ${numRegSrcVf}, numRegSrcV0: ${numRegSrcV0}, numRegSrcVl: ${numRegSrcVl}") 223 224 // RegCacheTagTable Module 225 val rcTagTable = Module(new RegCacheTagTable(numRegSrcInt * renameWidth)) 226 // BusyTable Modules 227 val intBusyTable = Module(new BusyTable(numRegSrcInt * renameWidth, backendParams.numPregWb(IntData()), IntPhyRegs, IntWB())) 228 val fpBusyTable = Module(new BusyTable(numRegSrcFp * renameWidth, backendParams.numPregWb(FpData()), FpPhyRegs, FpWB())) 229 val vecBusyTable = Module(new BusyTable(numRegSrcVf * renameWidth, backendParams.numPregWb(VecData()), VfPhyRegs, VfWB())) 230 val v0BusyTable = Module(new BusyTable(numRegSrcV0 * renameWidth, backendParams.numPregWb(V0Data()), V0PhyRegs, V0WB())) 231 val vlBusyTable = Module(new VlBusyTable(numRegSrcVl * renameWidth, backendParams.numPregWb(VlData()), VlPhyRegs, VlWB())) 232 vlBusyTable.io_vl_Wb.vlWriteBackInfo := io.vlWriteBackInfo 233 val busyTables = Seq(intBusyTable, fpBusyTable, vecBusyTable, v0BusyTable, vlBusyTable) 234 val wbPregs = Seq(io.wbPregsInt, io.wbPregsFp, io.wbPregsVec, io.wbPregsV0, io.wbPregsVl) 235 val idxRegType = Seq(idxRegTypeInt, idxRegTypeFp, idxRegTypeVec, idxRegTypeV0, idxRegTypeVl) 236 val allocPregsValid = Wire(Vec(busyTables.size, Vec(RenameWidth, Bool()))) 237 allocPregsValid(0) := VecInit(fromRename.map(x => x.valid && x.bits.rfWen && !x.bits.eliminatedMove)) 238 allocPregsValid(1) := VecInit(fromRename.map(x => x.valid && x.bits.fpWen)) 239 allocPregsValid(2) := VecInit(fromRename.map(x => x.valid && x.bits.vecWen)) 240 allocPregsValid(3) := VecInit(fromRename.map(x => x.valid && x.bits.v0Wen)) 241 allocPregsValid(4) := VecInit(fromRename.map(x => x.valid && x.bits.vlWen)) 242 val allocPregs = Wire(Vec(busyTables.size, Vec(RenameWidth, ValidIO(UInt(PhyRegIdxWidth.W))))) 243 allocPregs.zip(allocPregsValid).map(x =>{ 244 x._1.zip(x._2).zipWithIndex.map{case ((sink, source), i) => { 245 sink.valid := source 246 sink.bits := fromRename(i).bits.pdest 247 }} 248 }) 249 val wakeUp = io.wakeUpAll.wakeUpInt ++ io.wakeUpAll.wakeUpFp ++ io.wakeUpAll.wakeUpVec ++ io.wakeUpAll.wakeUpMem 250 busyTables.zip(wbPregs).zip(allocPregs).map{ case ((b, w), a) => { 251 b.io.wakeUpInt := io.wakeUpAll.wakeUpInt 252 b.io.wakeUpFp := io.wakeUpAll.wakeUpFp 253 b.io.wakeUpVec := io.wakeUpAll.wakeUpVec 254 b.io.wakeUpMem := io.wakeUpAll.wakeUpMem 255 b.io.og0Cancel := io.og0Cancel 256 b.io.ldCancel := io.ldCancel 257 b.io.wbPregs := w 258 b.io.allocPregs := a 259 }} 260 rcTagTable.io.allocPregs.zip(allocPregs(0)).map(x => x._1 := x._2) 261 rcTagTable.io.wakeupFromIQ := io.wakeUpAll.wakeUpInt ++ io.wakeUpAll.wakeUpMem 262 rcTagTable.io.og0Cancel := io.og0Cancel 263 rcTagTable.io.ldCancel := io.ldCancel 264 busyTables.zip(idxRegType).zipWithIndex.map { case ((b, idxseq), i) => { 265 val readAddr = VecInit(fromRename.map(x => x.bits.psrc.zipWithIndex.filter(xx => idxseq.contains(xx._2)).map(_._1)).flatten) 266 val readValid = VecInit(fromRename.map(x => x.bits.psrc.zipWithIndex.filter(xx => idxseq.contains(xx._2)).map(y => x.valid && SrcType.isXp(x.bits.srcType(y._2)))).flatten) 267 b.io.read.map(_.req).zip(readAddr).map(x => x._1 := x._2) 268 // only int src need srcLoadDependency, src0 src1 269 if (i == 0) { 270 val srcLoadDependencyUpdate = fromRenameUpdate.map(x => x.bits.srcLoadDependency.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 271 val srcType = fromRenameUpdate.map(x => x.bits.srcType.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 272 // for std, int src need srcLoadDependency, fp src donot need srcLoadDependency 273 srcLoadDependencyUpdate.lazyZip(b.io.read.map(_.loadDependency)).lazyZip(srcType).map{ case (sink, source, srctype) => 274 sink := Mux(SrcType.isXp(srctype), source, 0.U.asTypeOf(sink)) 275 } 276 // only int src need rcTag 277 val rcTagUpdate = fromRenameUpdate.map(x => x.bits.regCacheIdx.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 278 rcTagUpdate.zip(rcTagTable.io.readPorts.map(_.addr)).map(x => x._1 := x._2) 279 val useRegCacheUpdate = fromRenameUpdate.map(x => x.bits.useRegCache.zipWithIndex.filter(x => idxseq.contains(x._2)).map(_._1)).flatten 280 useRegCacheUpdate.zip(rcTagTable.io.readPorts.map(_.valid)).map(x => x._1 := x._2) 281 rcTagTable.io.readPorts.map(_.ren).zip(readValid).map(x => x._1 := x._2) 282 rcTagTable.io.readPorts.map(_.tag).zip(readAddr).map(x => x._1 := x._2) 283 } 284 }} 285 val allSrcState = Wire(Vec(renameWidth, Vec(numRegSrc, Vec(numRegType, Bool())))) 286 for (i <- 0 until renameWidth){ 287 for (j <- 0 until numRegSrc){ 288 for (k <- 0 until numRegType){ 289 if (!idxRegType(k).contains(j)) { 290 allSrcState(i)(j)(k) := false.B 291 } 292 else { 293 val readidx = i * idxRegType(k).size + idxRegType(k).indexOf(j) 294 val readEn = k match { 295 case 0 => SrcType.isXp(fromRename(i).bits.srcType(j)) 296 case 1 => SrcType.isFp(fromRename(i).bits.srcType(j)) 297 case 2 => SrcType.isVp(fromRename(i).bits.srcType(j)) 298 case 3 => SrcType.isV0(fromRename(i).bits.srcType(j)) 299 case 4 => true.B 300 } 301 allSrcState(i)(j)(k) := readEn && busyTables(k).io.read(readidx).resp || SrcType.isImm(fromRename(i).bits.srcType(j)) 302 } 303 } 304 } 305 } 306 307 // eliminate old vd 308 val ignoreOldVdVec = Wire(Vec(renameWidth, Bool())) 309 for (i <- 0 until renameWidth){ 310 // numRegSrcVf - 1 is old vd 311 var j = numRegSrcVf - 1 312 // 2 is type of vec 313 var k = 2 314 val readidx = i * idxRegType(k).size + idxRegType(k).indexOf(j) 315 val readEn = SrcType.isVp(fromRename(i).bits.srcType(j)) 316 val isDependOldVd = fromRename(i).bits.vpu.isDependOldVd 317 val isWritePartVd = fromRename(i).bits.vpu.isWritePartVd 318 val vta = fromRename(i).bits.vpu.vta 319 val vma = fromRename(i).bits.vpu.vma 320 val vm = fromRename(i).bits.vpu.vm 321 val vlIsVlmax = vlBusyTable.io_vl_read.vlReadInfo(i).is_vlmax 322 val vlIsNonZero = !vlBusyTable.io_vl_read.vlReadInfo(i).is_zero 323 val ignoreTail = vlIsVlmax && (vm =/= 0.U || vma) && !isWritePartVd 324 val ignoreWhole = (vm =/= 0.U || vma) && vta 325 val ignoreOldVd = vlBusyTable.io.read(i).resp && vlIsNonZero && !isDependOldVd && (ignoreTail || ignoreWhole) 326 ignoreOldVdVec(i) := readEn && ignoreOldVd 327 allSrcState(i)(j)(k) := readEn && (busyTables(k).io.read(readidx).resp || ignoreOldVd) || SrcType.isImm(fromRename(i).bits.srcType(j)) 328 } 329 330 // Singlestep should only commit one machine instruction after dret, and then hart enter debugMode according to singlestep exception. 331 val s_holdRobidx :: s_updateRobidx :: Nil = Enum(2) 332 val singleStepState = RegInit(s_updateRobidx) 333 334 val robidxStepNext = WireInit(0.U.asTypeOf(fromRename(0).bits.robIdx)) 335 val robidxStepReg = RegInit(0.U.asTypeOf(fromRename(0).bits.robIdx)) 336 val robidxCanCommitStepping = WireInit(0.U.asTypeOf(fromRename(0).bits.robIdx)) 337 338 when(!io.singleStep) { 339 singleStepState := s_updateRobidx 340 }.elsewhen(io.singleStep && fromRename(0).fire && io.enqRob.req(0).valid) { 341 singleStepState := s_holdRobidx 342 robidxStepNext := fromRename(0).bits.robIdx 343 } 344 345 when(singleStepState === s_updateRobidx) { 346 robidxStepReg := robidxStepNext 347 robidxCanCommitStepping := robidxStepNext 348 }.elsewhen(singleStepState === s_holdRobidx) { 349 robidxStepReg := robidxStepReg 350 robidxCanCommitStepping := robidxStepReg 351 } 352 353 val minIQSelAll = Wire(Vec(needMultiExu.size, Vec(renameWidth, Vec(issueQueueNum, Bool())))) 354 needMultiExu.zipWithIndex.map{ case ((fus, exuidx), needMultiExuidx) => { 355 val suffix = fus.map(_.name).mkString("_") 356 val iqNum = exuidx.size 357 val iqidx = allIssueParams.map(_.exuBlockParams.map(_.fuConfigs).flatten.toSet.toSeq).zipWithIndex.filter{x => fus.toSet.subsetOf(x._1.toSet)}.map(_._2) 358 println(s"[NewDispatch] ${fus.map(_.name)};iqidx:$iqidx;exuIdx:$exuidx") 359 val compareMatrix = Wire(Vec(iqNum, Vec(iqNum, Bool()))).suggestName(s"compareMatrix_$suffix") 360 for (i <- 0 until iqNum) { 361 for (j <- 0 until iqNum) { 362 if (i == j) compareMatrix(i)(j) := false.B 363 else if (i < j) compareMatrix(i)(j) := issueQueueCount(exuidx(i)) < issueQueueCount(exuidx(j)) 364 else compareMatrix(i)(j) := !compareMatrix(j)(i) 365 } 366 } 367 val IQSort = Reg(Vec(iqNum, Vec(iqNum, Bool()))).suggestName(s"IQSort_$suffix}") 368 for (i <- 0 until iqNum){ 369 // i = 0 minimum iq, i = iqNum - 1 -> maximum iq 370 IQSort(i) := compareMatrix.map(x => PopCount(x) === (iqNum - 1 - i).U) 371 } 372 val minIQSel = Wire(Vec(renameWidth, Vec(issueQueueNum, Bool()))).suggestName(s"minIQSel_$suffix") 373 for (i <- 0 until renameWidth){ 374 val minIQSel_ith = IQSort(i % iqNum) 375 println(s"minIQSel_${i}th_$suffix = IQSort(${i % iqNum})") 376 for (j <- 0 until issueQueueNum){ 377 minIQSel(i)(j) := false.B 378 if (iqidx.contains(j)){ 379 minIQSel(i)(j) := minIQSel_ith(iqidx.indexOf(j)) 380 println(s"minIQSel_${suffix}_${i}_${j} = minIQSel_ith(iqidx.indexOf(${j}))") 381 } 382 } 383 } 384 minIQSelAll(needMultiExuidx) := minIQSel 385 if (backendParams.debugEn){ 386 dontTouch(compareMatrix) 387 dontTouch(IQSort) 388 dontTouch(minIQSel) 389 } 390 } 391 } 392 val fuConfigSeq = needMultiExu.map(_._1) 393 val fuTypeOH = Wire(Vec(renameWidth, Vec(needMultiExu.size, Bool()))) 394 fuTypeOH.zip(renameIn).map{ case(oh, in) => { 395 oh := fuConfigSeq.map(x => x.map(xx => in.bits.fuType(xx.fuType.id)).reduce(_ || _) && in.valid) 396 } 397 } 398 // not count itself 399 val popFuTypeOH = Wire(Vec(renameWidth, Vec(needMultiExu.size, UInt((renameWidth-1).U.getWidth.W)))) 400 popFuTypeOH.zipWithIndex.map{ case (pop, idx) => { 401 if (idx == 0){ 402 pop := 0.U.asTypeOf(pop) 403 } 404 else { 405 pop.zipWithIndex.map{ case (p, i) => { 406 p := PopCount(fuTypeOH.take(idx).map(x => x(i))) 407 } 408 } 409 } 410 }} 411 val uopSelIQ = Reg(Vec(renameWidth, Vec(issueQueueNum, Bool()))) 412 val fuTypeOHSingle = Wire(Vec(renameWidth, Vec(needSingleIQ.size, Bool()))) 413 fuTypeOHSingle.zip(renameIn).map{ case (oh, in) => { 414 oh := needSingleIQ.map(_._1).map(x => x.map(xx => in.valid && in.bits.fuType(xx.fuType.id)).reduce(_ || _)) 415 }} 416 val uopSelIQSingle = Wire(Vec(needSingleIQ.size, Vec(issueQueueNum, Bool()))) 417 uopSelIQSingle := VecInit(needSingleIQ.map(_._2).flatten.map(x => VecInit((1.U(issueQueueNum.W) << x)(issueQueueNum-1, 0).asBools))) 418 uopSelIQ.zipWithIndex.map{ case (u, i) => { 419 when(io.toRenameAllFire){ 420 u := Mux(renameIn(i).valid, 421 Mux(fuTypeOH(i).asUInt.orR, 422 Mux1H(fuTypeOH(i), minIQSelAll)(Mux1H(fuTypeOH(i), popFuTypeOH(i))), 423 Mux1H(fuTypeOHSingle(i), uopSelIQSingle)), 424 0.U.asTypeOf(u) 425 ) 426 }.elsewhen(io.fromRename(i).fire){ 427 u := 0.U.asTypeOf(u) 428 } 429 }} 430 val uopSelIQMatrix = Wire(Vec(renameWidth, Vec(issueQueueNum, UInt(renameWidth.U.getWidth.W)))) 431 uopSelIQMatrix.zipWithIndex.map{ case (u, i) => { 432 u.zipWithIndex.map{ case (uu, j) => { 433 uu := PopCount(uopSelIQ.take(i+1).map(x => x.zipWithIndex.filter(_._2 == j).map(_._1)).flatten) 434 }} 435 }} 436 val IQSelUop = Wire(Vec(IQEnqSum, ValidIO(new DynInst))) 437 val uopBlockByIQ = Wire(Vec(renameWidth, Bool())) 438 val allowDispatch = Wire(Vec(renameWidth, Bool())) 439 val thisCanActualOut = Wire(Vec(renameWidth, Bool())) 440 val lsqCanAccept = Wire(Bool()) 441 for (i <- 0 until RenameWidth){ 442 // update valid logic 443 fromRenameUpdate(i).valid := fromRename(i).valid && allowDispatch(i) && !uopBlockByIQ(i) && thisCanActualOut(i) && 444 lsqCanAccept && !fromRename(i).bits.eliminatedMove && !fromRename(i).bits.hasException && !fromRenameUpdate(i).bits.singleStep 445 fromRename(i).ready := allowDispatch(i) && !uopBlockByIQ(i) && thisCanActualOut(i) && lsqCanAccept 446 // update src type if eliminate old vd 447 fromRenameUpdate(i).bits.srcType(numRegSrcVf - 1) := Mux(ignoreOldVdVec(i), SrcType.no, fromRename(i).bits.srcType(numRegSrcVf - 1)) 448 } 449 for (i <- 0 until RenameWidth){ 450 // check is drop amocas sta 451 fromRenameUpdate(i).bits.isDropAmocasSta := fromRename(i).bits.isAMOCAS && fromRename(i).bits.uopIdx(0) === 1.U 452 // update singleStep 453 fromRenameUpdate(i).bits.singleStep := io.singleStep && (fromRename(i).bits.robIdx =/= robidxCanCommitStepping) 454 } 455 var temp = 0 456 allIssueParams.zipWithIndex.map{ case(issue, iqidx) => { 457 for (i <- 0 until issue.numEnq){ 458 val oh = Wire(Vec(renameWidth, Bool())).suggestName(s"oh_IQSelUop_$temp") 459 oh := uopSelIQMatrix.map(_(iqidx)).map(_ === (i+1).U) 460 IQSelUop(temp) := PriorityMux(oh, fromRenameUpdate) 461 // there only assign valid not use PriorityMuxDefalut for better timing 462 IQSelUop(temp).valid := PriorityMuxDefault(oh.zip(fromRenameUpdate.map(_.valid)), false.B) 463 val allFuThisIQ = issue.exuBlockParams.map(_.fuConfigs).flatten.toSet.toSeq 464 val hasStaFu = !allFuThisIQ.filter(_.name == "sta").isEmpty 465 for (j <- 0 until numRegSrc){ 466 val maskForStd = hasStaFu && (j == 1) 467 val thisSrcHasInt = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) IntRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 468 val thisSrcHasFp = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) FpRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 469 val thisSrcHasVec = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) VecRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 470 val thisSrcHasV0 = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) V0RegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 471 val thisSrcHasVl = allFuThisIQ.map(x => {x.srcData.map(xx => {if (j < xx.size) VlRegSrcDataSet.contains(xx(j)) else false}).reduce(_ || _)}).reduce(_ || _) 472 val selSrcState = Seq(thisSrcHasInt || maskForStd, thisSrcHasFp || maskForStd, thisSrcHasVec, thisSrcHasV0, thisSrcHasVl) 473 IQSelUop(temp).bits.srcState(j) := PriorityMux(oh, allSrcState)(j).zip(selSrcState).filter(_._2 == true).map(_._1).foldLeft(false.B)(_ || _).asUInt 474 } 475 temp = temp + 1 476 if (backendParams.debugEn){ 477 dontTouch(oh) 478 } 479 } 480 }} 481 temp = 0 482 val uopBlockMatrix = Wire(Vec(renameWidth, Vec(issueQueueNum, Bool()))) 483 val uopBlockMatrixForAssign = allIssueParams.zipWithIndex.map { case (issue, iqidx) => { 484 val result = uopSelIQMatrix.map(_(iqidx)).map(x => Mux(io.toIssueQueues(temp).ready, x > issue.numEnq.U, x.orR)) 485 temp = temp + issue.numEnq 486 result 487 }}.transpose 488 uopBlockMatrix.zip(uopBlockMatrixForAssign).map(x => x._1 := VecInit(x._2)) 489 uopBlockByIQ := uopBlockMatrix.map(_.reduce(_ || _)) 490 io.toIssueQueues.zip(IQSelUop).map(x => { 491 x._1.valid := x._2.valid 492 x._1.bits := x._2.bits 493 }) 494 if (backendParams.debugEn){ 495 dontTouch(uopSelIQMatrix) 496 dontTouch(IQSelUop) 497 dontTouch(fromRenameUpdate) 498 dontTouch(uopBlockByIQ) 499 dontTouch(allowDispatch) 500 dontTouch(thisCanActualOut) 501 dontTouch(popFuTypeOH) 502 dontTouch(fuTypeOH) 503 dontTouch(fuTypeOHSingle) 504 dontTouch(minIQSelAll) 505 } 506 /////////////////////////////////////////////////////////// 507 508 val lsqEnqCtrl = Module(new LsqEnqCtrl) 509 510 // TODO: check lsqEnqCtrl redirect logic 511 // here is RegNext because dispatch2iq use s2_s4_redirect, newDispatch use s1_s3_redirect 512 lsqEnqCtrl.io.redirect := RegNext(io.redirect) 513 lsqEnqCtrl.io.lcommit := io.fromMem.lcommit 514 lsqEnqCtrl.io.scommit := io.fromMem.scommit 515 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.lqCancelCnt 516 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.sqCancelCnt 517 lsqEnqCtrl.io.enq.iqAccept := io.fromRename.map(x => !x.valid || x.fire) 518 io.toMem.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 519 520 private val enqLsqIO = lsqEnqCtrl.io.enq 521 private val lqFreeCount = lsqEnqCtrl.io.lqFreeCount 522 private val sqFreeCount = lsqEnqCtrl.io.sqFreeCount 523 524 private val numLoadDeq = LSQLdEnqWidth 525 private val numStoreAMODeq = LSQStEnqWidth 526 private val numVLoadDeq = LoadPipelineWidth 527 private val numDeq = enqLsqIO.req.size 528 lsqCanAccept := enqLsqIO.canAccept 529 530 private val isLoadVec = VecInit(fromRename.map(x => x.valid && FuType.isLoad(x.bits.fuType))) 531 private val isStoreVec = VecInit(fromRename.map(x => x.valid && FuType.isStore(x.bits.fuType))) 532 private val isAMOVec = fromRename.map(x => x.valid && FuType.isAMO(x.bits.fuType)) 533 private val isStoreAMOVec = fromRename.map(x => x.valid && (FuType.isStore(x.bits.fuType) || FuType.isAMO(x.bits.fuType))) 534 private val isVLoadVec = VecInit(fromRename.map(x => x.valid && FuType.isVLoad(x.bits.fuType))) 535 private val isVStoreVec = VecInit(fromRename.map(x => x.valid && FuType.isVStore(x.bits.fuType))) 536 537 private val loadCntVec = VecInit(isLoadVec.indices.map(x => PopCount(isLoadVec.slice(0, x + 1)))) 538 private val storeAMOCntVec = VecInit(isStoreAMOVec.indices.map(x => PopCount(isStoreAMOVec.slice(0, x + 1)))) 539 private val vloadCntVec = VecInit(isVLoadVec.indices.map(x => PopCount(isVLoadVec.slice(0, x + 1)))) 540 541 private val s0_enqLsq_resp = Wire(enqLsqIO.resp.cloneType) 542 for (i <- 0 until RenameWidth) { 543 // update lqIdx sqIdx 544 fromRenameUpdate(i).bits.lqIdx := s0_enqLsq_resp(i).lqIdx 545 fromRenameUpdate(i).bits.sqIdx := s0_enqLsq_resp(i).sqIdx 546 } 547 548 val loadBlockVec = VecInit(loadCntVec.map(_ > numLoadDeq.U)) 549 val storeAMOBlockVec = VecInit(storeAMOCntVec.map(_ > numStoreAMODeq.U)) 550 val vloadBlockVec = VecInit(vloadCntVec.map(_ > numVLoadDeq.U)) 551 val lsStructBlockVec = VecInit((loadBlockVec.zip(storeAMOBlockVec)).zip(vloadBlockVec).map(x => x._1._1 || x._1._2 || x._2)) 552 if (backendParams.debugEn) { 553 dontTouch(loadBlockVec) 554 dontTouch(storeAMOBlockVec) 555 dontTouch(lsStructBlockVec) 556 dontTouch(vloadBlockVec) 557 dontTouch(isLoadVec) 558 dontTouch(isVLoadVec) 559 dontTouch(loadCntVec) 560 } 561 562 private val uop = fromRename.map(_.bits) 563 private val fuType = uop.map(_.fuType) 564 private val fuOpType = uop.map(_.fuOpType) 565 private val vtype = uop.map(_.vpu.vtype) 566 private val sew = vtype.map(_.vsew) 567 private val lmul = vtype.map(_.vlmul) 568 private val eew = uop.map(_.vpu.veew) 569 private val mop = fuOpType.map(fuOpTypeItem => LSUOpType.getVecLSMop(fuOpTypeItem)) 570 private val nf = fuOpType.zip(uop.map(_.vpu.nf)).map { case (fuOpTypeItem, nfItem) => Mux(LSUOpType.isWhole(fuOpTypeItem), 0.U, nfItem) } 571 private val emul = fuOpType.zipWithIndex.map { case (fuOpTypeItem, index) => 572 Mux( 573 LSUOpType.isWhole(fuOpTypeItem), 574 GenUSWholeEmul(nf(index)), 575 Mux( 576 LSUOpType.isMasked(fuOpTypeItem), 577 0.U(mulBits.W), 578 EewLog2(eew(index)) - sew(index) + lmul(index) 579 ) 580 ) 581 } 582 583 private val isVlsType = fuType.map(fuTypeItem => FuType.isVls(fuTypeItem)).zip(fromRename.map(_.valid)).map(x => x._1 && x._2) 584 private val isLSType = fuType.map(fuTypeItem => FuType.isLoad(fuTypeItem) || FuType.isStore(fuTypeItem)).zip(fromRename.map(_.valid)).map(x => x._1 && x._2) 585 private val isSegment = fuType.map(fuTypeItem => FuType.isVsegls(fuTypeItem)).zip(fromRename.map(_.valid)).map(x => x._1 && x._2) 586 // TODO 587 private val isUnitStride = fuOpType.map(fuOpTypeItem => LSUOpType.isAllUS(fuOpTypeItem)) 588 private val isVecUnitType = isVlsType.zip(isUnitStride).map { case (isVlsTypeItme, isUnitStrideItem) => 589 isVlsTypeItme && isUnitStrideItem 590 } 591 private val isfofFixVlUop = uop.map { x => x.vpu.isVleff && x.lastUop } 592 private val instType = isSegment.zip(mop).map { case (isSegementItem, mopItem) => Cat(isSegementItem, mopItem) } 593 // There is no way to calculate the 'flow' for 'unit-stride' exactly: 594 // Whether 'unit-stride' needs to be split can only be known after obtaining the address. 595 // For scalar instructions, this is not handled here, and different assignments are done later according to the situation. 596 private val numLsElem = VecInit(uop.map(_.numLsElem)) 597 598 // The maximum 'numLsElem' number that can be emitted per port is: 599 // 16 2 2 2 2 2. 600 // The 'allowDispatch' calculations are done conservatively for timing purposes: 601 // The Flow of scalar instructions is considered 1, 602 // The flow of vector 'unit-stride' instructions is considered 2, and the flow of other vector instructions is considered 16. 603 private val conserveFlows = VecInit(isVlsType.zip(isLSType).zipWithIndex.map { case ((isVlsTyepItem, isLSTypeItem), index) => 604 Mux( 605 isVlsTyepItem, 606 Mux(isUnitStride(index), VecMemUnitStrideMaxFlowNum.U, 16.U), 607 Mux(isLSTypeItem, 1.U, 0.U) 608 ) 609 }) 610 611 private val conserveFlowsIs16 = VecInit(isVlsType.zipWithIndex.map { case (isVlsTyepItem, index) => 612 isVlsTyepItem && !isUnitStride(index) 613 }) 614 private val conserveFlowsIs2 = VecInit(isVlsType.zipWithIndex.map { case (isVlsTyepItem, index) => 615 isVlsTyepItem && isUnitStride(index) 616 }) 617 private val conserveFlowsIs1 = VecInit(isLSType.zipWithIndex.map { case (isLSTyepItem, index) => 618 isLSTyepItem 619 }) 620 private val flowTotalWidth = (VecMemLSQEnqIteratorNumberSeq.max * RenameWidth).U.getWidth 621 private val conserveFlowTotalDispatch = Wire(Vec(RenameWidth, UInt(flowTotalWidth.W))) 622 private val lowCountMaxWidth = (2 * RenameWidth).U.getWidth 623 conserveFlowTotalDispatch.zipWithIndex.map{ case (flowTotal, idx) => 624 val highCount = PopCount(conserveFlowsIs16.take(idx + 1)) 625 val conserveFlowsIs2Or1 = VecInit(conserveFlowsIs2.zip(conserveFlowsIs1).map(x => Cat(x._1, x._2))) 626 val lowCount = conserveFlowsIs2Or1.take(idx + 1).reduce(_ +& _).asTypeOf(0.U(lowCountMaxWidth.W)) 627 flowTotal := (if (RenameWidth == 6) Cat(highCount, lowCount) else ((highCount << 4).asUInt + lowCount)) 628 } 629 // renameIn 630 private val isVlsTypeRename = io.renameIn.map(x => x.valid && FuType.isVls(x.bits.fuType)) 631 private val isLSTypeRename = io.renameIn.map(x => x.valid && (FuType.isLoad(x.bits.fuType)) || FuType.isStore(x.bits.fuType)) 632 private val isUnitStrideRename = io.renameIn.map(x => LSUOpType.isAllUS(x.bits.fuOpType)) 633 private val conserveFlowsIs16Rename = VecInit(isVlsTypeRename.zipWithIndex.map { case (isVlsTyepItem, index) => 634 isVlsTyepItem && !isUnitStrideRename(index) 635 }) 636 private val conserveFlowsIs2Rename = VecInit(isVlsTypeRename.zipWithIndex.map { case (isVlsTyepItem, index) => 637 isVlsTyepItem && isUnitStrideRename(index) 638 }) 639 private val conserveFlowsIs1Rename = VecInit(isLSTypeRename.zipWithIndex.map { case (isLSTyepItem, index) => 640 isLSTyepItem 641 }) 642 private val conserveFlowTotalRename = Wire(Vec(RenameWidth, UInt(flowTotalWidth.W))) 643 conserveFlowTotalRename.zipWithIndex.map { case (flowTotal, idx) => 644 val highCount = PopCount(conserveFlowsIs16Rename.take(idx + 1)) 645 val conserveFlowsIs2Or1 = VecInit(conserveFlowsIs2Rename.zip(conserveFlowsIs1Rename).map(x => Cat(x._1, x._2))) 646 val lowCount = conserveFlowsIs2Or1.take(idx + 1).reduce(_ +& _).asTypeOf(0.U(lowCountMaxWidth.W)) 647 flowTotal := (if (RenameWidth == 6) Cat(highCount, lowCount) else ((highCount << 4).asUInt + lowCount)) 648 } 649 650 651 private val conserveFlowTotal = Reg(Vec(RenameWidth, UInt(flowTotalWidth.W))) 652 when(io.toRenameAllFire){ 653 conserveFlowTotal := conserveFlowTotalRename 654 }.otherwise( 655 conserveFlowTotal := conserveFlowTotalDispatch 656 ) 657 // A conservative allocation strategy is adopted here. 658 // Vector 'unit-stride' instructions and scalar instructions can be issued from all six ports, 659 // while other vector instructions can only be issued from the first port 660 // if is segment instruction, need disptch it to Vldst_RS0, so, except port 0, stall other. 661 // The allocation needs to meet a few conditions: 662 // 1) The lsq has enough entris. 663 // 2) The number of flows accumulated does not exceed VecMemDispatchMaxNumber. 664 // 3) Vector instructions other than 'unit-stride' can only be issued on the first port. 665 666 667 for (index <- allowDispatch.indices) { 668 val flowTotal = conserveFlowTotal(index) 669 val allowDispatchPrevious = if (index == 0) true.B else allowDispatch(index - 1) 670 when(isStoreVec(index) || isVStoreVec(index)) { 671 allowDispatch(index) := (sqFreeCount > flowTotal) && allowDispatchPrevious 672 }.elsewhen(isLoadVec(index) || isVLoadVec(index)) { 673 allowDispatch(index) := (lqFreeCount > flowTotal) && allowDispatchPrevious 674 }.elsewhen(isAMOVec(index)) { 675 allowDispatch(index) := allowDispatchPrevious 676 }.otherwise { 677 allowDispatch(index) := allowDispatchPrevious 678 } 679 } 680 681 682 // enqLsq io 683 require(enqLsqIO.req.size == enqLsqIO.resp.size) 684 for (i <- enqLsqIO.req.indices) { 685 when(!io.fromRename(i).fire) { 686 enqLsqIO.needAlloc(i) := 0.U 687 }.elsewhen(isStoreVec(i) || isVStoreVec(i)) { 688 enqLsqIO.needAlloc(i) := 2.U // store | vstore 689 }.elsewhen(isLoadVec(i) || isVLoadVec(i)){ 690 enqLsqIO.needAlloc(i) := 1.U // load | vload 691 }.otherwise { 692 enqLsqIO.needAlloc(i) := 0.U 693 } 694 enqLsqIO.req(i).valid := io.fromRename(i).fire && !isAMOVec(i) && !isSegment(i) && !isfofFixVlUop(i) 695 enqLsqIO.req(i).bits := io.fromRename(i).bits 696 697 // This is to make it easier to calculate in LSQ. 698 // Both scalar instructions and vector instructions with FLOW equal to 1 have a NUM value of 1.” 699 // But, the 'numLsElem' that is not a vector is set to 0 when passed to IQ 700 enqLsqIO.req(i).bits.numLsElem := Mux(isVlsType(i), numLsElem(i), 1.U) 701 s0_enqLsq_resp(i) := enqLsqIO.resp(i) 702 } 703 704 val isFp = VecInit(fromRename.map(req => FuType.isFArith(req.bits.fuType))) 705 val isVec = VecInit(fromRename.map(req => FuType.isVArith (req.bits.fuType) || 706 FuType.isVsetRvfWvf(req.bits.fuType))) 707 val isMem = VecInit(fromRename.map(req => FuType.isMem(req.bits.fuType) || 708 FuType.isVls (req.bits.fuType))) 709 val isLs = VecInit(fromRename.map(req => FuType.isLoadStore(req.bits.fuType))) 710 val isVls = VecInit(fromRename.map(req => FuType.isVls (req.bits.fuType))) 711 val isStore = VecInit(fromRename.map(req => FuType.isStore(req.bits.fuType))) 712 val isVStore = VecInit(fromRename.map(req => FuType.isVStore(req.bits.fuType))) 713 val isAMO = VecInit(fromRename.map(req => FuType.isAMO(req.bits.fuType))) 714 val isBlockBackward = VecInit(fromRename.map(x => x.valid && x.bits.blockBackward)) 715 val isWaitForward = VecInit(fromRename.map(x => x.valid && x.bits.waitForward)) 716 717 val updatedUop = Wire(Vec(RenameWidth, new DynInst)) 718 val checkpoint_id = RegInit(0.U(64.W)) 719 checkpoint_id := checkpoint_id + PopCount((0 until RenameWidth).map(i => 720 fromRename(i).fire 721 )) 722 723 724 for (i <- 0 until RenameWidth) { 725 726 updatedUop(i) := fromRename(i).bits 727 updatedUop(i).debugInfo.eliminatedMove := fromRename(i).bits.eliminatedMove 728 // For the LUI instruction: psrc(0) is from register file and should always be zero. 729 when (fromRename(i).bits.isLUI) { 730 updatedUop(i).psrc(0) := 0.U 731 } 732 //TODO: vec ls mdp 733 io.lfst.req(i).valid := fromRename(i).fire && updatedUop(i).storeSetHit 734 io.lfst.req(i).bits.isstore := isStore(i) 735 io.lfst.req(i).bits.ssid := updatedUop(i).ssid 736 io.lfst.req(i).bits.robIdx := updatedUop(i).robIdx // speculatively assigned in rename 737 738 // override load delay ctrl signal with store set result 739 if(StoreSetEnable) { 740 updatedUop(i).loadWaitBit := io.lfst.resp(i).bits.shouldWait 741 updatedUop(i).waitForRobIdx := io.lfst.resp(i).bits.robIdx 742 } else { 743 updatedUop(i).loadWaitBit := isLs(i) && !isStore(i) && fromRename(i).bits.loadWaitBit 744 } 745 // // update singleStep, singleStep exception only enable in next machine instruction. 746 updatedUop(i).singleStep := io.singleStep && (fromRename(i).bits.robIdx =/= robidxCanCommitStepping) 747 when (fromRename(i).fire) { 748 XSDebug(TriggerAction.isDmode(updatedUop(i).trigger) || updatedUop(i).exceptionVec(breakPoint), s"Debug Mode: inst ${i} has frontend trigger exception\n") 749 XSDebug(updatedUop(i).singleStep, s"Debug Mode: inst ${i} has single step exception\n") 750 } 751 if (env.EnableDifftest) { 752 // debug runahead hint 753 val debug_runahead_checkpoint_id = Wire(checkpoint_id.cloneType) 754 if(i == 0){ 755 debug_runahead_checkpoint_id := checkpoint_id 756 } else { 757 debug_runahead_checkpoint_id := checkpoint_id + PopCount((0 until i).map(i => 758 fromRename(i).fire 759 )) 760 } 761 } 762 } 763 764 // store set perf count 765 XSPerfAccumulate("waittable_load_wait", PopCount((0 until RenameWidth).map(i => 766 fromRename(i).fire && fromRename(i).bits.loadWaitBit && !isStore(i) && isLs(i) 767 ))) 768 XSPerfAccumulate("storeset_load_wait", PopCount((0 until RenameWidth).map(i => 769 fromRename(i).fire && updatedUop(i).loadWaitBit && !isStore(i) && isLs(i) 770 ))) 771 XSPerfAccumulate("storeset_load_strict_wait", PopCount((0 until RenameWidth).map(i => 772 fromRename(i).fire && updatedUop(i).loadWaitBit && updatedUop(i).loadWaitStrict && !isStore(i) && isLs(i) 773 ))) 774 XSPerfAccumulate("storeset_store_wait", PopCount((0 until RenameWidth).map(i => 775 fromRename(i).fire && updatedUop(i).loadWaitBit && isStore(i) 776 ))) 777 778 val allResourceReady = io.enqRob.canAccept 779 780 // Instructions should enter dispatch queues in order. 781 // blockedByWaitForward: this instruction is blocked by itself (based on waitForward) 782 // nextCanOut: next instructions can out (based on blockBackward) 783 // notBlockedByPrevious: previous instructions can enqueue 784 val hasException = VecInit(fromRename.zip(updatedUop).map { 785 case (fromRename: DecoupledIO[DynInst], uop: DynInst) => 786 fromRename.bits.hasException || uop.singleStep 787 }) 788 789 private val blockedByWaitForward = Wire(Vec(RenameWidth, Bool())) 790 blockedByWaitForward(0) := !io.enqRob.isEmpty && isWaitForward(0) 791 for (i <- 1 until RenameWidth) { 792 blockedByWaitForward(i) := blockedByWaitForward(i - 1) || (!io.enqRob.isEmpty || Cat(fromRename.take(i).map(_.valid)).orR) && isWaitForward(i) 793 } 794 if(backendParams.debugEn){ 795 dontTouch(blockedByWaitForward) 796 dontTouch(conserveFlows) 797 } 798 799 // Only the uop with block backward flag will block the next uop 800 val nextCanOut = VecInit((0 until RenameWidth).map(i => 801 !isBlockBackward(i) 802 )) 803 val notBlockedByPrevious = VecInit((0 until RenameWidth).map(i => 804 if (i == 0) true.B 805 else Cat((0 until i).map(j => nextCanOut(j))).andR 806 )) 807 808 // for noSpecExec: (robEmpty || !this.noSpecExec) && !previous.noSpecExec 809 // For blockBackward: 810 // this instruction can actually dequeue: 3 conditions 811 // (1) resources are ready 812 // (2) previous instructions are ready 813 thisCanActualOut := VecInit((0 until RenameWidth).map(i => !blockedByWaitForward(i) && notBlockedByPrevious(i) && io.enqRob.canAccept)) 814 val thisActualOut = (0 until RenameWidth).map(i => io.enqRob.req(i).valid && io.enqRob.canAccept) 815 816 // input for ROB, LSQ 817 for (i <- 0 until RenameWidth) { 818 // needAlloc no use, need deleted 819 io.enqRob.needAlloc(i) := fromRename(i).valid 820 io.enqRob.req(i).valid := fromRename(i).fire 821 io.enqRob.req(i).bits := updatedUop(i) 822 io.enqRob.req(i).bits.hasException := updatedUop(i).hasException || updatedUop(i).singleStep 823 io.enqRob.req(i).bits.numWB := Mux(updatedUop(i).singleStep, 0.U, updatedUop(i).numWB) 824 } 825 826 val hasValidInstr = VecInit(fromRename.map(_.valid)).asUInt.orR 827 val hasSpecialInstr = Cat((0 until RenameWidth).map(i => isBlockBackward(i))).orR 828 829 private val canAccept = !hasValidInstr || !hasSpecialInstr && io.enqRob.canAccept 830 831 val isWaitForwardOrBlockBackward = isWaitForward.asUInt.orR || isBlockBackward.asUInt.orR 832 val renameFireCnt = PopCount(fromRename.map(_.fire)) 833 834 val stall_rob = hasValidInstr && !io.enqRob.canAccept 835 val stall_int_dq = hasValidInstr && io.enqRob.canAccept 836 val stall_int_dq0 = hasValidInstr && io.enqRob.canAccept 837 val stall_int_dq1 = hasValidInstr && io.enqRob.canAccept 838 val stall_fp_dq = hasValidInstr && io.enqRob.canAccept 839 val stall_ls_dq = hasValidInstr && io.enqRob.canAccept 840 841 XSPerfAccumulate("in_valid_count", PopCount(fromRename.map(_.valid))) 842 XSPerfAccumulate("in_fire_count", PopCount(fromRename.map(_.fire))) 843 XSPerfAccumulate("in_valid_not_ready_count", PopCount(fromRename.map(x => x.valid && !x.ready))) 844 XSPerfAccumulate("wait_cycle", !fromRename.head.valid && allResourceReady) 845 846 XSPerfAccumulate("stall_cycle_rob", stall_rob) 847 XSPerfAccumulate("stall_cycle_int_dq0", stall_int_dq0) 848 XSPerfAccumulate("stall_cycle_int_dq1", stall_int_dq1) 849 XSPerfAccumulate("stall_cycle_fp_dq", stall_fp_dq) 850 XSPerfAccumulate("stall_cycle_ls_dq", stall_ls_dq) 851 852 val notIssue = !io.debugTopDown.fromRob.robHeadLsIssue 853 val tlbReplay = io.debugTopDown.fromCore.fromMem.robHeadTlbReplay 854 val tlbMiss = io.debugTopDown.fromCore.fromMem.robHeadTlbMiss 855 val vioReplay = io.debugTopDown.fromCore.fromMem.robHeadLoadVio 856 val mshrReplay = io.debugTopDown.fromCore.fromMem.robHeadLoadMSHR 857 val l1Miss = io.debugTopDown.fromCore.fromMem.robHeadMissInDCache 858 val l2Miss = io.debugTopDown.fromCore.l2MissMatch 859 val l3Miss = io.debugTopDown.fromCore.l3MissMatch 860 861 val ldReason = Mux(l3Miss, TopDownCounters.LoadMemStall.id.U, 862 Mux(l2Miss, TopDownCounters.LoadL3Stall.id.U, 863 Mux(l1Miss, TopDownCounters.LoadL2Stall.id.U, 864 Mux(notIssue, TopDownCounters.MemNotReadyStall.id.U, 865 Mux(tlbMiss, TopDownCounters.LoadTLBStall.id.U, 866 Mux(tlbReplay, TopDownCounters.LoadTLBStall.id.U, 867 Mux(mshrReplay, TopDownCounters.LoadMSHRReplayStall.id.U, 868 Mux(vioReplay, TopDownCounters.LoadVioReplayStall.id.U, 869 TopDownCounters.LoadL1Stall.id.U)))))))) 870 871 val decodeReason = RegNextN(io.stallReason.reason, 2) 872 val renameReason = RegNext(io.stallReason.reason) 873 874 val stallReason = Wire(chiselTypeOf(io.stallReason.reason)) 875 val firedVec = fromRename.map(_.fire) 876 io.stallReason.backReason.valid := !canAccept 877 io.stallReason.backReason.bits := TopDownCounters.OtherCoreStall.id.U 878 stallReason.zip(io.stallReason.reason).zip(firedVec).zipWithIndex.map { case (((update, in), fire), idx) => 879 val headIsInt = FuType.isInt(io.robHead.getDebugFuType) && io.robHeadNotReady 880 val headIsFp = FuType.isFArith(io.robHead.getDebugFuType) && io.robHeadNotReady 881 val headIsDiv = FuType.isDivSqrt(io.robHead.getDebugFuType) && io.robHeadNotReady 882 val headIsLd = io.robHead.getDebugFuType === FuType.ldu.U && io.robHeadNotReady || !io.lqCanAccept 883 val headIsSt = io.robHead.getDebugFuType === FuType.stu.U && io.robHeadNotReady || !io.sqCanAccept 884 val headIsAmo = io.robHead.getDebugFuType === FuType.mou.U && io.robHeadNotReady 885 val headIsLs = headIsLd || headIsSt 886 val robLsFull = io.robFull || !io.lqCanAccept || !io.sqCanAccept 887 888 import TopDownCounters._ 889 update := MuxCase(OtherCoreStall.id.U, Seq( 890 // fire 891 (fire ) -> NoStall.id.U , 892 // dispatch not stall / core stall from decode or rename 893 (in =/= OtherCoreStall.id.U && in =/= NoStall.id.U ) -> in , 894 // rob stall 895 (headIsAmo ) -> AtomicStall.id.U , 896 (headIsSt ) -> StoreStall.id.U , 897 (headIsLd ) -> ldReason , 898 (headIsDiv ) -> DivStall.id.U , 899 (headIsInt ) -> IntNotReadyStall.id.U , 900 (headIsFp ) -> FPNotReadyStall.id.U , 901 (renameReason(idx) =/= NoStall.id.U ) -> renameReason(idx) , 902 (decodeReason(idx) =/= NoStall.id.U ) -> decodeReason(idx) , 903 )) 904 } 905 906 TopDownCounters.values.foreach(ctr => XSPerfAccumulate(ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U)))) 907 908 val robTrueCommit = io.debugTopDown.fromRob.robTrueCommit 909 TopDownCounters.values.foreach(ctr => XSPerfRolling("td_"+ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U)), 910 robTrueCommit, 1000, clock, reset)) 911 912 XSPerfHistogram("slots_fire", PopCount(thisActualOut), true.B, 0, RenameWidth+1, 1) 913 // Explaination: when out(0) not fire, PopCount(valid) is not meaningfull 914 XSPerfHistogram("slots_valid_pure", PopCount(io.enqRob.req.map(_.valid)), thisActualOut(0), 0, RenameWidth+1, 1) 915 XSPerfHistogram("slots_valid_rough", PopCount(io.enqRob.req.map(_.valid)), true.B, 0, RenameWidth+1, 1) 916 917 val perfEvents = Seq( 918 ("dispatch_in", PopCount(fromRename.map(_.valid && fromRename(0).ready)) ), 919 ("dispatch_empty", !hasValidInstr ), 920 ("dispatch_utili", PopCount(fromRename.map(_.valid)) ), 921 ("dispatch_waitinstr", PopCount(fromRename.map(!_.valid && canAccept)) ), 922 ("dispatch_stall_cycle_lsq", false.B ), 923 ("dispatch_stall_cycle_rob", stall_rob ), 924 ("dispatch_stall_cycle_int_dq", stall_int_dq ), 925 ("dispatch_stall_cycle_fp_dq", stall_fp_dq ), 926 ("dispatch_stall_cycle_ls_dq", stall_ls_dq ) 927 ) 928 generatePerfEvent() 929} 930