1package xiangshan.frontend 2 3import chisel3._ 4import chiseltest._ 5import org.scalatest.flatspec.AnyFlatSpec 6import org.scalatest.matchers.must.Matchers 7import top.DefaultConfig 8import utility.{LogUtilsOptions, LogUtilsOptionsKey} 9import xiangshan.{DebugOptionsKey, XSCoreParameters, XSCoreParamsKey} 10 11 12class FrontendTriggerTest extends AnyFlatSpec with ChiselScalatestTester with Matchers { 13 val defaultConfig = (new DefaultConfig).alterPartial { 14 case XSCoreParamsKey => XSCoreParameters() 15 }.alter((site, here, up) => { 16 case LogUtilsOptionsKey => LogUtilsOptions( 17 here(DebugOptionsKey).EnableDebug, 18 here(DebugOptionsKey).EnablePerfDebug, 19 here(DebugOptionsKey).FPGAPlatform 20 ) 21 }) 22 23 println("test start") 24 25 behavior of "FrontendTrigger" 26 it should "run" in { 27 test(new FrontendTrigger()(defaultConfig)).withAnnotations(Seq(VerilatorBackendAnnotation)) { 28 m: FrontendTrigger => 29 m.io.frontendTrigger.debugMode.poke(false.B) 30 m.io.frontendTrigger.tEnableVec.map(_.poke(false.B)) 31 m.io.frontendTrigger.tEnableVec(1).poke(true.B) 32 m.io.frontendTrigger.triggerCanRaiseBpExp.poke(true.B) 33 m.io.frontendTrigger.tUpdate.valid.poke(true.B) 34 m.io.frontendTrigger.tUpdate.bits.addr.poke(1.U) 35 m.io.frontendTrigger.tUpdate.bits.tdata.matchType.poke(3.U) 36 m.io.frontendTrigger.tUpdate.bits.tdata.tdata2.poke("h1234_567f".U) 37 m.io.pc.zipWithIndex.map { case (pc, i) => 38 pc.poke((0x1234_5676 + 2 * i).U) 39 } 40 for (_ <- 0 until 4) { m.clock.step() } 41 m.io.triggered.zipWithIndex.map { case (action, i) => 42 println(s"out.triggerAction${i}：" + action.peek().litValue.toString(16) + "\n") 43 } 44 } 45 println("test done") 46 } 47} 48