freelist: optimize timing of read and writing (#1593)

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representatio

freelist: optimize timing of read and writing (#1593)

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representation of headPtr and further uses it to
read the free registers from the list, which should be better than the
previous implementation where headPtr is used to indexed into the queue.

The update of tailPtr and the freelist is delayed by one cycle to
optimize the timing. Because freelist allocates new registers in the
next cycle iff there are more than RenameWidth free registers in this
cycle. The freed registers in this cycle will never be used in the next
cycle. Thus, we can delay the updating of queue data to the next cycle.
We also move the update of tailPtr to the next cycle, since PopCount
takes a long timing and we move the last adder to the next cycle. Now
the adder works parallely with PopCount. That is, the updating of
tailPtr is pipelined.

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core,perf: optimize timing for some registers (#1589)

This commit adds some registers for performance counters to optimize
the timing. Pipelines are added.

decode: parallel fusion decoder and rat read (#1588)

rename: check valid condition for lui (#1368)

Debug Mode: support difftest with spike (#1363)

* Debug Mode: support basic difftest with spike

* Debug Mode: fix some bugs

Bugs fixed are:
1. All interrupts and exceptions cause debug mode t

Debug Mode: support difftest with spike (#1363)

* Debug Mode: support basic difftest with spike

* Debug Mode: fix some bugs

Bugs fixed are:
1. All interrupts and exceptions cause debug mode to enter park loop
2. Debug interrupt ignored due to flushPipe

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rename: add fused lui and load (#1356)

This commit adds fused load support by bypassing LUI results to load.

For better timing, detection is done at the rename stage. Imm is stored
in psrc(1), p

rename: add fused lui and load (#1356)

This commit adds fused load support by bypassing LUI results to load.

For better timing, detection is done at the rename stage. Imm is stored
in psrc(1), psrc(0) and imm.

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difftest: move sc_valid to AtomicsUnit (#1350)

core: refactor hardware performance counters (#1335)

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

refCounter: optimize timing for freeRegs (#1255)

This commit changes how isFreed is calculated. Instead of using
refCounter in the next, we compute it at this cycle and RegNext it.

mem,mdp: use robIdx instead of sqIdx (#1242)

* mdp: implement SSIT with sram

* mdp: use robIdx instead of sqIdx

Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not
get corr

mem,mdp: use robIdx instead of sqIdx (#1242)

* mdp: implement SSIT with sram

* mdp: use robIdx instead of sqIdx

Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not
get correct sqIdx in dispatch. Unlike robIdx, it is hard to maintain a
"speculatively assigned" sqIdx, as it is hard to track store insts in
dispatch queue. Yet we can still use "speculatively assigned" robIdx
for memory dependency predictor.

For now, memory dependency predictor uses "speculatively assigned"
robIdx to track inflight store.

However, sqIdx is still used to track those store which's addr is valid
but data it not valid. When load insts try to get forward data from
those store, load insts will get that store's sqIdx and wait in RS.
They will not waken until store data with that sqIdx is issued.

* mdp: add track robIdx recover logic

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difftest: add basic difftest features for releases (#1219)

* difftest: add basic difftest features for releases

This commit adds basic difftest features for every release, no matter
it's for sim

difftest: add basic difftest features for releases (#1219)

* difftest: add basic difftest features for releases

This commit adds basic difftest features for every release, no matter
it's for simulation or physical design. The macro SYNTHESIS is used to
skip these logics when synthesizing the design. This commit aims at
allowing designs for physical design to be verified.

* bump ready-to-run

* difftest: add int and fp writeback data

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lsq: enqueue at dispatch2 stage (#1167)

This commit changes when instructions enter load/store queue.
Now, at dispatch2, load/store instructions enter load/store queue.

add performance counters at core and hauncun (#1156)

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

rob: optimize bits width in storage (#1155)

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* is

rob: optimize bits width in storage (#1155)

This PR optimizes out isFused and crossPageIPFFix usages in Rob's DispatchData. They will not be stored in ROB. Now DispatchData has only 38 bits.

* isFused is merged with commitType (2 bits reduced)
* crossPageIPFFix is used only in ExceptionGen (1 bit reduced)
* rename: reduce ldest usages
* decode: set isMove to false if ldest is zero

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refCounter: delay de-allocation for one more cycle (#1144)

This commit changes how de-allocation is done in RefCounter. One cycle
after we update the reference counters, the free registers are rele

refCounter: delay de-allocation for one more cycle (#1144)

This commit changes how de-allocation is done in RefCounter. One cycle
after we update the reference counters, the free registers are released
to the freelist.

Previous version creates a critical path, starting from deallocate ports
and ending at freelist registers. This commit adds one more cycle in the
allocation --> updating reference counters --> freeing physical
registers --> allocation loop.

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rename: don't update refCounter 0 (#1126)

This commit removes the update logic for ref counter 0.

For simplicity, we don't count the number of references for physical
register 0. It should never

rename: don't update refCounter 0 (#1126)

This commit removes the update logic for ref counter 0.

For simplicity, we don't count the number of references for physical
register 0. It should never be released to freelist.

Previously we track register 0's references. It works fine but it makes
the performance counters confusing because it may increase to a large
number. It never causes real issues.

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backend: remove lsrc usages after rename (#1124)

This commit removes lsrc usages in the fence unit and lsrc is no longer
needed after an instruction is renamed. It helps timing and area.

lsrc is

backend: remove lsrc usages after rename (#1124)

This commit removes lsrc usages in the fence unit and lsrc is no longer
needed after an instruction is renamed. It helps timing and area.

lsrc is placed in imm at rename stage (the last stage we need lsrc).
They are extracted in the fence unit. Imm needs to go through the
pipelines because Jump needs it (and we re-use it for lsrc).

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rename: support full-featured move elimination (#1123)

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 regi

rename: support full-featured move elimination (#1123)

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 registers have counters of ones. Every time the physical register
is allocated or deallocated, the counter is increased or decreased by
one. When the counter becomes zero from a non-zero value, the register
is freed and released to freelist.

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core: use redirect ports for flush (#1121)

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

bump chisel and code clean up (#1104)

* bump chisel to 3.5.0-RC1

We don't want to use SNAPSHOT version any more because we don't know
what will happen when we wake up in the morning.

* misc:

bump chisel and code clean up (#1104)

* bump chisel to 3.5.0-RC1

We don't want to use SNAPSHOT version any more because we don't know
what will happen when we wake up in the morning.

* misc: remove TMA_* to avoid conflicts

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renameTable: optimize read and write timing (#1101)

This commit optimizes RenameTable's timing.

Read addresses come from instruction buffer directly and has best
timing. So we let data read at d

renameTable: optimize read and write timing (#1101)

This commit optimizes RenameTable's timing.

Read addresses come from instruction buffer directly and has best
timing. So we let data read at decode stage and bypass write data
from this clock cycle to the read data at next cycle.

For write, we latch the write request and process it at the next cycle.

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misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

Merge branch 'master' into me-timing

backend, freelist: shrink verilog size by using scala variable
instead of chisel var in MEFreeList.scala

backend, freelist: simplify walk logic