1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import huancun.{CacheParameters, HCCacheParameters} 27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC} 28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 FetchWidth: Int = 8, 48 EnableBPU: Boolean = true, 49 EnableBPD: Boolean = true, 50 EnableRAS: Boolean = true, 51 EnableLB: Boolean = false, 52 EnableLoop: Boolean = true, 53 EnableSC: Boolean = true, 54 EnbaleTlbDebug: Boolean = false, 55 EnableJal: Boolean = false, 56 EnableUBTB: Boolean = true, 57 HistoryLength: Int = 64, 58 PathHistoryLength: Int = 16, 59 BtbSize: Int = 2048, 60 JbtacSize: Int = 1024, 61 JbtacBanks: Int = 8, 62 RasSize: Int = 32, 63 CacheLineSize: Int = 512, 64 UBtbWays: Int = 16, 65 BtbWays: Int = 2, 66 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 67 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 68 // val loop = Module(new LoopPredictor) 69 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 70 // else Module(new Tage) } 71 // else { Module(new FakeTage) }) 72 val ftb = Module(new FTB()(p)) 73 val ubtb = Module(new MicroBTB()(p)) 74 val bim = Module(new BIM()(p)) 75 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 76 val ras = Module(new RAS()(p)) 77 val ittage = Module(new ITTage()(p)) 78 // val tage = Module(new Tage()(p)) 79 // val fake = Module(new FakePredictor()(p)) 80 81 // val preds = Seq(loop, tage, btb, ubtb, bim) 82 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 83 preds.map(_.io := DontCare) 84 85 // ubtb.io.resp_in(0) := resp_in 86 // bim.io.resp_in(0) := ubtb.io.resp 87 // btb.io.resp_in(0) := bim.io.resp 88 // tage.io.resp_in(0) := btb.io.resp 89 // loop.io.resp_in(0) := tage.io.resp 90 bim.io.in.bits.resp_in(0) := resp_in 91 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 92 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 93 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 94 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 95 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 96 97 (preds, ras.io.out.resp) 98 }), 99 100 101 EnableL1plusPrefetcher: Boolean = true, 102 IBufSize: Int = 48, 103 DecodeWidth: Int = 6, 104 RenameWidth: Int = 6, 105 CommitWidth: Int = 6, 106 FtqSize: Int = 64, 107 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 108 IssQueSize: Int = 16, 109 NRPhyRegs: Int = 160, 110 NRIntReadPorts: Int = 14, 111 NRIntWritePorts: Int = 8, 112 NRFpReadPorts: Int = 14, 113 NRFpWritePorts: Int = 8, 114 LoadQueueSize: Int = 64, 115 StoreQueueSize: Int = 48, 116 RobSize: Int = 192, 117 EnableIntMoveElim: Boolean = true, 118 IntRefCounterWidth: Int = 2, 119 dpParams: DispatchParameters = DispatchParameters( 120 IntDqSize = 16, 121 FpDqSize = 16, 122 LsDqSize = 16, 123 IntDqDeqWidth = 4, 124 FpDqDeqWidth = 4, 125 LsDqDeqWidth = 4 126 ), 127 exuParameters: ExuParameters = ExuParameters( 128 JmpCnt = 1, 129 AluCnt = 4, 130 MulCnt = 0, 131 MduCnt = 2, 132 FmacCnt = 4, 133 FmiscCnt = 2, 134 FmiscDivSqrtCnt = 0, 135 LduCnt = 2, 136 StuCnt = 2 137 ), 138 LoadPipelineWidth: Int = 2, 139 StorePipelineWidth: Int = 2, 140 StoreBufferSize: Int = 16, 141 StoreBufferThreshold: Int = 7, 142 EnableFastForward: Boolean = true, 143 RefillSize: Int = 512, 144 itlbParameters: TLBParameters = TLBParameters( 145 name = "itlb", 146 fetchi = true, 147 useDmode = false, 148 sameCycle = true, 149 normalNWays = 32, 150 normalReplacer = Some("plru"), 151 superNWays = 4, 152 superReplacer = Some("plru"), 153 shouldBlock = true 154 ), 155 ldtlbParameters: TLBParameters = TLBParameters( 156 name = "ldtlb", 157 normalNSets = 128, 158 normalNWays = 1, 159 normalAssociative = "sa", 160 normalReplacer = Some("setplru"), 161 superNWays = 8, 162 normalAsVictim = true, 163 outReplace = true 164 ), 165 sttlbParameters: TLBParameters = TLBParameters( 166 name = "sttlb", 167 normalNSets = 128, 168 normalNWays = 1, 169 normalAssociative = "sa", 170 normalReplacer = Some("setplru"), 171 superNWays = 8, 172 normalAsVictim = true, 173 outReplace = true 174 ), 175 refillBothTlb: Boolean = false, 176 btlbParameters: TLBParameters = TLBParameters( 177 name = "btlb", 178 normalNSets = 1, 179 normalNWays = 64, 180 superNWays = 4, 181 ), 182 useBTlb: Boolean = false, 183 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 184 NumPerfCounters: Int = 16, 185 icacheParameters: ICacheParameters = ICacheParameters( 186 tagECC = Some("parity"), 187 dataECC = Some("parity"), 188 replacer = Some("setplru"), 189 nMissEntries = 2 190 ), 191 dcacheParameters: DCacheParameters = DCacheParameters( 192 tagECC = Some("secded"), 193 dataECC = Some("secded"), 194 replacer = Some("setplru"), 195 nMissEntries = 16, 196 nProbeEntries = 16, 197 nReleaseEntries = 16, 198 nStoreReplayEntries = 16 199 ), 200 L2CacheParams: HCCacheParameters = HCCacheParameters( 201 name = "l2", 202 level = 2, 203 ways = 8, 204 sets = 1024, // default 512KB L2 205 prefetch = Some(huancun.prefetch.BOPParameters()) 206 ), 207 usePTWRepeater: Boolean = false, 208 useFakePTW: Boolean = false, 209 useFakeDCache: Boolean = false, 210 useFakeL1plusCache: Boolean = false, 211 useFakeL2Cache: Boolean = false 212){ 213 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 214 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 215 216 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 217 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 218 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 219 220 val fpExuConfigs = 221 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 222 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 223 224 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 225} 226 227case object DebugOptionsKey extends Field[DebugOptions] 228 229case class DebugOptions 230( 231 FPGAPlatform: Boolean = true, 232 EnableDebug: Boolean = true, 233 EnablePerfDebug: Boolean = true, 234 UseDRAMSim: Boolean = false 235) 236 237trait HasXSParameter { 238 239 implicit val p: Parameters 240 241 val coreParams = p(XSCoreParamsKey) 242 val env = p(DebugOptionsKey) 243 244 val XLEN = coreParams.XLEN 245 val hardId = coreParams.HartId 246 val minFLen = 32 247 val fLen = 64 248 def xLen = XLEN 249 250 val HasMExtension = coreParams.HasMExtension 251 val HasCExtension = coreParams.HasCExtension 252 val HasDiv = coreParams.HasDiv 253 val HasIcache = coreParams.HasICache 254 val HasDcache = coreParams.HasDCache 255 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 256 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 257 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 258 val AddrBytes = AddrBits / 8 // unused 259 val DataBits = XLEN 260 val DataBytes = DataBits / 8 261 val HasFPU = coreParams.HasFPU 262 val FetchWidth = coreParams.FetchWidth 263 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 264 val EnableBPU = coreParams.EnableBPU 265 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 266 val EnableRAS = coreParams.EnableRAS 267 val EnableLB = coreParams.EnableLB 268 val EnableLoop = coreParams.EnableLoop 269 val EnableSC = coreParams.EnableSC 270 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 271 val HistoryLength = coreParams.HistoryLength 272 val PathHistoryLength = coreParams.PathHistoryLength 273 val BtbSize = coreParams.BtbSize 274 // val BtbWays = 4 275 val BtbBanks = PredictWidth 276 // val BtbSets = BtbSize / BtbWays 277 val JbtacSize = coreParams.JbtacSize 278 val JbtacBanks = coreParams.JbtacBanks 279 val RasSize = coreParams.RasSize 280 281 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 282 coreParams.branchPredictor(resp_in, p, enableSC) 283 } 284 285 val CacheLineSize = coreParams.CacheLineSize 286 val CacheLineHalfWord = CacheLineSize / 16 287 val ExtHistoryLength = HistoryLength + 64 288 val UBtbWays = coreParams.UBtbWays 289 val BtbWays = coreParams.BtbWays 290 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 291 val IBufSize = coreParams.IBufSize 292 val DecodeWidth = coreParams.DecodeWidth 293 val RenameWidth = coreParams.RenameWidth 294 val CommitWidth = coreParams.CommitWidth 295 val FtqSize = coreParams.FtqSize 296 val IssQueSize = coreParams.IssQueSize 297 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 298 val NRPhyRegs = coreParams.NRPhyRegs 299 val PhyRegIdxWidth = log2Up(NRPhyRegs) 300 val RobSize = coreParams.RobSize 301 val EnableIntMoveElim = coreParams.EnableIntMoveElim 302 val IntRefCounterWidth = coreParams.IntRefCounterWidth 303 val StdFreeListSize = NRPhyRegs - 32 304 // val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 305 val MEFreeListSize = NRPhyRegs 306 val LoadQueueSize = coreParams.LoadQueueSize 307 val StoreQueueSize = coreParams.StoreQueueSize 308 val dpParams = coreParams.dpParams 309 val exuParameters = coreParams.exuParameters 310 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 311 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 312 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 313 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 314 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 315 val LoadPipelineWidth = coreParams.LoadPipelineWidth 316 val StorePipelineWidth = coreParams.StorePipelineWidth 317 val StoreBufferSize = coreParams.StoreBufferSize 318 val StoreBufferThreshold = coreParams.StoreBufferThreshold 319 val EnableFastForward = coreParams.EnableFastForward 320 val RefillSize = coreParams.RefillSize 321 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 322 val refillBothTlb = coreParams.refillBothTlb 323 val useBTlb = coreParams.useBTlb 324 val itlbParams = coreParams.itlbParameters 325 val ldtlbParams = coreParams.ldtlbParameters 326 val sttlbParams = coreParams.sttlbParameters 327 val btlbParams = coreParams.btlbParameters 328 val l2tlbParams = coreParams.l2tlbParameters 329 val NumPerfCounters = coreParams.NumPerfCounters 330 331 val instBytes = if (HasCExtension) 2 else 4 332 val instOffsetBits = log2Ceil(instBytes) 333 334 val icacheParameters = coreParams.icacheParameters 335 val dcacheParameters = coreParams.dcacheParameters 336 337 val LRSCCycles = 100 338 339 340 // cache hierarchy configurations 341 val l1BusDataWidth = 256 342 343 val useFakeDCache = coreParams.useFakeDCache 344 val useFakePTW = coreParams.useFakePTW 345 val useFakeL1plusCache = coreParams.useFakeL1plusCache 346 // L2 configurations 347 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 348 val L1BusWidth = 256 349 val L2BlockSize = 64 350 351 // L3 configurations 352 val L2BusWidth = 256 353 354 // load violation predict 355 val ResetTimeMax2Pow = 20 //1078576 356 val ResetTimeMin2Pow = 10 //1024 357 // wait table parameters 358 val WaitTableSize = 1024 359 val MemPredPCWidth = log2Up(WaitTableSize) 360 val LWTUse2BitCounter = true 361 // store set parameters 362 val SSITSize = WaitTableSize 363 val LFSTSize = 32 364 val SSIDWidth = log2Up(LFSTSize) 365 val LFSTWidth = 4 366 val StoreSetEnable = true // LWT will be disabled if SS is enabled 367 368 val loadExuConfigs = coreParams.loadExuConfigs 369 val storeExuConfigs = coreParams.storeExuConfigs 370 371 val intExuConfigs = coreParams.intExuConfigs 372 373 val fpExuConfigs = coreParams.fpExuConfigs 374 375 val exuConfigs = coreParams.exuConfigs 376 377} 378