1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18import utils._ 19import chisel3._ 20import chisel3.util._ 21import chipsalliance.rocketchip.config.Parameters 22import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 23import xiangshan._ 24import xiangshan.cache._ 25import xiangshan.cache.mmu.{TlbRequestIO, TlbPtwIO,TLB} 26import xiangshan.backend.fu.{HasExceptionNO, PMP, PMPChecker, PFEvent} 27 28 29class Frontend()(implicit p: Parameters) extends LazyModule with HasXSParameter{ 30 31 val instrUncache = LazyModule(new InstrUncache()) 32 val icache = LazyModule(new ICache()) 33 34 lazy val module = new FrontendImp(this) 35} 36 37 38class FrontendImp (outer: Frontend) extends LazyModuleImp(outer) 39 with HasXSParameter 40 with HasExceptionNO 41{ 42 val io = IO(new Bundle() { 43 val fencei = Input(Bool()) 44 val ptw = new TlbPtwIO(2) 45 val backend = new FrontendToCtrlIO 46 val sfence = Input(new SfenceBundle) 47 val tlbCsr = Input(new TlbCsrBundle) 48 val csrCtrl = Input(new CustomCSRCtrlIO) 49 val csrUpdate = new DistributedCSRUpdateReq 50 val error = new L1CacheErrorInfo 51 val frontendInfo = new Bundle { 52 val ibufFull = Output(Bool()) 53 val bpuInfo = new Bundle { 54 val bpRight = Output(UInt(XLEN.W)) 55 val bpWrong = Output(UInt(XLEN.W)) 56 } 57 } 58 }) 59 60 //decouped-frontend modules 61 val bpu = Module(new Predictor) 62 val ifu = Module(new NewIFU) 63 val ibuffer = Module(new Ibuffer) 64 val ftq = Module(new Ftq) 65 //icache 66 67 //PFEvent 68 val pfevent = Module(new PFEvent) 69 val tlbCsr = RegNext(io.tlbCsr) 70 pfevent.io.distribute_csr := io.csrCtrl.distribute_csr 71 // pmp 72 val pmp = Module(new PMP()) 73 val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(3, sameCycle = true)).io)) 74 pmp.io.distribute_csr := io.csrCtrl.distribute_csr 75 for (i <- pmp_check.indices) { 76 pmp_check(i).env.pmp := pmp.io.pmp 77 pmp_check(i).env.mode := tlbCsr.priv.imode 78 pmp_check(i).req <> ifu.io.pmp(i).req 79 ifu.io.pmp(i).resp <> pmp_check(i).resp 80 } 81 82 io.ptw <> TLB( 83 in = Seq(ifu.io.iTLBInter(0), ifu.io.iTLBInter(1)), 84 sfence = io.sfence, 85 csr = tlbCsr, 86 width = 2, 87 shouldBlock = true, 88 itlbParams 89 ) 90 //TODO: modules need to be removed 91 val instrUncache = outer.instrUncache.module 92 val icache = outer.icache.module 93 94 icache.io.fencei := RegNext(io.fencei) 95 96 val needFlush = io.backend.toFtq.stage3Redirect.valid 97 98 //IFU-Ftq 99 ifu.io.ftqInter.fromFtq <> ftq.io.toIfu 100 ftq.io.fromIfu <> ifu.io.ftqInter.toFtq 101 bpu.io.ftq_to_bpu <> ftq.io.toBpu 102 ftq.io.fromBpu <> bpu.io.bpu_to_ftq 103 //IFU-ICache 104 ifu.io.icacheInter.toIMeta <> icache.io.metaRead.req 105 ifu.io.icacheInter.fromIMeta <> icache.io.metaRead.resp 106 ifu.io.icacheInter.toIData <> icache.io.dataRead.req 107 ifu.io.icacheInter.fromIData <> icache.io.dataRead.resp 108 109 for(i <- 0 until 2){ 110 ifu.io.icacheInter.toMissQueue(i) <> icache.io.missQueue.req(i) 111 ifu.io.icacheInter.fromMissQueue(i) <> icache.io.missQueue.resp(i) 112 } 113 114 icache.io.missQueue.flush := ifu.io.ftqInter.fromFtq.redirect.valid || (ifu.io.ftqInter.toFtq.pdWb.valid && ifu.io.ftqInter.toFtq.pdWb.bits.misOffset.valid) 115 116 icache.io.csr.distribute_csr <> io.csrCtrl.distribute_csr 117 icache.io.csr.update <> io.csrUpdate 118 119 //IFU-Ibuffer 120 ifu.io.toIbuffer <> ibuffer.io.in 121 122 ftq.io.fromBackend <> io.backend.toFtq 123 io.backend.fromFtq <> ftq.io.toBackend 124 io.frontendInfo.bpuInfo <> ftq.io.bpuInfo 125 126 ibuffer.io.flush := needFlush 127 io.backend.cfVec <> ibuffer.io.out 128 129 instrUncache.io.req <> ifu.io.uncacheInter.toUncache 130 ifu.io.uncacheInter.fromUncache <> instrUncache.io.resp 131 instrUncache.io.flush := icache.io.missQueue.flush 132 io.error <> DontCare 133 134 val frontendBubble = PopCount((0 until DecodeWidth).map(i => io.backend.cfVec(i).ready && !ibuffer.io.out(i).valid)) 135 XSPerfAccumulate("FrontendBubble", frontendBubble) 136 io.frontendInfo.ibufFull := RegNext(ibuffer.io.full) 137 138 if(print_perfcounter){ 139 val ifu_perf = ifu.perfEvents.map(_._1).zip(ifu.perfinfo.perfEvents.perf_events) 140 val ibuffer_perf = ibuffer.perfEvents.map(_._1).zip(ibuffer.perfinfo.perfEvents.perf_events) 141 val icache_perf = icache.perfEvents.map(_._1).zip(icache.perfinfo.perfEvents.perf_events) 142 val ftq_perf = ftq.perfEvents.map(_._1).zip(ftq.perfinfo.perfEvents.perf_events) 143 val bpu_perf = bpu.perfEvents.map(_._1).zip(bpu.perfinfo.perfEvents.perf_events) 144 val perfEvents = ifu_perf ++ ibuffer_perf ++ icache_perf ++ ftq_perf ++ bpu_perf 145 146 for (((perf_name,perf),i) <- perfEvents.zipWithIndex) { 147 println(s"frontend perf $i: $perf_name") 148 } 149 } 150 151 val hpmEvents = ifu.perfinfo.perfEvents.perf_events ++ ibuffer.perfinfo.perfEvents.perf_events ++ 152 icache.perfinfo.perfEvents.perf_events ++ ftq.perfinfo.perfEvents.perf_events ++ 153 bpu.perfinfo.perfEvents.perf_events 154 val perf_length = hpmEvents.length 155 val csrevents = pfevent.io.hpmevent.slice(0,8) 156 val perfinfo = IO(new Bundle(){ 157 val perfEvents = Output(new PerfEventsBundle(csrevents.length)) 158 }) 159 val hpm_frontend = Module(new HPerfmonitor(perf_length,csrevents.length)) 160 hpm_frontend.io.hpm_event := csrevents 161 hpm_frontend.io.events_sets.perf_events := hpmEvents 162 perfinfo.perfEvents := RegNext(hpm_frontend.io.events_selected) 163} 164