1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 24import utils._ 25import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 26import freechips.rocketchip.tilelink._ 27 28case class TLBParameters 29( 30 name: String = "none", 31 fetchi: Boolean = false, // TODO: remove it 32 useDmode: Boolean = true, 33 sameCycle: Boolean = false, 34 normalNSets: Int = 1, // when da or sa 35 normalNWays: Int = 8, // when fa or sa 36 superNSets: Int = 1, 37 superNWays: Int = 2, 38 normalReplacer: Option[String] = Some("random"), 39 superReplacer: Option[String] = Some("plru"), 40 normalAssociative: String = "fa", // "fa", "sa", "da", "sa" is not supported 41 superAssociative: String = "fa", // must be fa 42 normalAsVictim: Boolean = false, // when get replace from fa, store it into sram 43 outReplace: Boolean = false, 44 shouldBlock: Boolean = false // only for perf, not support for io 45) 46 47case class L2TLBParameters 48( 49 name: String = "l2tlb", 50 // l1 51 l1Size: Int = 16, 52 l1Associative: String = "fa", 53 l1Replacer: Option[String] = Some("plru"), 54 // l2 55 l2nSets: Int = 32, 56 l2nWays: Int = 2, 57 l2Replacer: Option[String] = Some("setplru"), 58 // l3 59 l3nSets: Int = 128, 60 l3nWays: Int = 4, 61 l3Replacer: Option[String] = Some("setplru"), 62 // sp 63 spSize: Int = 16, 64 spReplacer: Option[String] = Some("plru"), 65 // dtlb filter 66 filterSize: Int = 8, 67 // miss queue, add more entries than 'must require' 68 // 0 for easier bug trigger, please set as big as u can, 8 maybe 69 missqueueExtendSize: Int = 0, 70 // way size 71 blockBytes: Int = 64, 72 // prefetch 73 enablePrefetch: Boolean = true, 74 // ecc 75 ecc: Option[String] = Some("secded") 76) 77 78trait HasTlbConst extends HasXSParameter { 79 val Level = 3 80 81 val offLen = 12 82 val ppnLen = PAddrBits - offLen 83 val vpnnLen = 9 84 val vpnLen = VAddrBits - offLen 85 val flagLen = 8 86 val pteResLen = XLEN - ppnLen - 2 - flagLen 87 val asidLen = 16 88 89 val sramSinglePort = true 90 91 val timeOutThreshold = 2000 92 93 def get_idx(vpn: UInt, nSets: Int): UInt = { 94 vpn(log2Up(nSets)-1, 0) 95 } 96 97 def replaceWrapper(v: UInt, lruIdx: UInt): UInt = { 98 val width = v.getWidth 99 val emptyIdx = ParallelPriorityMux((0 until width).map( i => (!v(i), i.U))) 100 val full = Cat(v).andR 101 Mux(full, lruIdx, emptyIdx) 102 } 103 104 def replaceWrapper(v: Seq[Bool], lruIdx: UInt): UInt = { 105 replaceWrapper(VecInit(v).asUInt, lruIdx) 106 } 107 108} 109 110trait HasPtwConst extends HasTlbConst with MemoryOpConstants{ 111 val PtwWidth = 2 112 val sourceWidth = { if (l2tlbParams.enablePrefetch) PtwWidth + 1 else PtwWidth} 113 val prefetchID = PtwWidth 114 val maxPrefetchNum = l2tlbParams.filterSize 115 116 val blockBits = l2tlbParams.blockBytes * 8 117 118 val bPtwWidth = log2Up(PtwWidth) 119 val bSourceWidth = log2Up(sourceWidth) 120 // ptwl1: fully-associated 121 val PtwL1TagLen = vpnnLen 122 123 /* +-------+----------+-------------+ 124 * | Tag | SetIdx | SectorIdx | 125 * +-------+----------+-------------+ 126 */ 127 // ptwl2: 8-way group-associated 128 val l2tlbParams.l2nWays = l2tlbParams.l2nWays 129 val PtwL2SetNum = l2tlbParams.l2nSets 130 val PtwL2SectorSize = blockBits /XLEN 131 val PtwL2IdxLen = log2Up(PtwL2SetNum * PtwL2SectorSize) 132 val PtwL2SectorIdxLen = log2Up(PtwL2SectorSize) 133 val PtwL2SetIdxLen = log2Up(PtwL2SetNum) 134 val PtwL2TagLen = vpnnLen * 2 - PtwL2IdxLen 135 136 // ptwl3: 16-way group-associated 137 val l2tlbParams.l3nWays = l2tlbParams.l3nWays 138 val PtwL3SetNum = l2tlbParams.l3nSets 139 val PtwL3SectorSize = blockBits / XLEN 140 val PtwL3IdxLen = log2Up(PtwL3SetNum * PtwL3SectorSize) 141 val PtwL3SectorIdxLen = log2Up(PtwL3SectorSize) 142 val PtwL3SetIdxLen = log2Up(PtwL3SetNum) 143 val PtwL3TagLen = vpnnLen * 3 - PtwL3IdxLen 144 145 // super page, including 1GB and 2MB page 146 val SPTagLen = vpnnLen * 2 147 148 // miss queue 149 val MSHRBaseSize = 1 + l2tlbParams.filterSize + l2tlbParams.missqueueExtendSize 150 val MSHRSize = { if (l2tlbParams.enablePrefetch) (MSHRBaseSize + 1) else MSHRBaseSize } 151 val MemReqWidth = MSHRSize + 1 152 val FsmReqID = MSHRSize 153 val bMemID = log2Up(MSHRSize + 1) 154 155 def genPtwL2Idx(vpn: UInt) = { 156 (vpn(vpnLen - 1, vpnnLen))(PtwL2IdxLen - 1, 0) 157 } 158 159 def genPtwL2SectorIdx(vpn: UInt) = { 160 genPtwL2Idx(vpn)(PtwL2SectorIdxLen - 1, 0) 161 } 162 163 def genPtwL2SetIdx(vpn: UInt) = { 164 genPtwL2Idx(vpn)(PtwL2SetIdxLen + PtwL2SectorIdxLen - 1, PtwL2SectorIdxLen) 165 } 166 167 def genPtwL3Idx(vpn: UInt) = { 168 vpn(PtwL3IdxLen - 1, 0) 169 } 170 171 def genPtwL3SectorIdx(vpn: UInt) = { 172 genPtwL3Idx(vpn)(PtwL3SectorIdxLen - 1, 0) 173 } 174 175 def dropL3SectorBits(vpn: UInt) = { 176 vpn(vpn.getWidth-1, PtwL3SectorIdxLen) 177 } 178 179 def genPtwL3SetIdx(vpn: UInt) = { 180 genPtwL3Idx(vpn)(PtwL3SetIdxLen + PtwL3SectorIdxLen - 1, PtwL3SectorIdxLen) 181 } 182 183 def MakeAddr(ppn: UInt, off: UInt) = { 184 require(off.getWidth == 9) 185 Cat(ppn, off, 0.U(log2Up(XLEN/8).W))(PAddrBits-1, 0) 186 } 187 188 def getVpnn(vpn: UInt, idx: Int): UInt = { 189 vpn(vpnnLen*(idx+1)-1, vpnnLen*idx) 190 } 191 192 def getVpnClip(vpn: UInt, level: Int) = { 193 // level 0 /* vpnn2 */ 194 // level 1 /* vpnn2 * vpnn1 */ 195 // level 2 /* vpnn2 * vpnn1 * vpnn0*/ 196 vpn(vpnLen - 1, (2 - level) * vpnnLen) 197 } 198 199 def get_next_line(vpn: UInt) = { 200 Cat(dropL3SectorBits(vpn) + 1.U, 0.U(PtwL3SectorIdxLen.W)) 201 } 202 203 def same_l2entry(vpn1: UInt, vpn2: UInt) = { 204 vpn1(vpnLen-1, vpnnLen) === vpn2(vpnLen-1, vpnnLen) 205 } 206 207 def from_pre(source: UInt) = { 208 (source === prefetchID.U) 209 } 210 211 def printVec[T <: Data](x: Seq[T]): Printable = { 212 (0 until x.length).map(i => p"(${i.U})${x(i)} ").reduce(_+_) 213 } 214} 215