1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17import chisel3._ 18import chisel3.util._ 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.tile.XLen 21import xiangshan.backend.fu._ 22import xiangshan.backend.fu.fpu._ 23import xiangshan.backend.exu._ 24import xiangshan.backend.{AmoData, Std} 25 26package object xiangshan { 27 object SrcType { 28 def reg = "b00".U 29 def pc = "b01".U 30 def imm = "b01".U 31 def fp = "b10".U 32 33 def DC = imm // Don't Care 34 35 def isReg(srcType: UInt) = srcType===reg 36 def isPc(srcType: UInt) = srcType===pc 37 def isImm(srcType: UInt) = srcType===imm 38 def isFp(srcType: UInt) = srcType(1) 39 def isPcOrImm(srcType: UInt) = srcType(0) 40 def isRegOrFp(srcType: UInt) = !srcType(0) 41 def regIsFp(srcType: UInt) = srcType(1) 42 43 def apply() = UInt(2.W) 44 } 45 46 object SrcState { 47 def busy = "b0".U 48 def rdy = "b1".U 49 // def specRdy = "b10".U // speculative ready, for future use 50 def apply() = UInt(1.W) 51 } 52 53 object FuType { 54 def jmp = "b0000".U 55 def i2f = "b0001".U 56 def csr = "b0010".U 57 def alu = "b0110".U 58 def mul = "b0100".U 59 def div = "b0101".U 60 def fence = "b0011".U 61 def bku = "b0111".U 62 63 def fmac = "b1000".U 64 def fmisc = "b1011".U 65 def fDivSqrt = "b1010".U 66 67 def ldu = "b1100".U 68 def stu = "b1101".U 69 def mou = "b1111".U // for amo, lr, sc, fence 70 71 def num = 14 72 73 def apply() = UInt(log2Up(num).W) 74 75 def isIntExu(fuType: UInt) = !fuType(3) 76 def isJumpExu(fuType: UInt) = fuType === jmp 77 def isFpExu(fuType: UInt) = fuType(3, 2) === "b10".U 78 def isMemExu(fuType: UInt) = fuType(3, 2) === "b11".U 79 def isLoadStore(fuType: UInt) = isMemExu(fuType) && !fuType(1) 80 def isStoreExu(fuType: UInt) = isMemExu(fuType) && fuType(0) 81 def isAMO(fuType: UInt) = fuType(1) 82 83 def jmpCanAccept(fuType: UInt) = !fuType(2) 84 def mduCanAccept(fuType: UInt) = fuType(2) && !fuType(1) || fuType(2) && fuType(1) && fuType(0) 85 def aluCanAccept(fuType: UInt) = fuType(2) && fuType(1) && !fuType(0) 86 87 def fmacCanAccept(fuType: UInt) = !fuType(1) 88 def fmiscCanAccept(fuType: UInt) = fuType(1) 89 90 def loadCanAccept(fuType: UInt) = !fuType(0) 91 def storeCanAccept(fuType: UInt) = fuType(0) 92 93 def storeIsAMO(fuType: UInt) = fuType(1) 94 95 val functionNameMap = Map( 96 jmp.litValue() -> "jmp", 97 i2f.litValue() -> "int_to_float", 98 csr.litValue() -> "csr", 99 alu.litValue() -> "alu", 100 mul.litValue() -> "mul", 101 div.litValue() -> "div", 102 fence.litValue() -> "fence", 103 bku.litValue() -> "bku", 104 fmac.litValue() -> "fmac", 105 fmisc.litValue() -> "fmisc", 106 fDivSqrt.litValue() -> "fdiv/fsqrt", 107 ldu.litValue() -> "load", 108 stu.litValue() -> "store", 109 mou.litValue() -> "mou" 110 ) 111 } 112 113 object FuOpType { 114 def apply() = UInt(7.W) 115 } 116 117 object CommitType { 118 def NORMAL = "b000".U // int/fp 119 def BRANCH = "b001".U // branch 120 def LOAD = "b010".U // load 121 def STORE = "b011".U // store 122 123 def apply() = UInt(3.W) 124 def isFused(commitType: UInt): Bool = commitType(2) 125 def isLoadStore(commitType: UInt): Bool = !isFused(commitType) && commitType(1) 126 def lsInstIsStore(commitType: UInt): Bool = commitType(0) 127 def isStore(commitType: UInt): Bool = isLoadStore(commitType) && lsInstIsStore(commitType) 128 def isBranch(commitType: UInt): Bool = commitType(0) && !commitType(1) && !isFused(commitType) 129 } 130 131 object RedirectLevel { 132 def flushAfter = "b0".U 133 def flush = "b1".U 134 135 def apply() = UInt(1.W) 136 // def isUnconditional(level: UInt) = level(1) 137 def flushItself(level: UInt) = level(0) 138 // def isException(level: UInt) = level(1) && level(0) 139 } 140 141 object ExceptionVec { 142 def apply() = Vec(16, Bool()) 143 } 144 145 object PMAMode { 146 def R = "b1".U << 0 //readable 147 def W = "b1".U << 1 //writeable 148 def X = "b1".U << 2 //executable 149 def I = "b1".U << 3 //cacheable: icache 150 def D = "b1".U << 4 //cacheable: dcache 151 def S = "b1".U << 5 //enable speculative access 152 def A = "b1".U << 6 //enable atomic operation, A imply R & W 153 def C = "b1".U << 7 //if it is cacheable is configable 154 def Reserved = "b0".U 155 156 def apply() = UInt(7.W) 157 158 def read(mode: UInt) = mode(0) 159 def write(mode: UInt) = mode(1) 160 def execute(mode: UInt) = mode(2) 161 def icache(mode: UInt) = mode(3) 162 def dcache(mode: UInt) = mode(4) 163 def speculate(mode: UInt) = mode(5) 164 def atomic(mode: UInt) = mode(6) 165 def configable_cache(mode: UInt) = mode(7) 166 167 def strToMode(s: String) = { 168 var result = 0.U(8.W) 169 if (s.toUpperCase.indexOf("R") >= 0) result = result + R 170 if (s.toUpperCase.indexOf("W") >= 0) result = result + W 171 if (s.toUpperCase.indexOf("X") >= 0) result = result + X 172 if (s.toUpperCase.indexOf("I") >= 0) result = result + I 173 if (s.toUpperCase.indexOf("D") >= 0) result = result + D 174 if (s.toUpperCase.indexOf("S") >= 0) result = result + S 175 if (s.toUpperCase.indexOf("A") >= 0) result = result + A 176 if (s.toUpperCase.indexOf("C") >= 0) result = result + C 177 result 178 } 179 } 180 181 182 object CSROpType { 183 def jmp = "b000".U 184 def wrt = "b001".U 185 def set = "b010".U 186 def clr = "b011".U 187 def wrti = "b101".U 188 def seti = "b110".U 189 def clri = "b111".U 190 } 191 192 // jump 193 object JumpOpType { 194 def jal = "b00".U 195 def jalr = "b01".U 196 def auipc = "b10".U 197// def call = "b11_011".U 198// def ret = "b11_100".U 199 def jumpOpisJalr(op: UInt) = op(0) 200 def jumpOpisAuipc(op: UInt) = op(1) 201 } 202 203 object FenceOpType { 204 def fence = "b10000".U 205 def sfence = "b10001".U 206 def fencei = "b10010".U 207 } 208 209 object ALUOpType { 210 // shift optype 211 def slliuw = "b000_0000".U // slliuw: ZEXT(src1[31:0]) << shamt 212 def sll = "b000_0001".U // sll: src1 << src2 213 214 def bclr = "b000_0010".U // bclr: src1 & ~(1 << src2[5:0]) 215 def bset = "b000_0011".U // bset: src1 | (1 << src2[5:0]) 216 def binv = "b000_0100".U // binv: src1 ^ ~(1 << src2[5:0]) 217 218 def srl = "b000_0101".U // srl: src1 >> src2 219 def bext = "b000_0110".U // bext: (src1 >> src2)[0] 220 def sra = "b000_0111".U // sra: src1 >> src2 (arithmetic) 221 222 def rol = "b000_1001".U // rol: (src1 << src2) | (src1 >> (xlen - src2)) 223 def ror = "b000_1011".U // ror: (src1 >> src2) | (src1 << (xlen - src2)) 224 225 // RV64 32bit optype 226 def addw = "b001_0000".U // addw: SEXT((src1 + src2)[31:0]) 227 def oddaddw = "b001_0001".U // oddaddw: SEXT((src1[0] + src2)[31:0]) 228 def subw = "b001_0010".U // subw: SEXT((src1 - src2)[31:0]) 229 230 def addwbit = "b001_0100".U // addwbit: (src1 + src2)[0] 231 def addwbyte = "b001_0101".U // addwbyte: (src1 + src2)[7:0] 232 def addwzexth = "b001_0110".U // addwzexth: ZEXT((src1 + src2)[15:0]) 233 def addwsexth = "b001_0111".U // addwsexth: SEXT((src1 + src2)[15:0]) 234 235 def sllw = "b001_1000".U // sllw: SEXT((src1 << src2)[31:0]) 236 def srlw = "b001_1001".U // srlw: SEXT((src1[31:0] >> src2)[31:0]) 237 def sraw = "b001_1010".U // sraw: SEXT((src1[31:0] >> src2)[31:0]) 238 def rolw = "b001_1100".U 239 def rorw = "b001_1101".U 240 241 // ADD-op 242 def adduw = "b010_0000".U // adduw: src1[31:0] + src2 243 def add = "b010_0001".U // add: src1 + src2 244 def oddadd = "b010_0010".U // oddadd: src1[0] + src2 245 246 def sr29add = "b010_0100".U // sr29add: src1[63:29] + src2 247 def sr30add = "b010_0101".U // sr30add: src1[63:30] + src2 248 def sr31add = "b010_0110".U // sr31add: src1[63:31] + src2 249 def sr32add = "b010_0111".U // sr32add: src1[63:32] + src2 250 251 def sh1adduw = "b010_1000".U // sh1adduw: {src1[31:0], 1'b0} + src2 252 def sh1add = "b010_1001".U // sh1add: {src1[62:0], 1'b0} + src2 253 def sh2adduw = "b010_1010".U // sh2add_uw: {src1[31:0], 2'b0} + src2 254 def sh2add = "b010_1011".U // sh2add: {src1[61:0], 2'b0} + src2 255 def sh3adduw = "b010_1100".U // sh3add_uw: {src1[31:0], 3'b0} + src2 256 def sh3add = "b010_1101".U // sh3add: {src1[60:0], 3'b0} + src2 257 def sh4add = "b010_1111".U // sh4add: {src1[59:0], 4'b0} + src2 258 259 // SUB-op: src1 - src2 260 def sub = "b011_0000".U 261 def sltu = "b011_0001".U 262 def slt = "b011_0010".U 263 def maxu = "b011_0100".U 264 def minu = "b011_0101".U 265 def max = "b011_0110".U 266 def min = "b011_0111".U 267 268 // branch 269 def beq = "b111_0000".U 270 def bne = "b111_0010".U 271 def blt = "b111_1000".U 272 def bge = "b111_1010".U 273 def bltu = "b111_1100".U 274 def bgeu = "b111_1110".U 275 276 // misc optype 277 def and = "b100_0000".U 278 def andn = "b100_0001".U 279 def or = "b100_0010".U 280 def orn = "b100_0011".U 281 def xor = "b100_0100".U 282 def xnor = "b100_0101".U 283 def orcb = "b100_0110".U 284 285 def sextb = "b100_1000".U 286 def packh = "b100_1001".U 287 def sexth = "b100_1010".U 288 def packw = "b100_1011".U 289 290 def revb = "b101_0000".U 291 def rev8 = "b101_0001".U 292 def pack = "b101_0010".U 293 def orh48 = "b101_0011".U 294 295 def szewl1 = "b101_1000".U 296 def szewl2 = "b101_1001".U 297 def szewl3 = "b101_1010".U 298 def byte2 = "b101_1011".U 299 300 def andlsb = "b110_0000".U 301 def andzexth = "b110_0001".U 302 def orlsb = "b110_0010".U 303 def orzexth = "b110_0011".U 304 def xorlsb = "b110_0100".U 305 def xorzexth = "b110_0101".U 306 def orcblsb = "b110_0110".U 307 def orcbzexth = "b110_0111".U 308 309 def isAddw(func: UInt) = func(6, 4) === "b001".U && !func(3) && !func(1) 310 def isSimpleLogic(func: UInt) = func(6, 4) === "b100".U && !func(0) 311 def logicToLsb(func: UInt) = Cat("b110".U(3.W), func(3, 1), 0.U(1.W)) 312 def logicToZexth(func: UInt) = Cat("b110".U(3.W), func(3, 1), 1.U(1.W)) 313 def isBranch(func: UInt) = func(6, 4) === "b111".U 314 def getBranchType(func: UInt) = func(3, 2) 315 def isBranchInvert(func: UInt) = func(1) 316 317 def apply() = UInt(7.W) 318 } 319 320 object MDUOpType { 321 // mul 322 // bit encoding: | type (2bit) | isWord(1bit) | opcode(2bit) | 323 def mul = "b00000".U 324 def mulh = "b00001".U 325 def mulhsu = "b00010".U 326 def mulhu = "b00011".U 327 def mulw = "b00100".U 328 329 def mulw7 = "b01100".U 330 331 // div 332 // bit encoding: | type (2bit) | isWord(1bit) | isSign(1bit) | opcode(1bit) | 333 def div = "b10000".U 334 def divu = "b10010".U 335 def rem = "b10001".U 336 def remu = "b10011".U 337 338 def divw = "b10100".U 339 def divuw = "b10110".U 340 def remw = "b10101".U 341 def remuw = "b10111".U 342 343 def isMul(op: UInt) = !op(4) 344 def isDiv(op: UInt) = op(4) 345 346 def isDivSign(op: UInt) = isDiv(op) && !op(1) 347 def isW(op: UInt) = op(2) 348 def isH(op: UInt) = (isDiv(op) && op(0)) || (isMul(op) && op(1, 0) =/= 0.U) 349 def getMulOp(op: UInt) = op(1, 0) 350 } 351 352 object LSUOpType { 353 // normal load/store 354 // bit(1, 0) are size 355 def lb = "b000000".U 356 def lh = "b000001".U 357 def lw = "b000010".U 358 def ld = "b000011".U 359 def lbu = "b000100".U 360 def lhu = "b000101".U 361 def lwu = "b000110".U 362 def sb = "b001000".U 363 def sh = "b001001".U 364 def sw = "b001010".U 365 def sd = "b001011".U 366 367 def cbo_zero = "b001111".U // l1 cache op 368 369 def cbo_clean = "b011111".U // llc op 370 def cbo_flush = "b101111".U // llc op 371 def cbo_inval = "b111111".U // llc op 372 373 def isLoad(op: UInt): Bool = !op(3) 374 def isStore(op: UInt): Bool = op(3) 375 def isCbo(op: UInt): Bool = op(3, 0) === "b1111".U 376 377 // atomics 378 // bit(1, 0) are size 379 // since atomics use a different fu type 380 // so we can safely reuse other load/store's encodings 381 def lr_w = "b000010".U 382 def sc_w = "b000110".U 383 def amoswap_w = "b001010".U 384 def amoadd_w = "b001110".U 385 def amoxor_w = "b010010".U 386 def amoand_w = "b010110".U 387 def amoor_w = "b011010".U 388 def amomin_w = "b011110".U 389 def amomax_w = "b100010".U 390 def amominu_w = "b100110".U 391 def amomaxu_w = "b101010".U 392 393 def lr_d = "b000011".U 394 def sc_d = "b000111".U 395 def amoswap_d = "b001011".U 396 def amoadd_d = "b001111".U 397 def amoxor_d = "b010011".U 398 def amoand_d = "b010111".U 399 def amoor_d = "b011011".U 400 def amomin_d = "b011111".U 401 def amomax_d = "b100011".U 402 def amominu_d = "b100111".U 403 def amomaxu_d = "b101011".U 404 405 def size(op: UInt) = op(1,0) 406 } 407 408 object BKUOpType { 409 410 def clmul = "b000000".U 411 def clmulh = "b000001".U 412 def clmulr = "b000010".U 413 def xpermn = "b000100".U 414 def xpermb = "b000101".U 415 416 def clz = "b001000".U 417 def clzw = "b001001".U 418 def ctz = "b001010".U 419 def ctzw = "b001011".U 420 def cpop = "b001100".U 421 def cpopw = "b001101".U 422 423 // 01xxxx is reserve 424 def aes64es = "b100000".U 425 def aes64esm = "b100001".U 426 def aes64ds = "b100010".U 427 def aes64dsm = "b100011".U 428 def aes64im = "b100100".U 429 def aes64ks1i = "b100101".U 430 def aes64ks2 = "b100110".U 431 432 // merge to two instruction sm4ks & sm4ed 433 def sm4ks0 = "b101000".U 434 def sm4ks1 = "b101001".U 435 def sm4ks2 = "b101010".U 436 def sm4ks3 = "b101011".U 437 def sm4ed0 = "b101100".U 438 def sm4ed1 = "b101101".U 439 def sm4ed2 = "b101110".U 440 def sm4ed3 = "b101111".U 441 442 def sha256sum0 = "b110000".U 443 def sha256sum1 = "b110001".U 444 def sha256sig0 = "b110010".U 445 def sha256sig1 = "b110011".U 446 def sha512sum0 = "b110100".U 447 def sha512sum1 = "b110101".U 448 def sha512sig0 = "b110110".U 449 def sha512sig1 = "b110111".U 450 451 def sm3p0 = "b111000".U 452 def sm3p1 = "b111001".U 453 } 454 455 object BTBtype { 456 def B = "b00".U // branch 457 def J = "b01".U // jump 458 def I = "b10".U // indirect 459 def R = "b11".U // return 460 461 def apply() = UInt(2.W) 462 } 463 464 object SelImm { 465 def IMM_X = "b0111".U 466 def IMM_S = "b0000".U 467 def IMM_SB = "b0001".U 468 def IMM_U = "b0010".U 469 def IMM_UJ = "b0011".U 470 def IMM_I = "b0100".U 471 def IMM_Z = "b0101".U 472 def INVALID_INSTR = "b0110".U 473 def IMM_B6 = "b1000".U 474 475 def apply() = UInt(4.W) 476 } 477 478 def dividerGen(p: Parameters) = new SRT16Divider(p(XLen))(p) 479 def multiplierGen(p: Parameters) = new ArrayMultiplier(p(XLen) + 1)(p) 480 def aluGen(p: Parameters) = new Alu()(p) 481 def bkuGen(p: Parameters) = new Bku()(p) 482 def jmpGen(p: Parameters) = new Jump()(p) 483 def fenceGen(p: Parameters) = new Fence()(p) 484 def csrGen(p: Parameters) = new CSR()(p) 485 def i2fGen(p: Parameters) = new IntToFP()(p) 486 def fmacGen(p: Parameters) = new FMA()(p) 487 def f2iGen(p: Parameters) = new FPToInt()(p) 488 def f2fGen(p: Parameters) = new FPToFP()(p) 489 def fdivSqrtGen(p: Parameters) = new FDivSqrt()(p) 490 def stdGen(p: Parameters) = new Std()(p) 491 def mouDataGen(p: Parameters) = new AmoData()(p) 492 493 def f2iSel(uop: MicroOp): Bool = { 494 uop.ctrl.rfWen 495 } 496 497 def i2fSel(uop: MicroOp): Bool = { 498 uop.ctrl.fpu.fromInt 499 } 500 501 def f2fSel(uop: MicroOp): Bool = { 502 val ctrl = uop.ctrl.fpu 503 ctrl.fpWen && !ctrl.div && !ctrl.sqrt 504 } 505 506 def fdivSqrtSel(uop: MicroOp): Bool = { 507 val ctrl = uop.ctrl.fpu 508 ctrl.div || ctrl.sqrt 509 } 510 511 val aluCfg = FuConfig( 512 name = "alu", 513 fuGen = aluGen, 514 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.alu, 515 fuType = FuType.alu, 516 numIntSrc = 2, 517 numFpSrc = 0, 518 writeIntRf = true, 519 writeFpRf = false, 520 hasRedirect = true, 521 ) 522 523 val jmpCfg = FuConfig( 524 name = "jmp", 525 fuGen = jmpGen, 526 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.jmp, 527 fuType = FuType.jmp, 528 numIntSrc = 1, 529 numFpSrc = 0, 530 writeIntRf = true, 531 writeFpRf = false, 532 hasRedirect = true, 533 ) 534 535 val fenceCfg = FuConfig( 536 name = "fence", 537 fuGen = fenceGen, 538 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.fence, 539 FuType.fence, 2, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 540 latency = UncertainLatency(), // TODO: need rewrite latency structure, not just this value, 541 hasExceptionOut = true 542 ) 543 544 val csrCfg = FuConfig( 545 name = "csr", 546 fuGen = csrGen, 547 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.csr, 548 fuType = FuType.csr, 549 numIntSrc = 1, 550 numFpSrc = 0, 551 writeIntRf = true, 552 writeFpRf = false, 553 hasRedirect = false, 554 hasExceptionOut = true 555 ) 556 557 val i2fCfg = FuConfig( 558 name = "i2f", 559 fuGen = i2fGen, 560 fuSel = i2fSel, 561 FuType.i2f, 562 numIntSrc = 1, 563 numFpSrc = 0, 564 writeIntRf = false, 565 writeFpRf = true, 566 hasRedirect = false, 567 latency = CertainLatency(2), 568 fastUopOut = true, fastImplemented = true 569 ) 570 571 val divCfg = FuConfig( 572 name = "div", 573 fuGen = dividerGen, 574 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.div, 575 FuType.div, 576 2, 577 0, 578 writeIntRf = true, 579 writeFpRf = false, 580 hasRedirect = false, 581 latency = UncertainLatency(), 582 fastUopOut = true, 583 fastImplemented = false 584 ) 585 586 val mulCfg = FuConfig( 587 name = "mul", 588 fuGen = multiplierGen, 589 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.mul, 590 FuType.mul, 591 2, 592 0, 593 writeIntRf = true, 594 writeFpRf = false, 595 hasRedirect = false, 596 latency = CertainLatency(2), 597 fastUopOut = true, 598 fastImplemented = true 599 ) 600 601 val bkuCfg = FuConfig( 602 name = "bku", 603 fuGen = bkuGen, 604 fuSel = (uop: MicroOp) => uop.ctrl.fuType === FuType.bku, 605 fuType = FuType.bku, 606 numIntSrc = 2, 607 numFpSrc = 0, 608 writeIntRf = true, 609 writeFpRf = false, 610 hasRedirect = false, 611 latency = CertainLatency(1), 612 fastUopOut = true, 613 fastImplemented = true 614 ) 615 616 val fmacCfg = FuConfig( 617 name = "fmac", 618 fuGen = fmacGen, 619 fuSel = _ => true.B, 620 FuType.fmac, 0, 3, writeIntRf = false, writeFpRf = true, hasRedirect = false, 621 latency = UncertainLatency(), fastUopOut = true, fastImplemented = true 622 ) 623 624 val f2iCfg = FuConfig( 625 name = "f2i", 626 fuGen = f2iGen, 627 fuSel = f2iSel, 628 FuType.fmisc, 0, 1, writeIntRf = true, writeFpRf = false, hasRedirect = false, CertainLatency(2), 629 fastUopOut = true, fastImplemented = true 630 ) 631 632 val f2fCfg = FuConfig( 633 name = "f2f", 634 fuGen = f2fGen, 635 fuSel = f2fSel, 636 FuType.fmisc, 0, 1, writeIntRf = false, writeFpRf = true, hasRedirect = false, CertainLatency(2), 637 fastUopOut = true, fastImplemented = true 638 ) 639 640 val fdivSqrtCfg = FuConfig( 641 name = "fdivSqrt", 642 fuGen = fdivSqrtGen, 643 fuSel = fdivSqrtSel, 644 FuType.fDivSqrt, 0, 2, writeIntRf = false, writeFpRf = true, hasRedirect = false, UncertainLatency(), 645 fastUopOut = true, fastImplemented = false, hasInputBuffer = true 646 ) 647 648 val lduCfg = FuConfig( 649 "ldu", 650 null, // DontCare 651 (uop: MicroOp) => FuType.loadCanAccept(uop.ctrl.fuType), 652 FuType.ldu, 1, 0, writeIntRf = true, writeFpRf = true, hasRedirect = false, 653 latency = UncertainLatency(), hasExceptionOut = true 654 ) 655 656 val staCfg = FuConfig( 657 "sta", 658 null, 659 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 660 FuType.stu, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 661 latency = UncertainLatency(), hasExceptionOut = true 662 ) 663 664 val stdCfg = FuConfig( 665 "std", 666 fuGen = stdGen, fuSel = (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), FuType.stu, 1, 1, 667 writeIntRf = false, writeFpRf = false, hasRedirect = false, latency = CertainLatency(1) 668 ) 669 670 val mouCfg = FuConfig( 671 "mou", 672 null, 673 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 674 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 675 latency = UncertainLatency(), hasExceptionOut = true 676 ) 677 678 val mouDataCfg = FuConfig( 679 "mou", 680 mouDataGen, 681 (uop: MicroOp) => FuType.storeCanAccept(uop.ctrl.fuType), 682 FuType.mou, 1, 0, writeIntRf = false, writeFpRf = false, hasRedirect = false, 683 latency = UncertainLatency(), hasExceptionOut = true 684 ) 685 686 val JumpExeUnitCfg = ExuConfig("JmpExeUnit", "Int", Seq(jmpCfg, i2fCfg), 2, Int.MaxValue) 687 val AluExeUnitCfg = ExuConfig("AluExeUnit", "Int", Seq(aluCfg), 0, Int.MaxValue) 688 val JumpCSRExeUnitCfg = ExuConfig("JmpCSRExeUnit", "Int", Seq(jmpCfg, csrCfg, fenceCfg, i2fCfg), 2, Int.MaxValue) 689 val MulDivExeUnitCfg = ExuConfig("MulDivExeUnit", "Int", Seq(mulCfg, divCfg, bkuCfg), 1, Int.MaxValue) 690 val FmacExeUnitCfg = ExuConfig("FmacExeUnit", "Fp", Seq(fmacCfg), Int.MaxValue, 0) 691 val FmiscExeUnitCfg = ExuConfig( 692 "FmiscExeUnit", 693 "Fp", 694 Seq(f2iCfg, f2fCfg, fdivSqrtCfg), 695 Int.MaxValue, 1 696 ) 697 val LdExeUnitCfg = ExuConfig("LoadExu", "Mem", Seq(lduCfg), wbIntPriority = 0, wbFpPriority = 0, extendsExu = false) 698 val StaExeUnitCfg = ExuConfig("StaExu", "Mem", Seq(staCfg, mouCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 699 val StdExeUnitCfg = ExuConfig("StdExu", "Mem", Seq(stdCfg, mouDataCfg), wbIntPriority = Int.MaxValue, wbFpPriority = Int.MaxValue, extendsExu = false) 700} 701