1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.cache._ 25import xiangshan.cache.{DCacheWordIO, DCacheLineIO, MemoryOpConstants} 26import xiangshan.cache.mmu.{TlbRequestIO} 27import xiangshan.mem._ 28import xiangshan.backend.rob.RobLsqIO 29 30class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 31 val lsIdx = Input(new LSIdx) 32 val isStore = Input(Bool()) 33 val vaddr = Output(UInt(VAddrBits.W)) 34} 35 36class FwdEntry extends Bundle { 37 val validFast = Bool() // validFast is generated the same cycle with query 38 val valid = Bool() // valid is generated 1 cycle after query request 39 val data = UInt(8.W) // data is generated 1 cycle after query request 40} 41 42// inflight miss block reqs 43class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 44 val block_addr = UInt(PAddrBits.W) 45 val valid = Bool() 46} 47 48class LsqEnqIO(implicit p: Parameters) extends XSBundle { 49 val canAccept = Output(Bool()) 50 val needAlloc = Vec(RenameWidth, Input(UInt(2.W))) 51 val req = Vec(RenameWidth, Flipped(ValidIO(new MicroOp))) 52 val resp = Vec(RenameWidth, Output(new LSIdx)) 53} 54 55// Load / Store Queue Wrapper for XiangShan Out of Order LSU 56class LsqWrappper(implicit p: Parameters) extends XSModule with HasDCacheParameters { 57 val io = IO(new Bundle() { 58 val enq = new LsqEnqIO 59 val brqRedirect = Flipped(ValidIO(new Redirect)) 60 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LsPipelineBundle))) 61 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 62 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreDataBundle))) // store data, send to sq from rs 63 val loadDataForwarded = Vec(LoadPipelineWidth, Input(Bool())) 64 val needReplayFromRS = Vec(LoadPipelineWidth, Input(Bool())) 65 val sbuffer = Vec(StorePipelineWidth, Decoupled(new DCacheWordReqWithVaddr)) 66 val ldout = Vec(2, DecoupledIO(new ExuOutput)) // writeback int load 67 val mmioStout = DecoupledIO(new ExuOutput) // writeback uncached store 68 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 69 val rob = Flipped(new RobLsqIO) 70 val rollback = Output(Valid(new Redirect)) 71 val dcache = Flipped(ValidIO(new Refill)) 72 val uncache = new DCacheWordIO 73 val exceptionAddr = new ExceptionAddrIO 74 val sqempty = Output(Bool()) 75 val issuePtrExt = Output(new SqPtr) 76 val sqFull = Output(Bool()) 77 val lqFull = Output(Bool()) 78 }) 79 80 val loadQueue = Module(new LoadQueue) 81 val storeQueue = Module(new StoreQueue) 82 83 // io.enq logic 84 // LSQ: send out canAccept when both load queue and store queue are ready 85 // Dispatch: send instructions to LSQ only when they are ready 86 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 87 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 88 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 89 for (i <- 0 until RenameWidth) { 90 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 91 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 92 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 93 94 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 95 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 96 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 97 98 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 99 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 100 } 101 102 // load queue wiring 103 loadQueue.io.brqRedirect <> io.brqRedirect 104 loadQueue.io.loadIn <> io.loadIn 105 loadQueue.io.storeIn <> io.storeIn 106 loadQueue.io.loadDataForwarded <> io.loadDataForwarded 107 loadQueue.io.needReplayFromRS <> io.needReplayFromRS 108 loadQueue.io.ldout <> io.ldout 109 loadQueue.io.rob <> io.rob 110 loadQueue.io.rollback <> io.rollback 111 loadQueue.io.dcache <> io.dcache 112 loadQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 113 loadQueue.io.exceptionAddr.isStore := DontCare 114 115 // store queue wiring 116 // storeQueue.io <> DontCare 117 storeQueue.io.brqRedirect <> io.brqRedirect 118 storeQueue.io.storeIn <> io.storeIn 119 storeQueue.io.storeDataIn <> io.storeDataIn 120 storeQueue.io.sbuffer <> io.sbuffer 121 storeQueue.io.mmioStout <> io.mmioStout 122 storeQueue.io.rob <> io.rob 123 storeQueue.io.exceptionAddr.lsIdx := io.exceptionAddr.lsIdx 124 storeQueue.io.exceptionAddr.isStore := DontCare 125 storeQueue.io.issuePtrExt <> io.issuePtrExt 126 127 loadQueue.io.load_s1 <> io.forward 128 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 129 130 storeQueue.io.sqempty <> io.sqempty 131 132 io.exceptionAddr.vaddr := Mux(io.exceptionAddr.isStore, storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 133 134 // naive uncache arbiter 135 val s_idle :: s_load :: s_store :: Nil = Enum(3) 136 val pendingstate = RegInit(s_idle) 137 138 switch(pendingstate){ 139 is(s_idle){ 140 when(io.uncache.req.fire()){ 141 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, s_store) 142 } 143 } 144 is(s_load){ 145 when(io.uncache.resp.fire()){ 146 pendingstate := s_idle 147 } 148 } 149 is(s_store){ 150 when(io.uncache.resp.fire()){ 151 pendingstate := s_idle 152 } 153 } 154 } 155 156 loadQueue.io.uncache := DontCare 157 storeQueue.io.uncache := DontCare 158 loadQueue.io.uncache.resp.valid := false.B 159 storeQueue.io.uncache.resp.valid := false.B 160 when(loadQueue.io.uncache.req.valid){ 161 io.uncache.req <> loadQueue.io.uncache.req 162 }.otherwise{ 163 io.uncache.req <> storeQueue.io.uncache.req 164 } 165 when(pendingstate === s_load){ 166 io.uncache.resp <> loadQueue.io.uncache.resp 167 }.otherwise{ 168 io.uncache.resp <> storeQueue.io.uncache.resp 169 } 170 171 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 172 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 173 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 174 175 io.lqFull := loadQueue.io.lqFull 176 io.sqFull := storeQueue.io.sqFull 177} 178