1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.cache.mmu 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import chisel3.internal.naming.chiselName 23import xiangshan._ 24import xiangshan.cache.{HasDCacheParameters, MemoryOpConstants} 25import utils._ 26import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 27import freechips.rocketchip.tilelink._ 28 29/* ptw cache caches the page table of all the three layers 30 * ptw cache resp at next cycle 31 * the cache should not be blocked 32 * when miss queue if full, just block req outside 33 */ 34class PtwCacheIO()(implicit p: Parameters) extends PtwBundle { 35 val req = Flipped(DecoupledIO(new Bundle { 36 val vpn = UInt(vpnLen.W) 37 val source = UInt(bSourceWidth.W) 38 })) 39 val req_isFirst = Input(Bool()) // only for perf counter 40 val resp = DecoupledIO(new Bundle { 41 val source = UInt(bSourceWidth.W) 42 val vpn = UInt(vpnLen.W) 43 val hit = Bool() 44 val prefetch = Bool() // is the entry fetched by prefetch 45 val toFsm = new Bundle { 46 val l1Hit = Bool() 47 val l2Hit = Bool() 48 val ppn = UInt(ppnLen.W) 49 } 50 val toTlb = new PtwEntry(tagLen = vpnLen, hasPerm = true, hasLevel = true) 51 }) 52 val refill = Flipped(ValidIO(new Bundle { 53 val ptes = UInt(blockBits.W) 54 val vpn = UInt(vpnLen.W) 55 val level = UInt(log2Up(Level).W) 56 val prefetch = Bool() // is the req a prefetch req 57 val addr_low = UInt((log2Up(l2tlbParams.blockBytes) - log2Up(XLEN/8)).W) 58 })) 59 val sfence = Input(new SfenceBundle) 60} 61 62 63@chiselName 64class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst { 65 val io = IO(new PtwCacheIO) 66 67 val ecc = Code.fromString(l2tlbParams.ecc) 68 val l2EntryType = new PTWEntriesWithEcc(ecc, num = PtwL2SectorSize, tagLen = PtwL2TagLen, level = 1, hasPerm = false) 69 val l3EntryType = new PTWEntriesWithEcc(ecc, num = PtwL3SectorSize, tagLen = PtwL3TagLen, level = 2, hasPerm = true) 70 71 // TODO: four caches make the codes dirty, think about how to deal with it 72 73 val sfence = io.sfence 74 val refill = io.refill.bits 75 76 val first_valid = io.req.valid 77 val first_fire = first_valid && io.req.ready 78 val first_req = io.req.bits 79 val second_ready = Wire(Bool()) 80 val second_valid = ValidHold(first_fire && !sfence.valid, io.resp.fire(), sfence.valid) 81 val second_req = RegEnable(first_req, first_fire) 82 // NOTE: if ptw cache resp may be blocked, hard to handle refill 83 // when miss queue is full, please to block itlb and dtlb input 84 val second_isFirst = RegEnable(io.req_isFirst, first_fire) // only for perf counter 85 86 // when refill, refuce to accept new req 87 val rwHarzad = if (sramSinglePort) io.refill.valid else false.B 88 io.req.ready := !rwHarzad && second_ready 89 // NOTE: when write, don't ready, whe 90 // when replay, just come in, out make sure resp.fire() 91 92 // l1: level 0 non-leaf pte 93 val l1 = Reg(Vec(l2tlbParams.l1Size, new PtwEntry(tagLen = PtwL1TagLen))) 94 val l1v = RegInit(0.U(l2tlbParams.l1Size.W)) 95 val l1g = Reg(UInt(l2tlbParams.l1Size.W)) 96 97 // l2: level 1 non-leaf pte 98 val l2 = Module(new SRAMTemplate( 99 l2EntryType, 100 set = l2tlbParams.l2nSets, 101 way = l2tlbParams.l2nWays, 102 singlePort = sramSinglePort 103 )) 104 val l2v = RegInit(0.U((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W)) 105 val l2g = Reg(UInt((l2tlbParams.l2nSets * l2tlbParams.l2nWays).W)) 106 def getl2vSet(vpn: UInt) = { 107 require(log2Up(l2tlbParams.l2nWays) == log2Down(l2tlbParams.l2nWays)) 108 val set = genPtwL2SetIdx(vpn) 109 require(set.getWidth == log2Up(l2tlbParams.l2nSets)) 110 val l2vVec = l2v.asTypeOf(Vec(l2tlbParams.l2nSets, UInt(l2tlbParams.l2nWays.W))) 111 l2vVec(set) 112 } 113 114 // l3: level 2 leaf pte of 4KB pages 115 val l3 = Module(new SRAMTemplate( 116 l3EntryType, 117 set = l2tlbParams.l3nSets, 118 way = l2tlbParams.l3nWays, 119 singlePort = sramSinglePort 120 )) 121 val l3v = RegInit(0.U((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W)) 122 val l3g = Reg(UInt((l2tlbParams.l3nSets * l2tlbParams.l3nWays).W)) 123 def getl3vSet(vpn: UInt) = { 124 require(log2Up(l2tlbParams.l3nWays) == log2Down(l2tlbParams.l3nWays)) 125 val set = genPtwL3SetIdx(vpn) 126 require(set.getWidth == log2Up(l2tlbParams.l3nSets)) 127 val l3vVec = l3v.asTypeOf(Vec(l2tlbParams.l3nSets, UInt(l2tlbParams.l3nWays.W))) 128 l3vVec(set) 129 } 130 131 // sp: level 0/1 leaf pte of 1GB/2MB super pages 132 val sp = Reg(Vec(l2tlbParams.spSize, new PtwEntry(tagLen = SPTagLen, hasPerm = true, hasLevel = true))) 133 val spv = RegInit(0.U(l2tlbParams.spSize.W)) 134 val spg = Reg(UInt(l2tlbParams.spSize.W)) 135 136 // Access Perf 137 val l1AccessPerf = Wire(Vec(l2tlbParams.l1Size, Bool())) 138 val l2AccessPerf = Wire(Vec(l2tlbParams.l2nWays, Bool())) 139 val l3AccessPerf = Wire(Vec(l2tlbParams.l3nWays, Bool())) 140 val spAccessPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 141 l1AccessPerf.map(_ := false.B) 142 l2AccessPerf.map(_ := false.B) 143 l3AccessPerf.map(_ := false.B) 144 spAccessPerf.map(_ := false.B) 145 146 val cache_read_valid = OneCycleValid(first_fire, sfence.valid) 147 // l1 148 val ptwl1replace = ReplacementPolicy.fromString(l2tlbParams.l1Replacer, l2tlbParams.l1Size) 149 val (l1Hit, l1HitPPN, l1Pre) = { 150 val hitVecT = l1.zipWithIndex.map { case (e, i) => e.hit(first_req.vpn) && l1v(i) } 151 val hitVec = hitVecT.map(RegEnable(_, first_fire)) 152 val hitPPN = ParallelPriorityMux(hitVec zip l1.map(_.ppn)) 153 val hitPre = ParallelPriorityMux(hitVec zip l1.map(_.prefetch)) 154 val hit = ParallelOR(hitVec) && cache_read_valid 155 156 when (hit) { ptwl1replace.access(OHToUInt(hitVec)) } 157 158 l1AccessPerf.zip(hitVec).map{ case (l, h) => l := h && RegNext(first_fire)} 159 for (i <- 0 until l2tlbParams.l1Size) { 160 XSDebug(first_fire, p"[l1] l1(${i.U}) ${l1(i)} hit:${l1(i).hit(first_req.vpn)}\n") 161 } 162 XSDebug(first_fire, p"[l1] l1v:${Binary(l1v)} hitVecT:${Binary(VecInit(hitVecT).asUInt)}\n") 163 XSDebug(second_valid, p"[l1] l1Hit:${hit} l1HitPPN:0x${Hexadecimal(hitPPN)} hitVec:${VecInit(hitVec).asUInt}\n") 164 165 VecInit(hitVecT).suggestName(s"l1_hitVecT") 166 VecInit(hitVec).suggestName(s"l1_hitVec") 167 168 (hit, hitPPN, hitPre) 169 } 170 171 // l2 172 val ptwl2replace = ReplacementPolicy.fromString(l2tlbParams.l2Replacer,l2tlbParams.l2nWays,l2tlbParams.l2nSets) 173 val (l2Hit, l2HitPPN, l2Pre, l2eccError) = { 174 val ridx = genPtwL2SetIdx(first_req.vpn) 175 val vidx = RegEnable(VecInit(getl2vSet(first_req.vpn).asBools), first_fire) 176 l2.io.r.req.valid := first_fire 177 l2.io.r.req.bits.apply(setIdx = ridx) 178 val ramDatas = l2.io.r.resp.data 179 // val hitVec = VecInit(ramDatas.map{wayData => wayData.hit(first_req.vpn) }) 180 val hitVec = VecInit(ramDatas.zip(vidx).map { case (wayData, v) => wayData.entries.hit(second_req.vpn) && v }) 181 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 182 val hitWayData = hitWayEntry.entries 183 val hitWayEcc = hitWayEntry.ecc 184 val hit = ParallelOR(hitVec) && cache_read_valid && RegNext(l2.io.r.req.ready, init = false.B) 185 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l2nWays).map(_.U)) 186 187 val eccError = ecc.decode(Cat(hitWayEcc, hitWayData.asUInt())).error 188 189 ridx.suggestName(s"l2_ridx") 190 vidx.suggestName(s"l2_vidx") 191 ramDatas.suggestName(s"l2_ramDatas") 192 hitVec.suggestName(s"l2_hitVec") 193 hitWayData.suggestName(s"l2_hitWayData") 194 hitWay.suggestName(s"l2_hitWay") 195 196 when (hit) { ptwl2replace.access(genPtwL2SetIdx(second_req.vpn), hitWay) } 197 198 l2AccessPerf.zip(hitVec).map{ case (l, h) => l := h && RegNext(first_fire) } 199 XSDebug(first_fire, p"[l2] ridx:0x${Hexadecimal(ridx)}\n") 200 for (i <- 0 until l2tlbParams.l2nWays) { 201 XSDebug(RegNext(first_fire), p"[l2] ramDatas(${i.U}) ${ramDatas(i)} l2v:${vidx(i)} hit:${ramDatas(i).entries.hit(second_req.vpn)}\n") 202 } 203 XSDebug(second_valid, p"[l2] l2Hit:${hit} l2HitPPN:0x${Hexadecimal(hitWayData.ppns(genPtwL2SectorIdx(second_req.vpn)))} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${Binary(vidx.asUInt)}\n") 204 205 (hit && !eccError, hitWayData.ppns(genPtwL2SectorIdx(second_req.vpn)), hitWayData.prefetch, hit && eccError) 206 } 207 208 // l3 209 val ptwl3replace = ReplacementPolicy.fromString(l2tlbParams.l3Replacer,l2tlbParams.l3nWays,l2tlbParams.l3nSets) 210 val (l3Hit, l3HitData, l3Pre, l3eccError) = { 211 val ridx = genPtwL3SetIdx(first_req.vpn) 212 val vidx = RegEnable(VecInit(getl3vSet(first_req.vpn).asBools), first_fire) 213 l3.io.r.req.valid := first_fire 214 l3.io.r.req.bits.apply(setIdx = ridx) 215 val ramDatas = l3.io.r.resp.data 216 val hitVec = VecInit(ramDatas.zip(vidx).map{ case (wayData, v) => wayData.entries.hit(second_req.vpn) && v }) 217 val hitWayEntry = ParallelPriorityMux(hitVec zip ramDatas) 218 val hitWayData = hitWayEntry.entries 219 val hitWayEcc = hitWayEntry.ecc 220 val hit = ParallelOR(hitVec) && cache_read_valid && RegNext(l3.io.r.req.ready, init = false.B) 221 val hitWay = ParallelPriorityMux(hitVec zip (0 until l2tlbParams.l3nWays).map(_.U)) 222 223 val eccError = ecc.decode(Cat(hitWayEcc, hitWayData.asUInt())).error 224 225 when (hit) { ptwl3replace.access(genPtwL3SetIdx(second_req.vpn), hitWay) } 226 227 l3AccessPerf.zip(hitVec).map{ case (l, h) => l := h && RegNext(first_fire) } 228 XSDebug(first_fire, p"[l3] ridx:0x${Hexadecimal(ridx)}\n") 229 for (i <- 0 until l2tlbParams.l3nWays) { 230 XSDebug(RegNext(first_fire), p"[l3] ramDatas(${i.U}) ${ramDatas(i)} l3v:${vidx(i)} hit:${ramDatas(i).entries.hit(second_req.vpn)}\n") 231 } 232 XSDebug(second_valid, p"[l3] l3Hit:${hit} l3HitData:${hitWayData} hitVec:${Binary(hitVec.asUInt)} hitWay:${hitWay} vidx:${Binary(vidx.asUInt)}\n") 233 234 ridx.suggestName(s"l3_ridx") 235 vidx.suggestName(s"l3_vidx") 236 ramDatas.suggestName(s"l3_ramDatas") 237 hitVec.suggestName(s"l3_hitVec") 238 hitWay.suggestName(s"l3_hitWay") 239 240 (hit && !eccError, hitWayData, hitWayData.prefetch, hit && eccError) 241 } 242 val l3HitPPN = l3HitData.ppns(genPtwL3SectorIdx(second_req.vpn)) 243 val l3HitPerm = l3HitData.perms.getOrElse(0.U.asTypeOf(Vec(PtwL3SectorSize, new PtePermBundle)))(genPtwL3SectorIdx(second_req.vpn)) 244 245 // super page 246 val spreplace = ReplacementPolicy.fromString(l2tlbParams.spReplacer, l2tlbParams.spSize) 247 val (spHit, spHitData, spPre) = { 248 val hitVecT = sp.zipWithIndex.map { case (e, i) => e.hit(first_req.vpn) && spv(i) } 249 val hitVec = hitVecT.map(RegEnable(_, first_fire)) 250 val hitData = ParallelPriorityMux(hitVec zip sp) 251 val hit = ParallelOR(hitVec) && cache_read_valid 252 253 when (hit) { spreplace.access(OHToUInt(hitVec)) } 254 255 spAccessPerf.zip(hitVec).map{ case (s, h) => s := h && RegNext(first_fire) } 256 for (i <- 0 until l2tlbParams.spSize) { 257 XSDebug(first_fire, p"[sp] sp(${i.U}) ${sp(i)} hit:${sp(i).hit(first_req.vpn)} spv:${spv(i)}\n") 258 } 259 XSDebug(second_valid, p"[sp] spHit:${hit} spHitData:${hitData} hitVec:${Binary(VecInit(hitVec).asUInt)}\n") 260 261 VecInit(hitVecT).suggestName(s"sp_hitVecT") 262 VecInit(hitVec).suggestName(s"sp_hitVec") 263 264 (hit, hitData, hitData.prefetch) 265 } 266 val spHitPerm = spHitData.perm.getOrElse(0.U.asTypeOf(new PtePermBundle)) 267 val spHitLevel = spHitData.level.getOrElse(0.U) 268 269 val resp = Wire(io.resp.bits.cloneType) 270 val resp_latch = RegEnable(resp, io.resp.valid && !io.resp.ready) 271 val resp_latch_valid = ValidHold(io.resp.valid && !io.resp.ready, io.resp.fire(), sfence.valid) 272 second_ready := !second_valid || io.resp.fire() 273 resp.source := second_req.source 274 resp.vpn := second_req.vpn 275 resp.hit := l3Hit || spHit 276 resp.prefetch := l3Pre && l3Hit || spPre && spHit 277 resp.toFsm.l1Hit := l1Hit 278 resp.toFsm.l2Hit := l2Hit 279 resp.toFsm.ppn := Mux(l2Hit, l2HitPPN, l1HitPPN) 280 resp.toTlb.tag := second_req.vpn 281 resp.toTlb.ppn := Mux(l3Hit, l3HitPPN, spHitData.ppn) 282 resp.toTlb.perm.map(_ := Mux(l3Hit, l3HitPerm, spHitPerm)) 283 resp.toTlb.level.map(_ := Mux(l3Hit, 2.U, spHitLevel)) 284 resp.toTlb.prefetch := from_pre(second_req.source) 285 286 io.resp.valid := second_valid 287 io.resp.bits := Mux(resp_latch_valid, resp_latch, resp) 288 assert(!(l3Hit && spHit), "normal page and super page both hit") 289 290 // refill Perf 291 val l1RefillPerf = Wire(Vec(l2tlbParams.l1Size, Bool())) 292 val l2RefillPerf = Wire(Vec(l2tlbParams.l2nWays, Bool())) 293 val l3RefillPerf = Wire(Vec(l2tlbParams.l3nWays, Bool())) 294 val spRefillPerf = Wire(Vec(l2tlbParams.spSize, Bool())) 295 l1RefillPerf.map(_ := false.B) 296 l2RefillPerf.map(_ := false.B) 297 l3RefillPerf.map(_ := false.B) 298 spRefillPerf.map(_ := false.B) 299 300 // refill 301 l2.io.w.req <> DontCare 302 l3.io.w.req <> DontCare 303 l2.io.w.req.valid := false.B 304 l3.io.w.req.valid := false.B 305 306 def get_part(data: UInt, index: UInt): UInt = { 307 val inner_data = data.asTypeOf(Vec(data.getWidth / XLEN, UInt(XLEN.W))) 308 inner_data(index) 309 } 310 311 val memRdata = refill.ptes 312 val memSelData = get_part(memRdata, refill.addr_low) 313 val memPtes = (0 until (l2tlbParams.blockBytes/(XLEN/8))).map(i => memRdata((i+1)*XLEN-1, i*XLEN).asTypeOf(new PteBundle)) 314 val memPte = memSelData.asTypeOf(new PteBundle) 315 316 memPte.suggestName("memPte") 317 318 // TODO: handle sfenceLatch outsize 319 when (io.refill.valid && !memPte.isPf(refill.level) && !sfence.valid ) { 320 when (refill.level === 0.U && !memPte.isLeaf()) { 321 // val refillIdx = LFSR64()(log2Up(l2tlbParams.l1Size)-1,0) // TODO: may be LRU 322 val refillIdx = replaceWrapper(l1v, ptwl1replace.way) 323 refillIdx.suggestName(s"PtwL1RefillIdx") 324 val rfOH = UIntToOH(refillIdx) 325 l1(refillIdx).refill(refill.vpn, memSelData, 0.U, refill.prefetch) 326 ptwl1replace.access(refillIdx) 327 l1v := l1v | rfOH 328 l1g := (l1g & ~rfOH) | Mux(memPte.perm.g, rfOH, 0.U) 329 330 for (i <- 0 until l2tlbParams.l1Size) { 331 l1RefillPerf(i) := i.U === refillIdx 332 } 333 334 XSDebug(p"[l1 refill] refillIdx:${refillIdx} refillEntry:${l1(refillIdx).genPtwEntry(refill.vpn, memSelData, 0.U, refill.prefetch)}\n") 335 XSDebug(p"[l1 refill] l1v:${Binary(l1v)}->${Binary(l1v | rfOH)} l1g:${Binary(l1g)}->${Binary((l1g & ~rfOH) | Mux(memPte.perm.g, rfOH, 0.U))}\n") 336 337 refillIdx.suggestName(s"l1_refillIdx") 338 rfOH.suggestName(s"l1_rfOH") 339 } 340 341 when (refill.level === 1.U && !memPte.isLeaf()) { 342 val refillIdx = genPtwL2SetIdx(refill.vpn) 343 val victimWay = replaceWrapper(RegEnable(VecInit(getl2vSet(refill.vpn).asBools).asUInt, first_fire), ptwl2replace.way(refillIdx)) 344 val victimWayOH = UIntToOH(victimWay) 345 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 346 val wdata = Wire(l2EntryType) 347 wdata.entries := wdata.entries.genEntries(vpn = refill.vpn, data = memRdata, levelUInt = 1.U, refill.prefetch) 348 wdata.ecc := ecc.encode(wdata.entries.asUInt()) >> wdata.entries.getWidth 349 l2.io.w.apply( 350 valid = true.B, 351 setIdx = refillIdx, 352 data = wdata, 353 waymask = victimWayOH 354 ) 355 ptwl2replace.access(refillIdx, victimWay) 356 l2v := l2v | rfvOH 357 l2g := l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 358 359 for (i <- 0 until l2tlbParams.l2nWays) { 360 l2RefillPerf(i) := i.U === victimWay 361 } 362 363 XSDebug(p"[l2 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 364 XSDebug(p"[l2 refill] refilldata:0x${ 365 (new PtwEntries(num = PtwL2SectorSize, tagLen = PtwL2TagLen, level = 1, hasPerm = false)).genEntries( 366 vpn = refill.vpn, data = memRdata, levelUInt = 1.U, refill.prefetch) 367 }\n") 368 XSDebug(p"[l2 refill] l2v:${Binary(l2v)} -> ${Binary(l2v | rfvOH)}\n") 369 XSDebug(p"[l2 refill] l2g:${Binary(l2g)} -> ${Binary(l2g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 370 371 refillIdx.suggestName(s"l2_refillIdx") 372 victimWay.suggestName(s"l2_victimWay") 373 victimWayOH.suggestName(s"l2_victimWayOH") 374 rfvOH.suggestName(s"l2_rfvOH") 375 } 376 377 when (refill.level === 2.U && memPte.isLeaf()) { 378 val refillIdx = genPtwL3SetIdx(refill.vpn) 379 val victimWay = replaceWrapper(RegEnable(VecInit(getl3vSet(refill.vpn).asBools).asUInt, first_fire), ptwl3replace.way(refillIdx)) 380 val victimWayOH = UIntToOH(victimWay) 381 val rfvOH = UIntToOH(Cat(refillIdx, victimWay)) 382 val wdata = Wire(l3EntryType) 383 wdata.entries := wdata.entries.genEntries(vpn = refill.vpn, data = memRdata, levelUInt = 2.U, refill.prefetch) 384 wdata.ecc := ecc.encode(wdata.entries.asUInt()) >> wdata.entries.getWidth 385 l3.io.w.apply( 386 valid = true.B, 387 setIdx = refillIdx, 388 data = wdata, 389 waymask = victimWayOH 390 ) 391 ptwl3replace.access(refillIdx, victimWay) 392 l3v := l3v | rfvOH 393 l3g := l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U) 394 395 for (i <- 0 until l2tlbParams.l3nWays) { 396 l3RefillPerf(i) := i.U === victimWay 397 } 398 399 XSDebug(p"[l3 refill] refillIdx:0x${Hexadecimal(refillIdx)} victimWay:${victimWay} victimWayOH:${Binary(victimWayOH)} rfvOH(in UInt):${Cat(refillIdx, victimWay)}\n") 400 XSDebug(p"[l3 refill] refilldata:0x${ 401 (new PtwEntries(num = PtwL3SectorSize, tagLen = PtwL3TagLen, level = 2, hasPerm = true)).genEntries( 402 vpn = refill.vpn, data = memRdata, levelUInt = 2.U, refill.prefetch) 403 }\n") 404 XSDebug(p"[l3 refill] l3v:${Binary(l3v)} -> ${Binary(l3v | rfvOH)}\n") 405 XSDebug(p"[l3 refill] l3g:${Binary(l3g)} -> ${Binary(l3g & ~rfvOH | Mux(Cat(memPtes.map(_.perm.g)).andR, rfvOH, 0.U))}\n") 406 407 refillIdx.suggestName(s"l3_refillIdx") 408 victimWay.suggestName(s"l3_victimWay") 409 victimWayOH.suggestName(s"l3_victimWayOH") 410 rfvOH.suggestName(s"l3_rfvOH") 411 } 412 when ((refill.level === 0.U || refill.level === 1.U) && memPte.isLeaf()) { 413 val refillIdx = spreplace.way// LFSR64()(log2Up(l2tlbParams.spSize)-1,0) // TODO: may be LRU 414 val rfOH = UIntToOH(refillIdx) 415 sp(refillIdx).refill(refill.vpn, memSelData, refill.level, refill.prefetch) 416 spreplace.access(refillIdx) 417 spv := spv | rfOH 418 spg := spg & ~rfOH | Mux(memPte.perm.g, rfOH, 0.U) 419 420 for (i <- 0 until l2tlbParams.spSize) { 421 spRefillPerf(i) := i.U === refillIdx 422 } 423 424 XSDebug(p"[sp refill] refillIdx:${refillIdx} refillEntry:${sp(refillIdx).genPtwEntry(refill.vpn, memSelData, refill.level, refill.prefetch)}\n") 425 XSDebug(p"[sp refill] spv:${Binary(spv)}->${Binary(spv | rfOH)} spg:${Binary(spg)}->${Binary(spg & ~rfOH | Mux(memPte.perm.g, rfOH, 0.U))}\n") 426 427 refillIdx.suggestName(s"sp_refillIdx") 428 rfOH.suggestName(s"sp_rfOH") 429 } 430 } 431 432 val l2eccFlush = RegNext(l2eccError, init = false.B) 433 val l3eccFlush = RegNext(l3eccError, init = false.B) 434 val eccVpn = RegNext(second_req.vpn) 435 436 assert(!l2eccFlush) 437 assert(!l3eccFlush) 438 when (l2eccFlush) { 439 val flushSetIdxOH = UIntToOH(genPtwL2SetIdx(eccVpn)) 440 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l2nWays, a.asUInt) }).asUInt 441 l2v := l2v & ~flushMask 442 l2g := l2g & ~flushMask 443 } 444 445 when (l3eccFlush) { 446 val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(eccVpn)) 447 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt 448 l3v := l3v & ~flushMask 449 l3g := l3g & ~flushMask 450 } 451 452 // sfence 453 when (sfence.valid) { 454 when (sfence.bits.rs1/*va*/) { 455 when (sfence.bits.rs2) { 456 // all va && all asid 457 l1v := 0.U 458 l2v := 0.U 459 l3v := 0.U 460 spv := 0.U 461 } .otherwise { 462 // all va && specific asid except global 463 l1v := l1v & l1g 464 l2v := l2v & l2g 465 l3v := l3v & l3g 466 spv := spv & spg 467 } 468 } .otherwise { 469 // val flushMask = UIntToOH(genTlbL2Idx(sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen))) 470 val flushSetIdxOH = UIntToOH(genPtwL3SetIdx(sfence.bits.addr(sfence.bits.addr.getWidth-1, offLen))) 471 // val flushMask = VecInit(flushSetIdxOH.asBools.map(Fill(l2tlbParams.l3nWays, _.asUInt))).asUInt 472 val flushMask = VecInit(flushSetIdxOH.asBools.map { a => Fill(l2tlbParams.l3nWays, a.asUInt) }).asUInt 473 flushSetIdxOH.suggestName(s"sfence_nrs1_flushSetIdxOH") 474 flushMask.suggestName(s"sfence_nrs1_flushMask") 475 when (sfence.bits.rs2) { 476 // specific leaf of addr && all asid 477 l3v := l3v & ~flushMask 478 l3g := l3g & ~flushMask 479 } .otherwise { 480 // specific leaf of addr && specific asid 481 l3v := l3v & (~flushMask | l3g) 482 } 483 spv := 0.U 484 } 485 } 486 487 // Perf Count 488 val resp_l3 = DataHoldBypass(l3Hit, io.resp.valid && !resp_latch_valid).asBool() 489 val resp_sp = DataHoldBypass(spHit, io.resp.valid && !resp_latch_valid).asBool() 490 val resp_l1_pre = DataHoldBypass(l1Pre, io.resp.valid && !resp_latch_valid).asBool() 491 val resp_l2_pre = DataHoldBypass(l2Pre, io.resp.valid && !resp_latch_valid).asBool() 492 val resp_l3_pre = DataHoldBypass(l3Pre, io.resp.valid && !resp_latch_valid).asBool() 493 val resp_sp_pre = DataHoldBypass(spPre, io.resp.valid && !resp_latch_valid).asBool() 494 val base_valid_access_0 = !from_pre(io.resp.bits.source) && io.resp.fire() 495 XSPerfAccumulate("access", base_valid_access_0) 496 XSPerfAccumulate("l1_hit", base_valid_access_0 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 497 XSPerfAccumulate("l2_hit", base_valid_access_0 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 498 XSPerfAccumulate("l3_hit", base_valid_access_0 && resp_l3) 499 XSPerfAccumulate("sp_hit", base_valid_access_0 && resp_sp) 500 XSPerfAccumulate("pte_hit",base_valid_access_0 && io.resp.bits.hit) 501 502 XSPerfAccumulate("l1_hit_pre", base_valid_access_0 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 503 XSPerfAccumulate("l2_hit_pre", base_valid_access_0 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 504 XSPerfAccumulate("l3_hit_pre", base_valid_access_0 && resp_l3_pre && resp_l3) 505 XSPerfAccumulate("sp_hit_pre", base_valid_access_0 && resp_sp_pre && resp_sp) 506 XSPerfAccumulate("pte_hit_pre",base_valid_access_0 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 507 508 val base_valid_access_1 = from_pre(io.resp.bits.source) && io.resp.fire() 509 XSPerfAccumulate("pre_access", base_valid_access_1) 510 XSPerfAccumulate("pre_l1_hit", base_valid_access_1 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 511 XSPerfAccumulate("pre_l2_hit", base_valid_access_1 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 512 XSPerfAccumulate("pre_l3_hit", base_valid_access_1 && resp_l3) 513 XSPerfAccumulate("pre_sp_hit", base_valid_access_1 && resp_sp) 514 XSPerfAccumulate("pre_pte_hit",base_valid_access_1 && io.resp.bits.hit) 515 516 XSPerfAccumulate("pre_l1_hit_pre", base_valid_access_1 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 517 XSPerfAccumulate("pre_l2_hit_pre", base_valid_access_1 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 518 XSPerfAccumulate("pre_l3_hit_pre", base_valid_access_1 && resp_l3_pre && resp_l3) 519 XSPerfAccumulate("pre_sp_hit_pre", base_valid_access_1 && resp_sp_pre && resp_sp) 520 XSPerfAccumulate("pre_pte_hit_pre",base_valid_access_1 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 521 522 val base_valid_access_2 = second_isFirst && !from_pre(io.resp.bits.source) && io.resp.fire() 523 XSPerfAccumulate("access_first", base_valid_access_2) 524 XSPerfAccumulate("l1_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 525 XSPerfAccumulate("l2_hit_first", base_valid_access_2 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 526 XSPerfAccumulate("l3_hit_first", base_valid_access_2 && resp_l3) 527 XSPerfAccumulate("sp_hit_first", base_valid_access_2 && resp_sp) 528 XSPerfAccumulate("pte_hit_first",base_valid_access_2 && io.resp.bits.hit) 529 530 XSPerfAccumulate("l1_hit_pre_first", base_valid_access_2 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 531 XSPerfAccumulate("l2_hit_pre_first", base_valid_access_2 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 532 XSPerfAccumulate("l3_hit_pre_first", base_valid_access_2 && resp_l3_pre && resp_l3) 533 XSPerfAccumulate("sp_hit_pre_first", base_valid_access_2 && resp_sp_pre && resp_sp) 534 XSPerfAccumulate("pte_hit_pre_first",base_valid_access_2 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 535 536 val base_valid_access_3 = second_isFirst && from_pre(io.resp.bits.source) && io.resp.fire() 537 XSPerfAccumulate("pre_access_first", base_valid_access_3) 538 XSPerfAccumulate("pre_l1_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 539 XSPerfAccumulate("pre_l2_hit_first", base_valid_access_3 && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 540 XSPerfAccumulate("pre_l3_hit_first", base_valid_access_3 && resp_l3) 541 XSPerfAccumulate("pre_sp_hit_first", base_valid_access_3 && resp_sp) 542 XSPerfAccumulate("pre_pte_hit_first", base_valid_access_3 && io.resp.bits.hit) 543 544 XSPerfAccumulate("pre_l1_hit_pre_first", base_valid_access_3 && resp_l1_pre && io.resp.bits.toFsm.l1Hit && !io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 545 XSPerfAccumulate("pre_l2_hit_pre_first", base_valid_access_3 && resp_l2_pre && io.resp.bits.toFsm.l2Hit && !io.resp.bits.hit) 546 XSPerfAccumulate("pre_l3_hit_pre_first", base_valid_access_3 && resp_l3_pre && resp_l3) 547 XSPerfAccumulate("pre_sp_hit_pre_first", base_valid_access_3 && resp_sp_pre && resp_sp) 548 XSPerfAccumulate("pre_pte_hit_pre_first",base_valid_access_3 && (resp_l3_pre && resp_l3 || resp_sp_pre && resp_sp) && io.resp.bits.hit) 549 550 XSPerfAccumulate("rwHarzad", io.req.valid && !io.req.ready) 551 XSPerfAccumulate("out_blocked", io.resp.valid && !io.resp.ready) 552 l1AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1AccessIndex${i}", l) } 553 l2AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2AccessIndex${i}", l) } 554 l3AccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3AccessIndex${i}", l) } 555 spAccessPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPAccessIndex${i}", l) } 556 l1RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L1RefillIndex${i}", l) } 557 l2RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L2RefillIndex${i}", l) } 558 l3RefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"L3RefillIndex${i}", l) } 559 spRefillPerf.zipWithIndex.map{ case (l, i) => XSPerfAccumulate(s"SPRefillIndex${i}", l) } 560 561 XSPerfAccumulate("l1Refill", Cat(l1RefillPerf).orR) 562 XSPerfAccumulate("l2Refill", Cat(l2RefillPerf).orR) 563 XSPerfAccumulate("l3Refill", Cat(l3RefillPerf).orR) 564 XSPerfAccumulate("spRefill", Cat(spRefillPerf).orR) 565 XSPerfAccumulate("l1Refill_pre", Cat(l1RefillPerf).orR && refill.prefetch) 566 XSPerfAccumulate("l2Refill_pre", Cat(l2RefillPerf).orR && refill.prefetch) 567 XSPerfAccumulate("l3Refill_pre", Cat(l3RefillPerf).orR && refill.prefetch) 568 XSPerfAccumulate("spRefill_pre", Cat(spRefillPerf).orR && refill.prefetch) 569 570 // debug 571 XSDebug(sfence.valid, p"[sfence] original v and g vector:\n") 572 XSDebug(sfence.valid, p"[sfence] l1v:${Binary(l1v)}\n") 573 XSDebug(sfence.valid, p"[sfence] l2v:${Binary(l2v)}\n") 574 XSDebug(sfence.valid, p"[sfence] l3v:${Binary(l3v)}\n") 575 XSDebug(sfence.valid, p"[sfence] l3g:${Binary(l3g)}\n") 576 XSDebug(sfence.valid, p"[sfence] spv:${Binary(spv)}\n") 577 XSDebug(RegNext(sfence.valid), p"[sfence] new v and g vector:\n") 578 XSDebug(RegNext(sfence.valid), p"[sfence] l1v:${Binary(l1v)}\n") 579 XSDebug(RegNext(sfence.valid), p"[sfence] l2v:${Binary(l2v)}\n") 580 XSDebug(RegNext(sfence.valid), p"[sfence] l3v:${Binary(l3v)}\n") 581 XSDebug(RegNext(sfence.valid), p"[sfence] l3g:${Binary(l3g)}\n") 582 XSDebug(RegNext(sfence.valid), p"[sfence] spv:${Binary(spv)}\n") 583} 584