fix(PTWCache): hfence_gvma should ignore g bit (#4539)

In "RISC-V Instruction Set Manual: Volume II: Privileged Architecture":
The G bit in all G-stage PTEs is reserved for future standard use. Unti

fix(PTWCache): hfence_gvma should ignore g bit (#4539)

In "RISC-V Instruction Set Manual: Volume II: Privileged Architecture":
The G bit in all G-stage PTEs is reserved for future standard use. Until
its use is defined by a standard extension, it should be cleared by
software for forward compatibility, and must be ignored by hardware.

Co-authored-by: SpecialWeeks <[email protected]>

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feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

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fix(PTWCache): length of PPN should be gvpnLen when hypervisor (#4453)

ppnLen: PaddrBits - Offset = 48 - 12 = 36
gvpnLen: GVaddrBits - Offset = 50 (Sv48x4) - 12 = 38

When hypervisor extension imple

fix(PTWCache): length of PPN should be gvpnLen when hypervisor (#4453)

ppnLen: PaddrBits - Offset = 48 - 12 = 36
gvpnLen: GVaddrBits - Offset = 50 (Sv48x4) - 12 = 38

When hypervisor extension implemented, PPN length should be gvpnLen
rather than ppnLen

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fix(MMU): Stage1Gpf should use hgatp instead of vsatp (#4448)

feat(PTWCache): Support a more precise flush for L2 TLB entries (#4390)

In the previous design, since we stored asid/vmid and vaddr information
in SRAM, it was not possible to simply read out all th

feat(PTWCache): Support a more precise flush for L2 TLB entries (#4390)

In the previous design, since we stored asid/vmid and vaddr information
in SRAM, it was not possible to simply read out all the information in a
single cycle for comparison with the parameters of sfence/hfence. As a
result, for L2 TLB entries, we ignored the rs1/rs2 parameters passed by
sfence/hfence and instead flushed all valid entries, regardless of
asid/vmid or vaddr.

However, this caused unnecessary flushing of a large number of entries
during process switching in virtualized environments, leading to L2 TLB
misses after a process switch. This forced the processor to perform a
page table walk in memory again, negatively impacting performance.

In this commit, asid/vmid and vaddr are hashed and stored in the
register file. When an sfence/hfence signal is received, these stored
values are compared against the incoming parameters, allowing for a more
precise TLB flush.

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feat(dfx): integerate dfx components (#4312)

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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fix(PageTableCache): transfer pbmt in l3 (#4231)

fix(PTWCache): avoid X-prop of spRefill (#4195)

In the previous design, the `spRefill` signal will be true when the
`refill.levelOH.sp` or `memPte(0).isNapot(refill.level_dup(0))`
conditions is me

fix(PTWCache): avoid X-prop of spRefill (#4195)

In the previous design, the `spRefill` signal will be true when the
`refill.levelOH.sp` or `memPte(0).isNapot(refill.level_dup(0))`
conditions is met, and acted as a control signal to control the refill
of the sp entries. However, `memPte(0).isNapot(refill.level_dup(0))`
does not determine whether `refill.level_dup(0)` is valid. When
`refill.level_dup(0)` is X, it causes `spRefill` to also be X, which in
turn causes X-prop.

This commit adds `refill.levelOH.l0` to `isNapot`. On the one hand, only
`levelOH.l0` (4KB page) can be a Svnapot page; on the other hand, the
assignment of `refill.levelOH.l0` takes `refill.valid` into account,
thus avoiding X-prop.

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feat(Svnapot): support Svnapot extension (#4107)

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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area(PTWCache): reduce l2tlb entries from 2k to 1k (#4003)

Previous design: l0 32 sets * 8 ways * 8 entries = 2048; l1 8 sets * 4 ways * 8 entries = 512

Modified: l0 32 sets * 4 ways * 8 entries

area(PTWCache): reduce l2tlb entries from 2k to 1k (#4003)

Previous design: l0 32 sets * 8 ways * 8 entries = 2048; l1 8 sets * 4 ways * 8 entries = 512

Modified: l0 32 sets * 4 ways * 8 entries = 1024; l1 8 sets * 2 ways * 8 entries = 256

Performance drops by 0.09% in spec06 with 0.3 coverage.

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fix(HPM): fix PTW perfevent print error, organize the code format of some perfevents (#3890)

`getperfevent` retrieves both the `name` and `value` fields, whereas
`getperf` only retrieves the `value

fix(HPM): fix PTW perfevent print error, organize the code format of some perfevents (#3890)

`getperfevent` retrieves both the `name` and `value` fields, whereas
`getperf` only retrieves the `value` port. The original implementation
caused all perf event information for PTW to be printed as
`perfEventsPTW`, making them indistinguishable.

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power(MemBlock): add ClockGate for DCache SRAM (#3824)

By using ClockGate for DCache SRAM, memory Power has 64% reduction,
MemBlock total power has 23.38% reduction.

fix(PageTableCache): fix hit & bypass logic when onlypf (#3625)

fix(PageTableCache): fix ptwcache refill logic when exception (#3588)

Since L2 Cache access width is 512 bits, 8 PTE items are refilled into
page cache together. In previous design, when an excepti

fix(PageTableCache): fix ptwcache refill logic when exception (#3588)

Since L2 Cache access width is 512 bits, 8 PTE items are refilled into
page cache together. In previous design, when an exception occurs in one
of the 8 refilled PTE entries, none of the 8 entries will be refilled.
In this case, if there is a normal entry in one of the 8 neighbouring
page tables, it will not be refillled because of the exception in the
other entries, which will lead to blocking.

This commit fixes this problem. `vs` means that if one of the 8
consecutive page tables has an exception, the corresponding `vs` will be
forced to be false when judging hit. `onlypf` means that if x2slate is
not enabled, and only pf occurs, then the pf information will be
returned. Except for the onlypf case, the rest of the exceptions will
not be refilled in page cache (none of them will hit).

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fix(L2TLB): Fix exception generation logic (#3453)

* fix(L2TLB): Fix exception generation logic

We may currently generate three types of exceptions, pf, gpf, and af.
There must be only one type

fix(L2TLB): Fix exception generation logic (#3453)

* fix(L2TLB): Fix exception generation logic

We may currently generate three types of exceptions, pf, gpf, and af.
There must be only one type of exception that should occur in each resp
returned by L2 TLB, which is the type of exception that occurs for the
first time during the PTW process. Among them
pf & gpf: the two cases correspond to stage1 and stage2 respectively.
**In our previous design, the error is that onlyStage1 is also
considered to need gpf checking, but in fact, onlyStage1 shouldn't
report gpf.**
af: there are two kinds of access faults, the first one is the access
fault obtained by querying pmp before PTW accesses the memory, and the
second one is the access fault obtained by the PPN high level of page
table is not 0 after PTW accesses the memory. we call these two kinds of
access faults as pmp_af and ppn_af respectively.

For allStage case: pf, gpf, af can happen. pf precedes gpf (if pf is
reported in the first stage, it should be returned directly without
checking gpf in the second stage). For af, if it's pmp_af, this af will
be reported before actually accessing memory, and will have a higher
priority than pf or gpf (actually, if pmp_af occurs, no memory will be
accessed, and there will not be a pf or gpf at the same time). In case
of ppn_af, this af should actually be checked in pmp before being
reported before using this physical address for fetch or access.
However, since our physical address will be truncated directly on
return, we need to check the af in advance, and this af will have the
lowest priority and will be lower than pf | gpf. (i.e., pf and gpf will
not occur at the same time, pf > gpf. The two kinds of pf and pmp_af
will not occur at the same time, but may occur at the same time as
ppn_af, pmp_af > {pf or gpf} > ppn_af).

For onlyStage1: only pf or af will appear, same as above.
For onlyStage2: only gpf or af will appear, same as above.
For noS2xlate: only pf or af will appear, same as above.

* fix(L2TLB): prevent L1 PTEs with PPN AF to be refilled into
PageTableCache

L0 and L1 of PageTableCache caches 8 PTEs at once. When any of 8 PTEs
have a PPN with non-zero high bits, all 8 PTEs should not be refilled
into PageTableCache. Also, GPF refill filter is moved to vs generator.

* fix(L2TLB): block L2/L3 PTEs with PPN AF to be refilled

For onlyStage2, any PTE with non-zero high bits should not be refilled
into PageTableCache.

* fix(HPTW): incorrect priority of different kinds of AF and PF

In HTPW, there is 3 kinds of AF/PF:
- accessFault: PMP check failed when accessing THIS level PTE
- pageFault: this level PTE is not valid, such as v =0.
- ppn_af: the high bits of the PPN in this level PTE is not zero, which
means accessing NEXT level PTE will raise accessFault.

The priority of the above three is accessFault > pageFault > ppn_af.
This patch ensured this.

---------

Co-authored-by: Xu, Zefan <[email protected]>

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feat(pbmt): support PBMTE in MMU (#3521)

Co-authored-by: Xuan Hu <[email protected]>

feat(PTWCache): split Page Cache SRAM (#3503)

l0: 32 * 3624 -> 32 * (16 * 228), fill 24 reserved bits
waySplit = 4, dataSplit = 4
l1: 8 * 1560 -> 8 * (8 * 200), fill 40 reserved bits
wayS

feat(PTWCache): split Page Cache SRAM (#3503)

l0: 32 * 3624 -> 32 * (16 * 228), fill 24 reserved bits
waySplit = 4, dataSplit = 4
l1: 8 * 1560 -> 8 * (8 * 200), fill 40 reserved bits
waySplit = 2, dataSplit = 4

also, minimalconfig need different reservedBits (for l0 and l1, 0 & 1),
just for requirement in SplittedSRAM.

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PTW, RVH: add the sv48 high gpaddr check (#3427)

svpbmt: add simplified support (#3404)

Only the `pbmt` attribute is added and treated as MMIO when `pbmt` is NC
or IO.

---------

Co-authored-by: ngc7331 <[email protected]>

MMU, RVH: fix the refill of pte that has gpf and change the check of pf/gpf in PTW and HPTW (#3420)

1. gpf pte shouldn't be refilled in page cache
2. In stage2, U bit should be valid when pte is le

MMU, RVH: fix the refill of pte that has gpf and change the check of pf/gpf in PTW and HPTW (#3420)

1. gpf pte shouldn't be refilled in page cache
2. In stage2, U bit should be valid when pte is leaf
3. rewrite the check of pf and gpf in PTW and HPTW

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MMU, RVH: add the check of gpaddr high bits and fix some bugs (#3348)

RVA23: Support Sv48 & Sv48x4 (#3406)

Co-authored-by: Xuan Hu <[email protected]>

MMU, RVH, fix the af refill error when refilling page cache (#3331)