1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, MicroBTB, RAS, Tage, ITTage, Tage_SC} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import scala.math.min 34 35case object XSTileKey extends Field[Seq[XSCoreParameters]] 36 37case object XSCoreParamsKey extends Field[XSCoreParameters] 38 39case class XSCoreParameters 40( 41 HasPrefetch: Boolean = false, 42 HartId: Int = 0, 43 XLEN: Int = 64, 44 HasMExtension: Boolean = true, 45 HasCExtension: Boolean = true, 46 HasDiv: Boolean = true, 47 HasICache: Boolean = true, 48 HasDCache: Boolean = true, 49 AddrBits: Int = 64, 50 VAddrBits: Int = 39, 51 HasFPU: Boolean = true, 52 HasCustomCSRCacheOp: Boolean = true, 53 FetchWidth: Int = 8, 54 AsidLength: Int = 16, 55 EnableBPU: Boolean = true, 56 EnableBPD: Boolean = true, 57 EnableRAS: Boolean = true, 58 EnableLB: Boolean = false, 59 EnableLoop: Boolean = true, 60 EnableSC: Boolean = true, 61 EnbaleTlbDebug: Boolean = false, 62 EnableJal: Boolean = false, 63 EnableUBTB: Boolean = true, 64 HistoryLength: Int = 256, 65 PathHistoryLength: Int = 16, 66 BtbSize: Int = 2048, 67 JbtacSize: Int = 1024, 68 JbtacBanks: Int = 8, 69 RasSize: Int = 32, 70 CacheLineSize: Int = 512, 71 UBtbWays: Int = 16, 72 BtbWays: Int = 2, 73 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 74 // Sets Hist Tag 75 Seq(( 128*8, 2, 7), 76 ( 128*8, 4, 7), 77 ( 256*8, 8, 8), 78 ( 256*8, 16, 8), 79 ( 128*8, 32, 9), 80 ( 128*8, 65, 9)), 81 TageBanks: Int = 2, 82 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 83 // Sets Hist Tag 84 Seq(( 512, 0, 0), 85 ( 256, 4, 8), 86 ( 256, 8, 8), 87 ( 512, 12, 8), 88 ( 512, 16, 8), 89 ( 512, 32, 8)), 90 SCNRows: Int = 1024, 91 SCNTables: Int = 6, 92 SCCtrBits: Int = 6, 93 numBr: Int = 2, 94 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 95 ((resp_in: BranchPredictionResp, p: Parameters) => { 96 // val loop = Module(new LoopPredictor) 97 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 98 // else Module(new Tage) } 99 // else { Module(new FakeTage) }) 100 val ftb = Module(new FTB()(p)) 101 val ubtb = Module(new MicroBTB()(p)) 102 val bim = Module(new BIM()(p)) 103 val tage = Module(new Tage_SC()(p)) 104 val ras = Module(new RAS()(p)) 105 val ittage = Module(new ITTage()(p)) 106 // val tage = Module(new Tage()(p)) 107 // val fake = Module(new FakePredictor()(p)) 108 109 // val preds = Seq(loop, tage, btb, ubtb, bim) 110 val preds = Seq(bim, ubtb, tage, ftb, ittage, ras) 111 preds.map(_.io := DontCare) 112 113 // ubtb.io.resp_in(0) := resp_in 114 // bim.io.resp_in(0) := ubtb.io.resp 115 // btb.io.resp_in(0) := bim.io.resp 116 // tage.io.resp_in(0) := btb.io.resp 117 // loop.io.resp_in(0) := tage.io.resp 118 bim.io.in.bits.resp_in(0) := resp_in 119 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 120 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 121 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 122 ittage.io.in.bits.resp_in(0) := ftb.io.out.resp 123 ras.io.in.bits.resp_in(0) := ittage.io.out.resp 124 125 (preds, ras.io.out.resp) 126 }), 127 IBufSize: Int = 48, 128 DecodeWidth: Int = 6, 129 RenameWidth: Int = 6, 130 CommitWidth: Int = 6, 131 FtqSize: Int = 64, 132 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 133 IssQueSize: Int = 16, 134 NRPhyRegs: Int = 192, 135 LoadQueueSize: Int = 80, 136 StoreQueueSize: Int = 64, 137 RobSize: Int = 256, 138 dpParams: DispatchParameters = DispatchParameters( 139 IntDqSize = 16, 140 FpDqSize = 16, 141 LsDqSize = 16, 142 IntDqDeqWidth = 4, 143 FpDqDeqWidth = 4, 144 LsDqDeqWidth = 4 145 ), 146 exuParameters: ExuParameters = ExuParameters( 147 JmpCnt = 1, 148 AluCnt = 4, 149 MulCnt = 0, 150 MduCnt = 2, 151 FmacCnt = 4, 152 FmiscCnt = 2, 153 FmiscDivSqrtCnt = 0, 154 LduCnt = 2, 155 StuCnt = 2 156 ), 157 LoadPipelineWidth: Int = 2, 158 StorePipelineWidth: Int = 2, 159 StoreBufferSize: Int = 16, 160 StoreBufferThreshold: Int = 7, 161 EnableLoadToLoadForward: Boolean = false, 162 EnableFastForward: Boolean = false, 163 EnableLdVioCheckAfterReset: Boolean = true, 164 RefillSize: Int = 512, 165 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 166 itlbParameters: TLBParameters = TLBParameters( 167 name = "itlb", 168 fetchi = true, 169 useDmode = false, 170 sameCycle = true, 171 normalNWays = 32, 172 normalReplacer = Some("plru"), 173 superNWays = 4, 174 superReplacer = Some("plru"), 175 shouldBlock = true 176 ), 177 ldtlbParameters: TLBParameters = TLBParameters( 178 name = "ldtlb", 179 normalNSets = 128, 180 normalNWays = 1, 181 normalAssociative = "sa", 182 normalReplacer = Some("setplru"), 183 superNWays = 8, 184 normalAsVictim = true, 185 outReplace = true, 186 saveLevel = true 187 ), 188 sttlbParameters: TLBParameters = TLBParameters( 189 name = "sttlb", 190 normalNSets = 128, 191 normalNWays = 1, 192 normalAssociative = "sa", 193 normalReplacer = Some("setplru"), 194 superNWays = 8, 195 normalAsVictim = true, 196 outReplace = true, 197 saveLevel = true 198 ), 199 refillBothTlb: Boolean = false, 200 btlbParameters: TLBParameters = TLBParameters( 201 name = "btlb", 202 normalNSets = 1, 203 normalNWays = 64, 204 superNWays = 4, 205 ), 206 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 207 NumPerfCounters: Int = 16, 208 icacheParameters: ICacheParameters = ICacheParameters( 209 tagECC = Some("parity"), 210 dataECC = Some("parity"), 211 replacer = Some("setplru"), 212 nMissEntries = 2, 213 nReleaseEntries = 2 214 ), 215 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 216 tagECC = Some("secded"), 217 dataECC = Some("secded"), 218 replacer = Some("setplru"), 219 nMissEntries = 16, 220 nProbeEntries = 8, 221 nReleaseEntries = 18 222 )), 223 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 224 name = "l2", 225 level = 2, 226 ways = 8, 227 sets = 1024, // default 512KB L2 228 prefetch = Some(huancun.prefetch.BOPParameters()) 229 )), 230 L2NBanks: Int = 1, 231 usePTWRepeater: Boolean = false, 232 softPTW: Boolean = false // dpi-c debug only 233){ 234 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 235 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 236 237 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 238 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 239 240 val fpExuConfigs = 241 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 242 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 243 244 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 245} 246 247case object DebugOptionsKey extends Field[DebugOptions] 248 249case class DebugOptions 250( 251 FPGAPlatform: Boolean = false, 252 EnableDifftest: Boolean = false, 253 AlwaysBasicDiff: Boolean = true, 254 EnableDebug: Boolean = false, 255 EnablePerfDebug: Boolean = true, 256 UseDRAMSim: Boolean = false 257) 258 259trait HasXSParameter { 260 261 implicit val p: Parameters 262 263 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 264 265 val coreParams = p(XSCoreParamsKey) 266 val env = p(DebugOptionsKey) 267 268 val XLEN = coreParams.XLEN 269 val minFLen = 32 270 val fLen = 64 271 def xLen = XLEN 272 273 val HasMExtension = coreParams.HasMExtension 274 val HasCExtension = coreParams.HasCExtension 275 val HasDiv = coreParams.HasDiv 276 val HasIcache = coreParams.HasICache 277 val HasDcache = coreParams.HasDCache 278 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 279 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 280 val AsidLength = coreParams.AsidLength 281 val AddrBytes = AddrBits / 8 // unused 282 val DataBits = XLEN 283 val DataBytes = DataBits / 8 284 val HasFPU = coreParams.HasFPU 285 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 286 val FetchWidth = coreParams.FetchWidth 287 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 288 val EnableBPU = coreParams.EnableBPU 289 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 290 val EnableRAS = coreParams.EnableRAS 291 val EnableLB = coreParams.EnableLB 292 val EnableLoop = coreParams.EnableLoop 293 val EnableSC = coreParams.EnableSC 294 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 295 val HistoryLength = coreParams.HistoryLength 296 val PathHistoryLength = coreParams.PathHistoryLength 297 val BtbSize = coreParams.BtbSize 298 // val BtbWays = 4 299 val BtbBanks = PredictWidth 300 // val BtbSets = BtbSize / BtbWays 301 val JbtacSize = coreParams.JbtacSize 302 val JbtacBanks = coreParams.JbtacBanks 303 val RasSize = coreParams.RasSize 304 305 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 306 coreParams.branchPredictor(resp_in, p) 307 } 308 val numBr = coreParams.numBr 309 val TageTableInfos = coreParams.TageTableInfos 310 311 312 val BankTageTableInfos = (0 until numBr).map(i => 313 TageTableInfos.map{ case (s, h, t) => (s/(1 << i), h, t) } 314 ) 315 val TageBanks = coreParams.TageBanks 316 val SCNRows = coreParams.SCNRows 317 val SCCtrBits = coreParams.SCCtrBits 318 val BankSCHistLens = BankTageTableInfos.map(info => 0 :: info.map{ case (_,h,_) => h}.toList) 319 val BankSCNTables = Seq.fill(numBr)(coreParams.SCNTables) 320 321 val BankSCTableInfos = (BankSCNTables zip BankSCHistLens).map { 322 case (ntable, histlens) => 323 Seq.fill(ntable)((SCNRows, SCCtrBits)) zip histlens map {case ((n, cb), h) => (n, cb, h)} 324 } 325 val ITTageTableInfos = coreParams.ITTageTableInfos 326 type FoldedHistoryInfo = Tuple2[Int, Int] 327 val foldedGHistInfos = 328 (BankTageTableInfos.flatMap(_.map{ case (nRows, h, t) => 329 if (h > 0) 330 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 331 else 332 Set[FoldedHistoryInfo]() 333 }.reduce(_++_)).toSet ++ 334 BankSCTableInfos.flatMap(_.map{ case (nRows, _, h) => 335 if (h > 0) 336 Set((h, min(log2Ceil(nRows/TageBanks), h))) 337 else 338 Set[FoldedHistoryInfo]() 339 }.reduce(_++_)).toSet ++ 340 ITTageTableInfos.map{ case (nRows, h, t) => 341 if (h > 0) 342 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 343 else 344 Set[FoldedHistoryInfo]() 345 }.reduce(_++_)).toList 346 347 val CacheLineSize = coreParams.CacheLineSize 348 val CacheLineHalfWord = CacheLineSize / 16 349 val ExtHistoryLength = HistoryLength + 64 350 val UBtbWays = coreParams.UBtbWays 351 val BtbWays = coreParams.BtbWays 352 val IBufSize = coreParams.IBufSize 353 val DecodeWidth = coreParams.DecodeWidth 354 val RenameWidth = coreParams.RenameWidth 355 val CommitWidth = coreParams.CommitWidth 356 val FtqSize = coreParams.FtqSize 357 val IssQueSize = coreParams.IssQueSize 358 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 359 val NRPhyRegs = coreParams.NRPhyRegs 360 val PhyRegIdxWidth = log2Up(NRPhyRegs) 361 val RobSize = coreParams.RobSize 362 val IntRefCounterWidth = log2Ceil(RobSize) 363 val LoadQueueSize = coreParams.LoadQueueSize 364 val StoreQueueSize = coreParams.StoreQueueSize 365 val dpParams = coreParams.dpParams 366 val exuParameters = coreParams.exuParameters 367 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 368 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 369 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 370 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 371 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 372 val LoadPipelineWidth = coreParams.LoadPipelineWidth 373 val StorePipelineWidth = coreParams.StorePipelineWidth 374 val StoreBufferSize = coreParams.StoreBufferSize 375 val StoreBufferThreshold = coreParams.StoreBufferThreshold 376 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 377 val EnableFastForward = coreParams.EnableFastForward 378 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 379 val RefillSize = coreParams.RefillSize 380 val asidLen = coreParams.MMUAsidLen 381 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 382 val refillBothTlb = coreParams.refillBothTlb 383 val itlbParams = coreParams.itlbParameters 384 val ldtlbParams = coreParams.ldtlbParameters 385 val sttlbParams = coreParams.sttlbParameters 386 val btlbParams = coreParams.btlbParameters 387 val l2tlbParams = coreParams.l2tlbParameters 388 val NumPerfCounters = coreParams.NumPerfCounters 389 390 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 391 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 392 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 393 ((exuParameters.StuCnt+1)/2) + ((exuParameters.StuCnt+1)/2) 394 395 val instBytes = if (HasCExtension) 2 else 4 396 val instOffsetBits = log2Ceil(instBytes) 397 398 val icacheParameters = coreParams.icacheParameters 399 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 400 401 val LRSCCycles = 100 402 403 // cache hierarchy configurations 404 val l1BusDataWidth = 256 405 406 // load violation predict 407 val ResetTimeMax2Pow = 20 //1078576 408 val ResetTimeMin2Pow = 10 //1024 409 // wait table parameters 410 val WaitTableSize = 1024 411 val MemPredPCWidth = log2Up(WaitTableSize) 412 val LWTUse2BitCounter = true 413 // store set parameters 414 val SSITSize = WaitTableSize 415 val LFSTSize = 32 416 val SSIDWidth = log2Up(LFSTSize) 417 val LFSTWidth = 4 418 val StoreSetEnable = true // LWT will be disabled if SS is enabled 419 420 val loadExuConfigs = coreParams.loadExuConfigs 421 val storeExuConfigs = coreParams.storeExuConfigs 422 423 val intExuConfigs = coreParams.intExuConfigs 424 425 val fpExuConfigs = coreParams.fpExuConfigs 426 427 val exuConfigs = coreParams.exuConfigs 428 429 val PCntIncrStep: Int = 6 430 val numPCntHc: Int = 25 431 val numPCntPtw: Int = 19 432 433 val numCSRPCntFrontend = 8 434 val numCSRPCntCtrl = 8 435 val numCSRPCntLsu = 8 436 val numCSRPCntHc = 5 437} 438