1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.ImmUnion 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache._ 27import xiangshan.cache.mmu.{TLB, TlbCmd, TlbPtwIO, TlbReq, TlbRequestIO, TlbResp} 28 29class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 30 val loadIn = ValidIO(new LsPipelineBundle) 31 val ldout = Flipped(DecoupledIO(new ExuOutput)) 32 val loadDataForwarded = Output(Bool()) 33 val needReplayFromRS = Output(Bool()) 34 val forward = new PipeLoadForwardQueryIO 35 val loadViolationQuery = new LoadViolationQueryIO 36} 37 38class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 39 // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 40 val data = UInt(XLEN.W) 41 val valid = Bool() 42} 43 44// Load Pipeline Stage 0 45// Generate addr, use addr to query DCache and DTLB 46class LoadUnit_S0(implicit p: Parameters) extends XSModule with HasDCacheParameters{ 47 val io = IO(new Bundle() { 48 val in = Flipped(Decoupled(new ExuInput)) 49 val out = Decoupled(new LsPipelineBundle) 50 val fastpath = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 51 val dtlbReq = DecoupledIO(new TlbReq) 52 val dcacheReq = DecoupledIO(new DCacheWordReq) 53 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 54 val isFirstIssue = Input(Bool()) 55 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 56 }) 57 require(LoadPipelineWidth == exuParameters.LduCnt) 58 59 val s0_uop = io.in.bits.uop 60 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 61 62 // slow vaddr from non-load insts 63 val slowpath_vaddr = io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 64 val slowpath_mask = genWmask(slowpath_vaddr, s0_uop.ctrl.fuOpType(1,0)) 65 66 // fast vaddr from load insts 67 val fastpath_vaddrs = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 68 io.fastpath(i).data + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 69 }))) 70 val fastpath_masks = WireInit(VecInit(List.tabulate(LoadPipelineWidth)(i => { 71 genWmask(fastpath_vaddrs(i), s0_uop.ctrl.fuOpType(1,0)) 72 }))) 73 val fastpath_vaddr = Mux1H(io.loadFastMatch, fastpath_vaddrs) 74 val fastpath_mask = Mux1H(io.loadFastMatch, fastpath_masks) 75 76 // select vaddr from 2 alus 77 val s0_vaddr = Mux(io.loadFastMatch.orR, fastpath_vaddr, slowpath_vaddr) 78 val s0_mask = Mux(io.loadFastMatch.orR, fastpath_mask, slowpath_mask) 79 XSPerfAccumulate("load_to_load_forward", io.loadFastMatch.orR && io.in.fire()) 80 81 val isSoftPrefetch = Wire(Bool()) 82 isSoftPrefetch := s0_uop.ctrl.isORI //it's a ORI but it exists in ldu, which means it's a softprefecth 83 val isSoftPrefetchRead = Wire(Bool()) 84 val isSoftPrefetchWrite = Wire(Bool()) 85 isSoftPrefetchRead := s0_uop.ctrl.isSoftPrefetchRead 86 isSoftPrefetchWrite := s0_uop.ctrl.isSoftPrefetchWrite 87 88 // query DTLB 89 io.dtlbReq.valid := io.in.valid 90 io.dtlbReq.bits.vaddr := s0_vaddr 91 io.dtlbReq.bits.cmd := TlbCmd.read 92 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 93 io.dtlbReq.bits.robIdx := s0_uop.robIdx 94 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 95 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 96 97 // query DCache 98 io.dcacheReq.valid := io.in.valid 99 when (isSoftPrefetchRead) { 100 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFR 101 }.elsewhen (isSoftPrefetchWrite) { 102 io.dcacheReq.bits.cmd := MemoryOpConstants.M_PFW 103 }.otherwise { 104 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 105 } 106 io.dcacheReq.bits.addr := s0_vaddr 107 io.dcacheReq.bits.mask := s0_mask 108 io.dcacheReq.bits.data := DontCare 109 when(isSoftPrefetch) { 110 io.dcacheReq.bits.instrtype := SOFT_PREFETCH.U 111 }.otherwise { 112 io.dcacheReq.bits.instrtype := LOAD_SOURCE.U 113 } 114 115 // TODO: update cache meta 116 io.dcacheReq.bits.id := DontCare 117 118 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 119 "b00".U -> true.B, //b 120 "b01".U -> (s0_vaddr(0) === 0.U), //h 121 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 122 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 123 )) 124 125 io.out.valid := io.in.valid && io.dcacheReq.ready 126 127 io.out.bits := DontCare 128 io.out.bits.vaddr := s0_vaddr 129 io.out.bits.mask := s0_mask 130 io.out.bits.uop := s0_uop 131 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 132 io.out.bits.rsIdx := io.rsIdx 133 io.out.bits.isFirstIssue := io.isFirstIssue 134 io.out.bits.isSoftPrefetch := isSoftPrefetch 135 136 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 137 138 XSDebug(io.dcacheReq.fire(), 139 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 140 ) 141 XSPerfAccumulate("in_valid", io.in.valid) 142 XSPerfAccumulate("in_fire", io.in.fire) 143 XSPerfAccumulate("in_fire_first_issue", io.in.valid && io.isFirstIssue) 144 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready) 145 XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready) 146 XSPerfAccumulate("addr_spec_success", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 147 XSPerfAccumulate("addr_spec_failed", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 148 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 149 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 150} 151 152 153// Load Pipeline Stage 1 154// TLB resp (send paddr to dcache) 155class LoadUnit_S1(implicit p: Parameters) extends XSModule { 156 val io = IO(new Bundle() { 157 val in = Flipped(Decoupled(new LsPipelineBundle)) 158 val out = Decoupled(new LsPipelineBundle) 159 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 160 val dcachePAddr = Output(UInt(PAddrBits.W)) 161 val dcacheKill = Output(Bool()) 162 val dcacheBankConflict = Input(Bool()) 163 val fullForwardFast = Output(Bool()) 164 val sbuffer = new LoadForwardQueryIO 165 val lsq = new PipeLoadForwardQueryIO 166 val loadViolationQueryReq = Decoupled(new LoadViolationQueryReq) 167 val rsFeedback = ValidIO(new RSFeedback) 168 val csrCtrl = Flipped(new CustomCSRCtrlIO) 169 val needLdVioCheckRedo = Output(Bool()) 170 }) 171 172 val isSoftPrefetch = io.in.bits.isSoftPrefetch 173 val actually_execpt = io.dtlbResp.bits.excp.pf.ld || io.dtlbResp.bits.excp.af.ld || io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) 174 val actually_mmio = !io.dtlbResp.bits.miss && io.dtlbResp.bits.mmio 175 176 val softprefecth_mmio = isSoftPrefetch && actually_mmio //TODO, fix it 177 val softprefecth_excep = isSoftPrefetch && actually_execpt //TODO, fix it 178 179 val s1_uop = io.in.bits.uop 180 val s1_paddr = io.dtlbResp.bits.paddr 181 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR // af & pf exception were modified below. 182 val s1_tlb_miss = io.dtlbResp.bits.miss 183 //val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 184 val s1_mmio = !isSoftPrefetch && actually_mmio 185 val s1_mask = io.in.bits.mask 186 val s1_bank_conflict = io.dcacheBankConflict 187 188 io.out.bits := io.in.bits // forwardXX field will be updated in s1 189 190 io.dtlbResp.ready := true.B 191 192 // TOOD: PMA check 193 io.dcachePAddr := s1_paddr 194 //io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 195 io.dcacheKill := s1_tlb_miss || actually_mmio || actually_execpt 196 197 // load forward query datapath 198 io.sbuffer.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 199 io.sbuffer.vaddr := io.in.bits.vaddr 200 io.sbuffer.paddr := s1_paddr 201 io.sbuffer.uop := s1_uop 202 io.sbuffer.sqIdx := s1_uop.sqIdx 203 io.sbuffer.mask := s1_mask 204 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 205 206 io.lsq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 207 io.lsq.vaddr := io.in.bits.vaddr 208 io.lsq.paddr := s1_paddr 209 io.lsq.uop := s1_uop 210 io.lsq.sqIdx := s1_uop.sqIdx 211 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 212 io.lsq.mask := s1_mask 213 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 214 215 // ld-ld violation query 216 io.loadViolationQueryReq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 217 io.loadViolationQueryReq.bits.paddr := s1_paddr 218 io.loadViolationQueryReq.bits.uop := s1_uop 219 220 // Generate forwardMaskFast to wake up insts earlier 221 val forwardMaskFast = io.lsq.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt 222 io.fullForwardFast := (~forwardMaskFast & s1_mask) === 0.U 223 224 // Generate feedback signal caused by: 225 // * dcache bank conflict 226 // * need redo ld-ld violation check 227 val needLdVioCheckRedo = io.loadViolationQueryReq.valid && 228 !io.loadViolationQueryReq.ready && 229 RegNext(io.csrCtrl.ldld_vio_check) 230 io.needLdVioCheckRedo := needLdVioCheckRedo 231 io.rsFeedback.valid := io.in.valid && (s1_bank_conflict || needLdVioCheckRedo) 232 io.rsFeedback.bits.hit := false.B // we have found s1_bank_conflict / re do ld-ld violation check 233 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 234 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 235 io.rsFeedback.bits.sourceType := Mux(s1_bank_conflict, RSFeedbackType.bankConflict, RSFeedbackType.ldVioCheckRedo) 236 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 237 238 // if replay is detected in load_s1, 239 // load inst will be canceled immediately 240 io.out.valid := io.in.valid && !io.rsFeedback.valid 241 io.out.bits.paddr := s1_paddr 242 io.out.bits.mmio := s1_mmio && !s1_exception 243 io.out.bits.tlbMiss := s1_tlb_miss 244 245 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 246 // af & pf exception were modified 247 io.out.bits.uop.cf.exceptionVec(loadPageFault) := !isSoftPrefetch && io.dtlbResp.bits.excp.pf.ld 248 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := !isSoftPrefetch && io.dtlbResp.bits.excp.af.ld 249 250 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 251 io.out.bits.rsIdx := io.in.bits.rsIdx 252 253 // soft prefetch stuff 254 io.out.bits.isSoftPrefetch := io.in.bits.isSoftPrefetch 255 io.out.bits.isSoftPreExcept := softprefecth_excep 256 io.out.bits.isSoftPremmio := softprefecth_mmio 257 258 io.in.ready := !io.in.valid || io.out.ready 259 260 XSPerfAccumulate("in_valid", io.in.valid) 261 XSPerfAccumulate("in_fire", io.in.fire) 262 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 263 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 264 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 265 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 266} 267 268// Load Pipeline Stage 2 269// DCache resp 270class LoadUnit_S2(implicit p: Parameters) extends XSModule with HasLoadHelper { 271 val io = IO(new Bundle() { 272 val in = Flipped(Decoupled(new LsPipelineBundle)) 273 val out = Decoupled(new LsPipelineBundle) 274 val rsFeedback = ValidIO(new RSFeedback) 275 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 276 val pmpResp = Input(new PMPRespBundle()) 277 val lsq = new LoadForwardQueryIO 278 val dataInvalidSqIdx = Input(UInt()) 279 val sbuffer = new LoadForwardQueryIO 280 val dataForwarded = Output(Bool()) 281 val needReplayFromRS = Output(Bool()) 282 val fullForward = Output(Bool()) 283 val fastpath = Output(new LoadToLoadIO) 284 val dcache_kill = Output(Bool()) 285 val loadViolationQueryResp = Flipped(Valid(new LoadViolationQueryResp)) 286 val csrCtrl = Flipped(new CustomCSRCtrlIO) 287 }) 288 289 val excep = WireInit(io.in.bits.uop.cf.exceptionVec) 290 excep(loadAccessFault) := io.in.bits.uop.cf.exceptionVec(loadAccessFault) || io.pmpResp.ld 291 val s2_exception = selectLoad(excep, false).asUInt.orR 292 293 val s2_uop = io.in.bits.uop 294 val s2_mask = io.in.bits.mask 295 val s2_paddr = io.in.bits.paddr 296 val s2_tlb_miss = io.in.bits.tlbMiss 297 val s2_data_invalid = io.lsq.dataInvalid 298 val s2_mmio = io.in.bits.mmio && !s2_exception 299 val s2_cache_miss = io.dcacheResp.bits.miss 300 val s2_cache_replay = io.dcacheResp.bits.replay 301 302 val s2_cache_miss_enter = io.dcacheResp.bits.miss_enter //missReq enter the mshr successfully 303 val isSoftPreExcept = io.in.bits.isSoftPreExcept 304 val isSoftPremmio = io.in.bits.isSoftPremmio 305 // val cnt = RegInit(127.U) 306 // cnt := cnt + io.in.valid.asUInt 307 // val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid || cnt === 0.U 308 309 val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid 310 311 // assert(!s2_forward_fail) 312 io.dcache_kill := io.in.valid && io.pmpResp.ld 313 io.dcacheResp.ready := true.B 314 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 315 assert(!(io.in.valid && (dcacheShouldResp && !io.dcacheResp.valid) && (!isSoftPreExcept) && (!isSoftPremmio)), "DCache response got lost") 316 317 // merge forward result 318 // lsq has higher priority than sbuffer 319 val forwardMask = Wire(Vec(8, Bool())) 320 val forwardData = Wire(Vec(8, UInt(8.W))) 321 322 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U && !io.lsq.dataInvalid 323 io.lsq := DontCare 324 io.sbuffer := DontCare 325 io.fullForward := fullForward 326 327 // generate XLEN/8 Muxs 328 for (i <- 0 until XLEN / 8) { 329 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 330 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 331 } 332 333 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 334 s2_uop.cf.pc, 335 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 336 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 337 ) 338 339 // data merge 340 val rdataVec = VecInit((0 until XLEN / 8).map(j => 341 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 342 val rdata = rdataVec.asUInt 343 val rdataSel = LookupTree(s2_paddr(2, 0), List( 344 "b000".U -> rdata(63, 0), 345 "b001".U -> rdata(63, 8), 346 "b010".U -> rdata(63, 16), 347 "b011".U -> rdata(63, 24), 348 "b100".U -> rdata(63, 32), 349 "b101".U -> rdata(63, 40), 350 "b110".U -> rdata(63, 48), 351 "b111".U -> rdata(63, 56) 352 )) 353 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 354 355 io.out.valid := io.in.valid && !s2_tlb_miss && !s2_data_invalid 356 // Inst will be canceled in store queue / lsq, 357 // so we do not need to care about flush in load / store unit's out.valid 358 io.out.bits := io.in.bits 359 io.out.bits.data := rdataPartialLoad 360 // when exception occurs, set it to not miss and let it write back to rob (via int port) 361 if (EnableFastForward) { 362 when(io.in.bits.isSoftPrefetch) { 363 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail && !fullForward && !s2_cache_miss_enter && !isSoftPreExcept && !isSoftPremmio 364 }.otherwise { 365 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail && !fullForward 366 } 367 } else { 368 when(io.in.bits.isSoftPrefetch) { 369 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail && !s2_cache_miss_enter && !isSoftPreExcept && !isSoftPremmio 370 }.otherwise { 371 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail 372 } 373 } 374 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 375 // if forward fail, replay this inst from fetch 376 val forwardFailReplay = s2_forward_fail && !s2_mmio 377 // if ld-ld violation is detected, replay from this inst from fetch 378 val ldldVioReplay = io.loadViolationQueryResp.valid && 379 io.loadViolationQueryResp.bits.have_violation && 380 RegNext(io.csrCtrl.ldld_vio_check) 381 io.out.bits.uop.ctrl.replayInst := forwardFailReplay || ldldVioReplay 382 io.out.bits.mmio := s2_mmio 383 io.out.bits.uop.cf.exceptionVec := excep 384 385 // For timing reasons, sometimes we can not let 386 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 387 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 388 // and dcache query is no longer needed. 389 // Such inst will be writebacked from load queue. 390 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception && !s2_forward_fail 391 // io.out.bits.forwardX will be send to lq 392 io.out.bits.forwardMask := forwardMask 393 // data retbrived from dcache is also included in io.out.bits.forwardData 394 io.out.bits.forwardData := rdataVec 395 396 io.in.ready := io.out.ready || !io.in.valid 397 398 399 // feedback tlb result to RS 400 io.rsFeedback.valid := io.in.valid 401 when (io.in.bits.isSoftPrefetch) { 402 io.rsFeedback.bits.hit := (!s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception || fullForward) && !s2_data_invalid) || s2_cache_miss_enter || isSoftPreExcept || isSoftPremmio 403 }.otherwise { 404 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception || fullForward) && !s2_data_invalid 405 } 406 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 407 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 408 io.rsFeedback.bits.sourceType := Mux(s2_tlb_miss, RSFeedbackType.tlbMiss, 409 Mux(io.lsq.dataInvalid, 410 RSFeedbackType.dataInvalid, 411 RSFeedbackType.mshrFull 412 ) 413 ) 414 io.rsFeedback.bits.dataInvalidSqIdx.value := io.dataInvalidSqIdx 415 io.rsFeedback.bits.dataInvalidSqIdx.flag := DontCare 416 417 // s2_cache_replay is quite slow to generate, send it separately to LQ 418 io.needReplayFromRS := s2_cache_replay && !fullForward 419 420 // fast load to load forward 421 io.fastpath.valid := io.in.valid // for debug only 422 io.fastpath.data := rdata // raw data 423 424 425 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 426 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 427 forwardData.asUInt, forwardMask.asUInt 428 ) 429 430 XSPerfAccumulate("in_valid", io.in.valid) 431 XSPerfAccumulate("in_fire", io.in.fire) 432 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 433 XSPerfAccumulate("dcache_miss", io.in.fire && s2_cache_miss) 434 XSPerfAccumulate("dcache_miss_first_issue", io.in.fire && s2_cache_miss && io.in.bits.isFirstIssue) 435 XSPerfAccumulate("full_forward", io.in.valid && fullForward) 436 XSPerfAccumulate("dcache_miss_full_forward", io.in.valid && s2_cache_miss && fullForward) 437 XSPerfAccumulate("replay", io.rsFeedback.valid && !io.rsFeedback.bits.hit) 438 XSPerfAccumulate("replay_tlb_miss", io.rsFeedback.valid && !io.rsFeedback.bits.hit && s2_tlb_miss) 439 XSPerfAccumulate("replay_cache", io.rsFeedback.valid && !io.rsFeedback.bits.hit && !s2_tlb_miss && s2_cache_replay) 440 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 441 XSPerfAccumulate("replay_from_fetch_forward", io.out.valid && forwardFailReplay) 442 XSPerfAccumulate("replay_from_fetch_load_vio", io.out.valid && ldldVioReplay) 443} 444 445class LoadUnit(implicit p: Parameters) extends XSModule with HasLoadHelper { 446 val io = IO(new Bundle() { 447 val ldin = Flipped(Decoupled(new ExuInput)) 448 val ldout = Decoupled(new ExuOutput) 449 val redirect = Flipped(ValidIO(new Redirect)) 450 val feedbackSlow = ValidIO(new RSFeedback) 451 val feedbackFast = ValidIO(new RSFeedback) 452 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 453 val isFirstIssue = Input(Bool()) 454 val dcache = new DCacheLoadIO 455 val sbuffer = new LoadForwardQueryIO 456 val lsq = new LoadToLsqIO 457 val fastUop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1 458 459 val tlb = new TlbRequestIO 460 val pmp = Input(new PMPRespBundle()) // arrive same to tlb now 461 462 val fastpathOut = Output(new LoadToLoadIO) 463 val fastpathIn = Input(Vec(LoadPipelineWidth, new LoadToLoadIO)) 464 val loadFastMatch = Input(UInt(exuParameters.LduCnt.W)) 465 466 val csrCtrl = Flipped(new CustomCSRCtrlIO) 467 }) 468 469 val load_s0 = Module(new LoadUnit_S0) 470 val load_s1 = Module(new LoadUnit_S1) 471 val load_s2 = Module(new LoadUnit_S2) 472 473 load_s0.io.in <> io.ldin 474 load_s0.io.dtlbReq <> io.tlb.req 475 load_s0.io.dcacheReq <> io.dcache.req 476 load_s0.io.rsIdx := io.rsIdx 477 load_s0.io.isFirstIssue := io.isFirstIssue 478 load_s0.io.fastpath := io.fastpathIn 479 load_s0.io.loadFastMatch := io.loadFastMatch 480 481 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 482 483 load_s1.io.dtlbResp <> io.tlb.resp 484 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 485 io.dcache.s1_kill <> load_s1.io.dcacheKill 486 load_s1.io.sbuffer <> io.sbuffer 487 load_s1.io.lsq <> io.lsq.forward 488 load_s1.io.loadViolationQueryReq <> io.lsq.loadViolationQuery.req 489 load_s1.io.dcacheBankConflict <> io.dcache.s1_bank_conflict 490 load_s1.io.csrCtrl <> io.csrCtrl 491 492 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 493 494 io.dcache.s2_kill <> load_s2.io.dcache_kill 495 load_s2.io.dcacheResp <> io.dcache.resp 496 load_s2.io.pmpResp <> io.pmp 497 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 498 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 499 load_s2.io.lsq.forwardMaskFast <> io.lsq.forward.forwardMaskFast // should not be used in load_s2 500 load_s2.io.lsq.dataInvalid <> io.lsq.forward.dataInvalid 501 load_s2.io.lsq.matchInvalid <> io.lsq.forward.matchInvalid 502 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 503 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 504 load_s2.io.sbuffer.forwardMaskFast <> io.sbuffer.forwardMaskFast // should not be used in load_s2 505 load_s2.io.sbuffer.dataInvalid <> io.sbuffer.dataInvalid // always false 506 load_s2.io.sbuffer.matchInvalid <> io.sbuffer.matchInvalid 507 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 508 load_s2.io.fastpath <> io.fastpathOut 509 load_s2.io.dataInvalidSqIdx := io.lsq.forward.dataInvalidSqIdx // provide dataInvalidSqIdx to make wakeup faster 510 load_s2.io.loadViolationQueryResp <> io.lsq.loadViolationQuery.resp 511 load_s2.io.csrCtrl <> io.csrCtrl 512 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 513 514 // feedback tlb miss / dcache miss queue full 515 io.feedbackSlow.bits := RegNext(load_s2.io.rsFeedback.bits) 516 io.feedbackSlow.valid := RegNext(load_s2.io.rsFeedback.valid && !load_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 517 518 // feedback bank conflict to rs 519 io.feedbackFast.bits := load_s1.io.rsFeedback.bits 520 io.feedbackFast.valid := load_s1.io.rsFeedback.valid 521 // If replay is reported at load_s1, inst will be canceled (will not enter load_s2), 522 // in that case: 523 // * replay should not be reported twice 524 assert(!(RegNext(RegNext(io.feedbackFast.valid)) && io.feedbackSlow.valid)) 525 // * io.fastUop.valid should not be reported 526 assert(!RegNext(io.feedbackFast.valid && io.fastUop.valid)) 527 528 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 529 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 530 io.lsq.forward.sqIdxMask := sqIdxMaskReg 531 532 // // use s2_hit_way to select data received in s1 533 // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data)) 534 // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 535 536 io.fastUop.valid := io.dcache.s1_hit_way.orR && // dcache hit 537 !io.dcache.s1_disable_fast_wakeup && // load fast wakeup should be disabled when dcache data read is not ready 538 load_s1.io.in.valid && // valid laod request 539 !load_s1.io.dcacheKill && // not mmio or tlb miss 540 !io.lsq.forward.dataInvalidFast && // forward failed 541 !load_s1.io.needLdVioCheckRedo // load-load violation check: load paddr cam struct hazard 542 io.fastUop.bits := load_s1.io.out.bits.uop 543 544 XSDebug(load_s0.io.out.valid, 545 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 546 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 547 XSDebug(load_s1.io.out.valid, 548 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 549 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 550 551 // writeback to LSQ 552 // Current dcache use MSHR 553 // Load queue will be updated at s2 for both hit/miss int/fp load 554 io.lsq.loadIn.valid := load_s2.io.out.valid 555 io.lsq.loadIn.bits := load_s2.io.out.bits 556 557 // write to rob and writeback bus 558 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss && !load_s2.io.out.bits.mmio 559 560 // Int load, if hit, will be writebacked at s2 561 val hitLoadOut = Wire(Valid(new ExuOutput)) 562 hitLoadOut.valid := s2_wb_valid 563 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 564 hitLoadOut.bits.data := load_s2.io.out.bits.data 565 hitLoadOut.bits.redirectValid := false.B 566 hitLoadOut.bits.redirect := DontCare 567 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 568 hitLoadOut.bits.debug.isPerfCnt := false.B 569 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 570 hitLoadOut.bits.fflags := DontCare 571 572 load_s2.io.out.ready := true.B 573 574 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 575 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 576 577 io.lsq.ldout.ready := !hitLoadOut.valid 578 579 val perfinfo = IO(new Bundle(){ 580 val perfEvents = Output(new PerfEventsBundle(12)) 581 }) 582 583 val perfEvents = Seq( 584 ("load_s0_in_fire ", load_s0.io.in.fire() ), 585 ("load_to_load_forward ", load_s0.io.loadFastMatch.orR && load_s0.io.in.fire() ), 586 ("stall_dcache ", load_s0.io.out.valid && load_s0.io.out.ready && !load_s0.io.dcacheReq.ready ), 587 ("addr_spec_success ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) === load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 588 ("addr_spec_failed ", load_s0.io.out.fire() && load_s0.io.dtlbReq.bits.vaddr(VAddrBits-1, 12) =/= load_s0.io.in.bits.src(0)(VAddrBits-1, 12) ), 589 ("load_s1_in_fire ", load_s1.io.in.fire ), 590 ("load_s1_tlb_miss ", load_s1.io.in.fire && load_s1.io.dtlbResp.bits.miss ), 591 ("load_s2_in_fire ", load_s2.io.in.fire ), 592 ("load_s2_dcache_miss ", load_s2.io.in.fire && load_s2.io.dcacheResp.bits.miss ), 593 ("load_s2_replay ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit ), 594 ("load_s2_replay_tlb_miss ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && load_s2.io.in.bits.tlbMiss ), 595 ("load_s2_replay_cache ", load_s2.io.rsFeedback.valid && !load_s2.io.rsFeedback.bits.hit && !load_s2.io.in.bits.tlbMiss && load_s2.io.dcacheResp.bits.miss), 596 ) 597 598 for (((perf_out,(perf_name,perf)),i) <- perfinfo.perfEvents.perf_events.zip(perfEvents).zipWithIndex) { 599 perf_out.incr_step := RegNext(perf) 600 } 601 602 when(io.ldout.fire()){ 603 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 604 } 605} 606