xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision c3abb8b6b92c14ec0f3dbbac60a8caa531994a95) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.exu._
23import xiangshan.backend.dispatch.DispatchParameters
24import xiangshan.cache.DCacheParameters
25import xiangshan.cache.prefetch._
26import huancun.{CacheParameters, HCCacheParameters}
27import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, ITTage, Tage_SC}
28import xiangshan.cache.mmu.{TLBParameters, L2TLBParameters}
29import freechips.rocketchip.diplomacy.AddressSet
30
31case object XSCoreParamsKey extends Field[XSCoreParameters]
32
33case class XSCoreParameters
34(
35  HasPrefetch: Boolean = false,
36  HartId: Int = 0,
37  XLEN: Int = 64,
38  HasMExtension: Boolean = true,
39  HasCExtension: Boolean = true,
40  HasDiv: Boolean = true,
41  HasICache: Boolean = true,
42  HasDCache: Boolean = true,
43  AddrBits: Int = 64,
44  VAddrBits: Int = 39,
45  PAddrBits: Int = 40,
46  HasFPU: Boolean = true,
47  HasCustomCSRCacheOp: Boolean = true,
48  FetchWidth: Int = 8,
49  AsidLength: Int = 16,
50  EnableBPU: Boolean = true,
51  EnableBPD: Boolean = true,
52  EnableRAS: Boolean = true,
53  EnableLB: Boolean = false,
54  EnableLoop: Boolean = true,
55  EnableSC: Boolean = true,
56  EnbaleTlbDebug: Boolean = false,
57  EnableJal: Boolean = false,
58  EnableUBTB: Boolean = true,
59  HistoryLength: Int = 64,
60  PathHistoryLength: Int = 16,
61  BtbSize: Int = 2048,
62  JbtacSize: Int = 1024,
63  JbtacBanks: Int = 8,
64  RasSize: Int = 32,
65  CacheLineSize: Int = 512,
66  UBtbWays: Int = 16,
67  BtbWays: Int = 2,
68  branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] =
69    ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => {
70      // val loop = Module(new LoopPredictor)
71      // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC)
72      //                             else          Module(new Tage) }
73      //             else          { Module(new FakeTage) })
74      val ftb = Module(new FTB()(p))
75      val ubtb = Module(new MicroBTB()(p))
76      val bim = Module(new BIM()(p))
77      val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) }
78      val ras = Module(new RAS()(p))
79      val ittage = Module(new ITTage()(p))
80      // val tage = Module(new Tage()(p))
81      // val fake = Module(new FakePredictor()(p))
82
83      // val preds = Seq(loop, tage, btb, ubtb, bim)
84      val preds = Seq(bim, ubtb, tage, ftb, ittage, ras)
85      preds.map(_.io := DontCare)
86
87      // ubtb.io.resp_in(0)  := resp_in
88      // bim.io.resp_in(0)   := ubtb.io.resp
89      // btb.io.resp_in(0)   := bim.io.resp
90      // tage.io.resp_in(0)  := btb.io.resp
91      // loop.io.resp_in(0)  := tage.io.resp
92      bim.io.in.bits.resp_in(0)  := resp_in
93      ubtb.io.in.bits.resp_in(0) := bim.io.out.resp
94      tage.io.in.bits.resp_in(0) := ubtb.io.out.resp
95      ftb.io.in.bits.resp_in(0)  := tage.io.out.resp
96      ittage.io.in.bits.resp_in(0)  := ftb.io.out.resp
97      ras.io.in.bits.resp_in(0) := ittage.io.out.resp
98
99      (preds, ras.io.out.resp)
100    }),
101  IBufSize: Int = 48,
102  DecodeWidth: Int = 6,
103  RenameWidth: Int = 6,
104  CommitWidth: Int = 6,
105  FtqSize: Int = 64,
106  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
107  IssQueSize: Int = 16,
108  NRPhyRegs: Int = 192,
109  NRIntReadPorts: Int = 14,
110  NRIntWritePorts: Int = 8,
111  NRFpReadPorts: Int = 14,
112  NRFpWritePorts: Int = 8,
113  LoadQueueSize: Int = 80,
114  StoreQueueSize: Int = 64,
115  RobSize: Int = 256,
116  dpParams: DispatchParameters = DispatchParameters(
117    IntDqSize = 16,
118    FpDqSize = 16,
119    LsDqSize = 16,
120    IntDqDeqWidth = 4,
121    FpDqDeqWidth = 4,
122    LsDqDeqWidth = 4
123  ),
124  exuParameters: ExuParameters = ExuParameters(
125    JmpCnt = 1,
126    AluCnt = 4,
127    MulCnt = 0,
128    MduCnt = 2,
129    FmacCnt = 4,
130    FmiscCnt = 2,
131    FmiscDivSqrtCnt = 0,
132    LduCnt = 2,
133    StuCnt = 2
134  ),
135  LoadPipelineWidth: Int = 2,
136  StorePipelineWidth: Int = 2,
137  StoreBufferSize: Int = 16,
138  StoreBufferThreshold: Int = 7,
139  EnableFastForward: Boolean = true,
140  EnableLdVioCheckAfterReset: Boolean = false,
141  RefillSize: Int = 512,
142  MMUAsidLen: Int = 16, // max is 16, 0 is not supported now
143  itlbParameters: TLBParameters = TLBParameters(
144    name = "itlb",
145    fetchi = true,
146    useDmode = false,
147    sameCycle = true,
148    normalNWays = 32,
149    normalReplacer = Some("plru"),
150    superNWays = 4,
151    superReplacer = Some("plru"),
152    shouldBlock = true
153  ),
154  ldtlbParameters: TLBParameters = TLBParameters(
155    name = "ldtlb",
156    normalNSets = 128,
157    normalNWays = 1,
158    normalAssociative = "sa",
159    normalReplacer = Some("setplru"),
160    superNWays = 8,
161    normalAsVictim = true,
162    outReplace = true
163  ),
164  sttlbParameters: TLBParameters = TLBParameters(
165    name = "sttlb",
166    normalNSets = 128,
167    normalNWays = 1,
168    normalAssociative = "sa",
169    normalReplacer = Some("setplru"),
170    superNWays = 8,
171    normalAsVictim = true,
172    outReplace = true
173  ),
174  refillBothTlb: Boolean = false,
175  btlbParameters: TLBParameters = TLBParameters(
176    name = "btlb",
177    normalNSets = 1,
178    normalNWays = 64,
179    superNWays = 4,
180  ),
181  l2tlbParameters: L2TLBParameters = L2TLBParameters(),
182  NumPMP: Int = 16, // 0 or 16 or 64
183  NumPerfCounters: Int = 16,
184  icacheParameters: ICacheParameters = ICacheParameters(
185    tagECC = Some("parity"),
186    dataECC = Some("parity"),
187    replacer = Some("setplru"),
188    nMissEntries = 2
189  ),
190  dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters(
191    tagECC = Some("secded"),
192    dataECC = Some("secded"),
193    replacer = Some("setplru"),
194    nMissEntries = 16,
195    nProbeEntries = 16,
196    nReleaseEntries = 32
197  )),
198  L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters(
199    name = "l2",
200    level = 2,
201    ways = 8,
202    sets = 1024, // default 512KB L2
203    prefetch = Some(huancun.prefetch.BOPParameters())
204  )),
205  L2NBanks: Int = 1,
206  usePTWRepeater: Boolean = false,
207  softPTW: Boolean = false // dpi-c debug only
208){
209  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
210  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg)
211
212  val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
213    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg)
214
215  val fpExuConfigs =
216    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
217      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
218
219  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
220}
221
222case object DebugOptionsKey extends Field[DebugOptions]
223
224case class DebugOptions
225(
226  FPGAPlatform: Boolean = true,
227  EnableDebug: Boolean = true,
228  EnablePerfDebug: Boolean = true,
229  UseDRAMSim: Boolean = false
230)
231
232trait HasXSParameter {
233
234  implicit val p: Parameters
235
236  val coreParams = p(XSCoreParamsKey)
237  val env = p(DebugOptionsKey)
238
239  val XLEN = coreParams.XLEN
240  val hardId = coreParams.HartId
241  val minFLen = 32
242  val fLen = 64
243  def xLen = XLEN
244
245  val HasMExtension = coreParams.HasMExtension
246  val HasCExtension = coreParams.HasCExtension
247  val HasDiv = coreParams.HasDiv
248  val HasIcache = coreParams.HasICache
249  val HasDcache = coreParams.HasDCache
250  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
251  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
252  val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits
253  val AsidLength = coreParams.AsidLength
254  val AddrBytes = AddrBits / 8 // unused
255  val DataBits = XLEN
256  val DataBytes = DataBits / 8
257  val HasFPU = coreParams.HasFPU
258  val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp
259  val FetchWidth = coreParams.FetchWidth
260  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
261  val EnableBPU = coreParams.EnableBPU
262  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
263  val EnableRAS = coreParams.EnableRAS
264  val EnableLB = coreParams.EnableLB
265  val EnableLoop = coreParams.EnableLoop
266  val EnableSC = coreParams.EnableSC
267  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
268  val HistoryLength = coreParams.HistoryLength
269  val PathHistoryLength = coreParams.PathHistoryLength
270  val BtbSize = coreParams.BtbSize
271  // val BtbWays = 4
272  val BtbBanks = PredictWidth
273  // val BtbSets = BtbSize / BtbWays
274  val JbtacSize = coreParams.JbtacSize
275  val JbtacBanks = coreParams.JbtacBanks
276  val RasSize = coreParams.RasSize
277
278  def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = {
279    coreParams.branchPredictor(resp_in, p, enableSC)
280  }
281
282  val CacheLineSize = coreParams.CacheLineSize
283  val CacheLineHalfWord = CacheLineSize / 16
284  val ExtHistoryLength = HistoryLength + 64
285  val UBtbWays = coreParams.UBtbWays
286  val BtbWays = coreParams.BtbWays
287  val IBufSize = coreParams.IBufSize
288  val DecodeWidth = coreParams.DecodeWidth
289  val RenameWidth = coreParams.RenameWidth
290  val CommitWidth = coreParams.CommitWidth
291  val FtqSize = coreParams.FtqSize
292  val IssQueSize = coreParams.IssQueSize
293  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
294  val NRPhyRegs = coreParams.NRPhyRegs
295  val PhyRegIdxWidth = log2Up(NRPhyRegs)
296  val RobSize = coreParams.RobSize
297  val IntRefCounterWidth = log2Ceil(RobSize)
298  val StdFreeListSize = NRPhyRegs - 32
299  val MEFreeListSize = NRPhyRegs
300  val LoadQueueSize = coreParams.LoadQueueSize
301  val StoreQueueSize = coreParams.StoreQueueSize
302  val dpParams = coreParams.dpParams
303  val exuParameters = coreParams.exuParameters
304  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
305  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
306  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
307  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
308  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
309  val LoadPipelineWidth = coreParams.LoadPipelineWidth
310  val StorePipelineWidth = coreParams.StorePipelineWidth
311  val StoreBufferSize = coreParams.StoreBufferSize
312  val StoreBufferThreshold = coreParams.StoreBufferThreshold
313  val EnableFastForward = coreParams.EnableFastForward
314  val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset
315  val RefillSize = coreParams.RefillSize
316  val asidLen = coreParams.MMUAsidLen
317  val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
318  val refillBothTlb = coreParams.refillBothTlb
319  val itlbParams = coreParams.itlbParameters
320  val ldtlbParams = coreParams.ldtlbParameters
321  val sttlbParams = coreParams.sttlbParameters
322  val btlbParams = coreParams.btlbParameters
323  val l2tlbParams = coreParams.l2tlbParameters
324  val NumPMP = coreParams.NumPMP
325  val PlatformGrain: Int = log2Up(coreParams.RefillSize/8) // set PlatformGrain to avoid itlb, dtlb, ptw size conflict
326  val NumPerfCounters = coreParams.NumPerfCounters
327
328  val instBytes = if (HasCExtension) 2 else 4
329  val instOffsetBits = log2Ceil(instBytes)
330
331  val icacheParameters = coreParams.icacheParameters
332  val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters())
333
334  val LRSCCycles = 100
335
336  // cache hierarchy configurations
337  val l1BusDataWidth = 256
338
339  // load violation predict
340  val ResetTimeMax2Pow = 20 //1078576
341  val ResetTimeMin2Pow = 10 //1024
342  // wait table parameters
343  val WaitTableSize = 1024
344  val MemPredPCWidth = log2Up(WaitTableSize)
345  val LWTUse2BitCounter = true
346  // store set parameters
347  val SSITSize = WaitTableSize
348  val LFSTSize = 32
349  val SSIDWidth = log2Up(LFSTSize)
350  val LFSTWidth = 4
351  val StoreSetEnable = true // LWT will be disabled if SS is enabled
352
353  val loadExuConfigs = coreParams.loadExuConfigs
354  val storeExuConfigs = coreParams.storeExuConfigs
355
356  val intExuConfigs = coreParams.intExuConfigs
357
358  val fpExuConfigs = coreParams.fpExuConfigs
359
360  val exuConfigs = coreParams.exuConfigs
361
362}
363