sq: fix commited flag update logic (#1094)

commitCount has been delayed for 1 cycle, so we need to check
uncacheState 1 cycle earlier

core: use redirect ports for flush (#1121)

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

mem: update block load logic (#1035)

* mem: update block load logic

Now load will be selected as soon as the store it depends on is ready,
which is predicted by Store Sets

* mem: opt block lo

mem: update block load logic (#1035)

* mem: update block load logic

Now load will be selected as soon as the store it depends on is ready,
which is predicted by Store Sets

* mem: opt block load logic

Load blocked by std invalid will wait for that std to issue
Load blocked by load violation wait for that sta to issue

* csr: add 2 extra storeset config bits

Following bits were added to slvpredctl:
- storeset_wait_store
- storeset_no_fast_wakeup

* storeset: fix waitForSqIdx generate logic

Now right waitForSqIdx will be generated for earlier store in the same
dispatch bundle

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add softprefetch (prefetch.r & prefetch.w). (#1099)

* add soft prefetch
Add the softprefetch. Actually, prefetch.r&w are an ORI which's ldest is x0, we distinguish it in decodeUnit and send it to l

add softprefetch (prefetch.r & prefetch.w). (#1099)

* add soft prefetch
Add the softprefetch. Actually, prefetch.r&w are an ORI which's ldest is x0, we distinguish it in decodeUnit and send it to ld func unit. Then, we modified some interaction signals in ordinary Load steps.

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Add runahead debug signals (#1082)

* runahead: add runahead support (WIP)

* runahead: fix redirect event

* difftest: bump difftest

* runahead: bump version

Note: current runahead does no

Add runahead debug signals (#1082)

* runahead: add runahead support (WIP)

* runahead: fix redirect event

* difftest: bump difftest

* runahead: bump version

Note: current runahead does not support instruction fusion, disable that
in XiangShan if runahead is needed

* runahead: bump version

* difftest: bump version to support runahead

* chore: bump huancun to make ci happy

* chore: fix wrong submodule url

* difftest: bump version

BREAKING CHANGE: nemu update_config api has changed

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Refactor cache params (#1078)

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

128KB L1D + non-inclusive L2/L3 (#1051)

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to c

128KB L1D + non-inclusive L2/L3 (#1051)

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to compile verialted files

* dcache: add BankedDataArray

* dcache: fix data read way_en

* dcache: fix banked data wmask

* dcache: replay conflict correctly

When conflict is detected:
* Report replay
* Disable fast wakeup

* dcache: fix bank addr match logic

* dcache: add bank conflict perf counter

* dcache: fix miss perf counters

* chore: make lsq data print perttier

* dcache: enable banked ecc array

* dcache: set dcache size to 128KB

* dcache: read mainpipe data from banked data array

* dcache: add independent mainpipe data read port

* dcache: revert size change

* Size will be changed after main pipe refactor

* Merge remote-tracking branch 'origin/master' into l1-size

* dcache: reduce banked data load conflict

* MainPipe: ReleaseData for all replacement even if it's clean

* dcache: set dcache size to 128KB

BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1,
and it has to help l1 to avoid addr alias problem

* chore: fix merge conflict

* Change L2 to non-inclusive / Add alias bits in L1D

* debug: hard coded dup data array for debuging

* dcache: fix ptag width

* dcache: fix amo main pipe req

* dcache: when probe, use vaddr for main pipe req

* dcache: include vaddr in atomic unit req

* dcache: fix get_tag() function

* dcache: fix writeback paddr

* huancun: bump version

* dcache: erase block offset bits in release addr

* dcache: do not require probe vaddr != 0

* dcache: opt banked data read timing

* bump huancun

* dcache: fix atom unit pipe req vaddr

* dcache: simplify main pipe writeback_vaddr

* bump huancun

* dcache: remove debug data array

* Turn on all usr bits in L1

* Bump huancun

* Bump huancun

* enable L2 prefetcher

* bump huancun

* set non-inclusive L2/L3 + 128KB L1 as default config

* Use data in TLBundleB to hint ProbeAck beeds data

* mmu.l2tlb: mem_resp now fills multi mq pte buffer

mq entries can just deq without accessing l2tlb cache

* dcache: handle dirty userbit

* bump huancun

* chore: l1 cache code clean up

* Remove l1plus cache
* Remove HasBankedDataArrayParameters

* Add bus pmu between L3 and Mem

* bump huncun

* dcache: fix l1 probe index generate logic

* Now right probe index will be used according to the len of alias bits

* dcache: clean up amo pipeline

* DCacheParameter rowBits will be removed in the future, now we set it to 128
to make dcache work

* dcache: fix amo word index

* bump huancun

Co-authored-by: William Wang <[email protected]>
Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: TangDan <[email protected]>
Co-authored-by: ZhangZifei <[email protected]>
Co-authored-by: wangkaifan <[email protected]>

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core: add timer counters for important stages (#1045)

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We

core: add timer counters for important stages (#1045)

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We add performance counters for different types of instructions to see
the latency in different pipeline stages.

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Merge pull request #987 from OpenXiangShan/fast-refill

dcache,lq: make dcache to lq refill faster

use ExtModule instead of Chisel3.BlackBox. (#988)

Merge remote-tracking branch 'origin/master' into fast-refill

Merge branch 'master' into vaddr-fwd

Merge remote-tracking branch 'origin/master' into decoupled-frontend

Merge remote-tracking branch 'origin/master' into vaddr-fwd

fudian: The new floating-point lib to replace hardfloat (#975)

* Add submodule 'fudian'

* IntToFP: use fudian

* FMA: use fudian.CMA

* FPToInt: remove recode format

Merge branch 'master' into dcp-merge-master

Merge remote-tracking branch 'origin/master' into fastpath

mem: let lq refill width be equal to l1d bus width

mem: reduce refill writeback delay by 1 cycle

* Now inst being refilled currently can be selected as wb candidate

backend: separate store address and data (#921)

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how st

backend: separate store address and data (#921)

This commit separates store address and store data in backend, including both reservation stations and function units. This commit also changes how stIssuePtr is updated. stIssuePtr should only be updated when both store data and address issue.

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mem: fix rsFeedback for fast forward

mem: loadpipe will not miss if fullForward succeed

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is gene

mem: loadpipe will not miss if fullForward succeed

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is generated at load_s1, it is used to generate
fastUop for fast wakeup
* `forwardMask` is generated at load_s2, it will be used to check if
forward result is correct

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Merge remote-tracking branch 'origin/master' into vaddr-fwd

Merge branch 'master' into merge-master