1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import xiangshan.cache.mmu.{L2TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30 31case object XSCoreParamsKey extends Field[XSCoreParameters] 32 33case class XSCoreParameters 34( 35 HasPrefetch: Boolean = false, 36 HartId: Int = 0, 37 XLEN: Int = 64, 38 HasMExtension: Boolean = true, 39 HasCExtension: Boolean = true, 40 HasDiv: Boolean = true, 41 HasICache: Boolean = true, 42 HasDCache: Boolean = true, 43 AddrBits: Int = 64, 44 VAddrBits: Int = 39, 45 PAddrBits: Int = 40, 46 HasFPU: Boolean = true, 47 FetchWidth: Int = 8, 48 EnableBPU: Boolean = true, 49 EnableBPD: Boolean = true, 50 EnableRAS: Boolean = true, 51 EnableLB: Boolean = false, 52 EnableLoop: Boolean = true, 53 EnableSC: Boolean = true, 54 EnbaleTlbDebug: Boolean = false, 55 EnableJal: Boolean = false, 56 EnableUBTB: Boolean = true, 57 HistoryLength: Int = 64, 58 BtbSize: Int = 2048, 59 JbtacSize: Int = 1024, 60 JbtacBanks: Int = 8, 61 RasSize: Int = 16, 62 CacheLineSize: Int = 512, 63 UBtbWays: Int = 16, 64 BtbWays: Int = 2, 65 66 EnableL1plusPrefetcher: Boolean = true, 67 IBufSize: Int = 48, 68 DecodeWidth: Int = 6, 69 RenameWidth: Int = 6, 70 CommitWidth: Int = 6, 71 BrqSize: Int = 32, 72 FtqSize: Int = 48, 73 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 74 IssQueSize: Int = 16, 75 NRPhyRegs: Int = 160, 76 NRIntReadPorts: Int = 14, 77 NRIntWritePorts: Int = 8, 78 NRFpReadPorts: Int = 14, 79 NRFpWritePorts: Int = 8, 80 LoadQueueSize: Int = 64, 81 StoreQueueSize: Int = 48, 82 RoqSize: Int = 192, 83 dpParams: DispatchParameters = DispatchParameters( 84 IntDqSize = 16, 85 FpDqSize = 16, 86 LsDqSize = 16, 87 IntDqDeqWidth = 4, 88 FpDqDeqWidth = 4, 89 LsDqDeqWidth = 4 90 ), 91 exuParameters: ExuParameters = ExuParameters( 92 JmpCnt = 1, 93 AluCnt = 4, 94 MulCnt = 0, 95 MduCnt = 2, 96 FmacCnt = 4, 97 FmiscCnt = 2, 98 FmiscDivSqrtCnt = 0, 99 LduCnt = 2, 100 StuCnt = 2 101 ), 102 LoadPipelineWidth: Int = 2, 103 StorePipelineWidth: Int = 2, 104 StoreBufferSize: Int = 16, 105 StoreBufferThreshold: Int = 7, 106 EnableFastForward: Boolean = true, 107 RefillSize: Int = 512, 108 TlbEntrySize: Int = 32, 109 TlbSPEntrySize: Int = 4, 110 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 111 NumPerfCounters: Int = 16, 112 icacheParameters: ICacheParameters = ICacheParameters( 113 tagECC = Some("parity"), 114 dataECC = Some("parity"), 115 replacer = Some("setplru"), 116 nMissEntries = 2 117 ), 118 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 119 tagECC = Some("secded"), 120 dataECC = Some("secded"), 121 replacer = Some("setplru"), 122 nMissEntries = 8 123 ), 124 dcacheParameters: DCacheParameters = DCacheParameters( 125 tagECC = Some("secded"), 126 dataECC = Some("secded"), 127 replacer = Some("setplru"), 128 nMissEntries = 16, 129 nProbeEntries = 16, 130 nReleaseEntries = 16, 131 nStoreReplayEntries = 16 132 ), 133 L2Size: Int = 512 * 1024, // 512KB 134 L2NWays: Int = 8, 135 usePTWRepeater: Boolean = false, 136 useFakePTW: Boolean = false, 137 useFakeDCache: Boolean = false, 138 useFakeL1plusCache: Boolean = false, 139 useFakeL2Cache: Boolean = false 140){ 141 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 142 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 143 144 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 145 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 146 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 147 148 val fpExuConfigs = 149 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 150 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 151 152 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 153} 154 155case object DebugOptionsKey extends Field[DebugOptions] 156 157case class DebugOptions 158( 159 FPGAPlatform: Boolean = true, 160 EnableDebug: Boolean = true, 161 EnablePerfDebug: Boolean = true, 162 UseDRAMSim: Boolean = false 163) 164 165trait HasXSParameter { 166 167 implicit val p: Parameters 168 169 val coreParams = p(XSCoreParamsKey) 170 val env = p(DebugOptionsKey) 171 172 val XLEN = coreParams.XLEN 173 val hardId = coreParams.HartId 174 val minFLen = 32 175 val fLen = 64 176 def xLen = XLEN 177 178 val HasMExtension = coreParams.HasMExtension 179 val HasCExtension = coreParams.HasCExtension 180 val HasDiv = coreParams.HasDiv 181 val HasIcache = coreParams.HasICache 182 val HasDcache = coreParams.HasDCache 183 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 184 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 185 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 186 val AddrBytes = AddrBits / 8 // unused 187 val DataBits = XLEN 188 val DataBytes = DataBits / 8 189 val HasFPU = coreParams.HasFPU 190 val FetchWidth = coreParams.FetchWidth 191 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 192 val EnableBPU = coreParams.EnableBPU 193 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 194 val EnableRAS = coreParams.EnableRAS 195 val EnableLB = coreParams.EnableLB 196 val EnableLoop = coreParams.EnableLoop 197 val EnableSC = coreParams.EnableSC 198 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 199 val HistoryLength = coreParams.HistoryLength 200 val BtbSize = coreParams.BtbSize 201 // val BtbWays = 4 202 val BtbBanks = PredictWidth 203 // val BtbSets = BtbSize / BtbWays 204 val JbtacSize = coreParams.JbtacSize 205 val JbtacBanks = coreParams.JbtacBanks 206 val RasSize = coreParams.RasSize 207 val CacheLineSize = coreParams.CacheLineSize 208 val CacheLineHalfWord = CacheLineSize / 16 209 val ExtHistoryLength = HistoryLength + 64 210 val UBtbWays = coreParams.UBtbWays 211 val BtbWays = coreParams.BtbWays 212 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 213 val IBufSize = coreParams.IBufSize 214 val DecodeWidth = coreParams.DecodeWidth 215 val RenameWidth = coreParams.RenameWidth 216 val CommitWidth = coreParams.CommitWidth 217 val BrqSize = coreParams.BrqSize 218 val FtqSize = coreParams.FtqSize 219 val IssQueSize = coreParams.IssQueSize 220 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 221 val BrTagWidth = log2Up(BrqSize) 222 val NRPhyRegs = coreParams.NRPhyRegs 223 val PhyRegIdxWidth = log2Up(NRPhyRegs) 224 val RoqSize = coreParams.RoqSize 225 val LoadQueueSize = coreParams.LoadQueueSize 226 val StoreQueueSize = coreParams.StoreQueueSize 227 val dpParams = coreParams.dpParams 228 val exuParameters = coreParams.exuParameters 229 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 230 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 231 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 232 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 233 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 234 val LoadPipelineWidth = coreParams.LoadPipelineWidth 235 val StorePipelineWidth = coreParams.StorePipelineWidth 236 val StoreBufferSize = coreParams.StoreBufferSize 237 val StoreBufferThreshold = coreParams.StoreBufferThreshold 238 val EnableFastForward = coreParams.EnableFastForward 239 val RefillSize = coreParams.RefillSize 240 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 241 val TlbEntrySize = coreParams.TlbEntrySize 242 val TlbSPEntrySize = coreParams.TlbSPEntrySize 243 val l2tlbParams = coreParams.l2tlbParameters 244 val NumPerfCounters = coreParams.NumPerfCounters 245 246 val instBytes = if (HasCExtension) 2 else 4 247 val instOffsetBits = log2Ceil(instBytes) 248 249 val icacheParameters = coreParams.icacheParameters 250 val l1plusCacheParameters = coreParams.l1plusCacheParameters 251 val dcacheParameters = coreParams.dcacheParameters 252 253 val LRSCCycles = 100 254 255 256 // cache hierarchy configurations 257 val l1BusDataWidth = 256 258 259 val usePTWRepeater = coreParams.usePTWRepeater 260 val useFakeDCache = coreParams.useFakeDCache 261 val useFakePTW = coreParams.useFakePTW 262 val useFakeL1plusCache = coreParams.useFakeL1plusCache 263 // L2 configurations 264 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 265 val L1BusWidth = 256 266 val L2Size = coreParams.L2Size 267 val L2BlockSize = 64 268 val L2NWays = coreParams.L2NWays 269 val L2NSets = L2Size / L2BlockSize / L2NWays 270 271 // L3 configurations 272 val L2BusWidth = 256 273 274 // icache prefetcher 275 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 276 enable = true, 277 _type = "stream", 278 streamParams = StreamPrefetchParameters( 279 streamCnt = 2, 280 streamSize = 4, 281 ageWidth = 4, 282 blockBytes = l1plusCacheParameters.blockBytes, 283 reallocStreamOnMissInstantly = true, 284 cacheName = "icache" 285 ) 286 ) 287 288 // dcache prefetcher 289 val l2PrefetcherParameters = L2PrefetcherParameters( 290 enable = true, 291 _type = "bop", // "stream" or "bop" 292 streamParams = StreamPrefetchParameters( 293 streamCnt = 4, 294 streamSize = 4, 295 ageWidth = 4, 296 blockBytes = L2BlockSize, 297 reallocStreamOnMissInstantly = true, 298 cacheName = "dcache" 299 ), 300 bopParams = BOPParameters( 301 rrTableEntries = 256, 302 rrTagBits = 12, 303 scoreBits = 5, 304 roundMax = 50, 305 badScore = 1, 306 blockBytes = L2BlockSize, 307 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 308 ), 309 ) 310 311 // load violation predict 312 val ResetTimeMax2Pow = 20 //1078576 313 val ResetTimeMin2Pow = 10 //1024 314 // wait table parameters 315 val WaitTableSize = 1024 316 val MemPredPCWidth = log2Up(WaitTableSize) 317 val LWTUse2BitCounter = true 318 // store set parameters 319 val SSITSize = WaitTableSize 320 val LFSTSize = 32 321 val SSIDWidth = log2Up(LFSTSize) 322 val LFSTWidth = 4 323 val StoreSetEnable = true // LWT will be disabled if SS is enabled 324 325 val loadExuConfigs = coreParams.loadExuConfigs 326 val storeExuConfigs = coreParams.storeExuConfigs 327 328 val intExuConfigs = coreParams.intExuConfigs 329 330 val fpExuConfigs = coreParams.fpExuConfigs 331 332 val exuConfigs = coreParams.exuConfigs 333 334} 335