xref: /XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala (revision c7160cd3e17f1f3c35393bcf4ee63b39665ec264) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19
20import chipsalliance.rocketchip.config.Parameters
21import chisel3._
22import chisel3.util._
23import xiangshan._
24import utils._
25import xiangshan.backend.rob.RobPtr
26import xiangshan.cache._
27import xiangshan.backend.fu.FenceToSbuffer
28
29object genWmask {
30  def apply(addr: UInt, sizeEncode: UInt): UInt = {
31    (LookupTree(sizeEncode, List(
32      "b00".U -> 0x1.U, //0001 << addr(2:0)
33      "b01".U -> 0x3.U, //0011
34      "b10".U -> 0xf.U, //1111
35      "b11".U -> 0xff.U //11111111
36    )) << addr(2, 0)).asUInt()
37  }
38}
39
40object genWdata {
41  def apply(data: UInt, sizeEncode: UInt): UInt = {
42    LookupTree(sizeEncode, List(
43      "b00".U -> Fill(8, data(7, 0)),
44      "b01".U -> Fill(4, data(15, 0)),
45      "b10".U -> Fill(2, data(31, 0)),
46      "b11".U -> data
47    ))
48  }
49}
50
51class LsPipelineBundle(implicit p: Parameters) extends XSBundle {
52  val vaddr = UInt(VAddrBits.W)
53  val paddr = UInt(PAddrBits.W)
54  val func = UInt(6.W) //fixme???
55  val mask = UInt(8.W)
56  val data = UInt((XLEN+1).W)
57  val uop = new MicroOp
58
59  val miss = Bool()
60  val tlbMiss = Bool()
61  val ptwBack = Bool()
62  val mmio = Bool()
63  val rsIdx = UInt(log2Up(IssQueSize).W)
64
65  val forwardMask = Vec(8, Bool())
66  val forwardData = Vec(8, UInt(8.W))
67
68  // For debug usage
69  val isFirstIssue = Bool()
70  //softprefetch
71  val isSoftPrefetch = Bool()
72  //softprefetch except
73  val isSoftPreExcept = Bool()
74  val isSoftPremmio = Bool()
75}
76
77class StoreDataBundle(implicit p: Parameters) extends XSBundle {
78  val data = UInt((XLEN+1).W)
79  val uop = new MicroOp
80}
81
82class LoadForwardQueryIO(implicit p: Parameters) extends XSBundle {
83  val vaddr = Output(UInt(VAddrBits.W))
84  val paddr = Output(UInt(PAddrBits.W))
85  val mask = Output(UInt(8.W))
86  val uop = Output(new MicroOp) // for replay
87  val pc = Output(UInt(VAddrBits.W)) //for debug
88  val valid = Output(Bool()) //for debug
89
90  val forwardMaskFast = Input(Vec(8, Bool())) // resp to load_s1
91  val forwardMask = Input(Vec(8, Bool())) // resp to load_s2
92  val forwardData = Input(Vec(8, UInt(8.W))) // resp to load_s2
93
94  // val lqIdx = Output(UInt(LoadQueueIdxWidth.W))
95  val sqIdx = Output(new SqPtr)
96
97  // dataInvalid suggests store to load forward found forward should happen,
98  // but data is not available for now. If dataInvalid, load inst should
99  // be replayed from RS. Feedback type should be RSFeedbackType.dataInvalid
100  val dataInvalid = Input(Bool()) // Addr match, but data is not valid for now
101
102  // matchInvalid suggests in store to load forward logic, paddr cam result does
103  // to equal to vaddr cam result. If matchInvalid, a microarchitectural exception
104  // should be raised to flush SQ and committed sbuffer.
105  val matchInvalid = Input(Bool()) // resp to load_s2
106}
107
108// LoadForwardQueryIO used in load pipeline
109//
110// Difference between PipeLoadForwardQueryIO and LoadForwardQueryIO:
111// PipeIO use predecoded sqIdxMask for better forward timing
112class PipeLoadForwardQueryIO(implicit p: Parameters) extends LoadForwardQueryIO {
113  // val sqIdx = Output(new SqPtr) // for debug, should not be used in pipeline for timing reasons
114  // sqIdxMask is calcuated in earlier stage for better timing
115  val sqIdxMask = Output(UInt(StoreQueueSize.W))
116
117  // dataInvalid: addr match, but data is not valid for now
118  val dataInvalidFast = Input(Bool()) // resp to load_s1
119  // val dataInvalid = Input(Bool()) // resp to load_s2
120  val dataInvalidSqIdx = Input(UInt(log2Up(StoreQueueSize).W)) // resp to load_s2, sqIdx value
121}
122
123// // Bundle for load / store wait waking up
124class MemWaitUpdateReq(implicit p: Parameters) extends XSBundle {
125  val staIssue = Vec(exuParameters.StuCnt, ValidIO(new ExuInput))
126  val stdIssue = Vec(exuParameters.StuCnt, ValidIO(new ExuInput))
127}