1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import xiangshan.frontend.{BIM, BasePredictor, BranchPredictionResp, FTB, FakePredictor, ICacheParameters, MicroBTB, RAS, Tage, Tage_SC} 29import xiangshan.cache.mmu.{L2TLBParameters} 30import freechips.rocketchip.diplomacy.AddressSet 31 32case object XSCoreParamsKey extends Field[XSCoreParameters] 33 34case class XSCoreParameters 35( 36 HasPrefetch: Boolean = false, 37 HartId: Int = 0, 38 XLEN: Int = 64, 39 HasMExtension: Boolean = true, 40 HasCExtension: Boolean = true, 41 HasDiv: Boolean = true, 42 HasICache: Boolean = true, 43 HasDCache: Boolean = true, 44 AddrBits: Int = 64, 45 VAddrBits: Int = 39, 46 PAddrBits: Int = 40, 47 HasFPU: Boolean = true, 48 FetchWidth: Int = 8, 49 EnableBPU: Boolean = true, 50 EnableBPD: Boolean = true, 51 EnableRAS: Boolean = true, 52 EnableLB: Boolean = false, 53 EnableLoop: Boolean = true, 54 EnableSC: Boolean = true, 55 EnbaleTlbDebug: Boolean = false, 56 EnableJal: Boolean = false, 57 EnableUBTB: Boolean = true, 58 HistoryLength: Int = 64, 59 PathHistoryLength: Int = 16, 60 BtbSize: Int = 2048, 61 JbtacSize: Int = 1024, 62 JbtacBanks: Int = 8, 63 RasSize: Int = 16, 64 CacheLineSize: Int = 512, 65 UBtbWays: Int = 16, 66 BtbWays: Int = 2, 67 branchPredictor: Function3[BranchPredictionResp, Parameters, Boolean, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 68 ((resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) => { 69 // val loop = Module(new LoopPredictor) 70 // val tage = (if(EnableBPD) { if (EnableSC) Module(new Tage_SC) 71 // else Module(new Tage) } 72 // else { Module(new FakeTage) }) 73 val ftb = Module(new FTB()(p)) 74 val ubtb = Module(new MicroBTB()(p)) 75 val bim = Module(new BIM()(p)) 76 val tage = if (enableSC) { Module(new Tage_SC()(p)) } else { Module(new Tage()(p)) } 77 val ras = Module(new RAS()(p)) 78 // val tage = Module(new Tage()(p)) 79 // val fake = Module(new FakePredictor()(p)) 80 81 // val preds = Seq(loop, tage, btb, ubtb, bim) 82 val preds = Seq(bim, ubtb, tage, ftb, ras) 83 preds.map(_.io := DontCare) 84 85 // ubtb.io.resp_in(0) := resp_in 86 // bim.io.resp_in(0) := ubtb.io.resp 87 // btb.io.resp_in(0) := bim.io.resp 88 // tage.io.resp_in(0) := btb.io.resp 89 // loop.io.resp_in(0) := tage.io.resp 90 bim.io.in.bits.resp_in(0) := resp_in 91 ubtb.io.in.bits.resp_in(0) := bim.io.out.resp 92 tage.io.in.bits.resp_in(0) := ubtb.io.out.resp 93 ftb.io.in.bits.resp_in(0) := tage.io.out.resp 94 ras.io.in.bits.resp_in(0) := ftb.io.out.resp 95 96 (preds, ras.io.out.resp) 97 }), 98 99 100 EnableL1plusPrefetcher: Boolean = true, 101 IBufSize: Int = 48, 102 DecodeWidth: Int = 6, 103 RenameWidth: Int = 6, 104 CommitWidth: Int = 6, 105 BrqSize: Int = 32, 106 FtqSize: Int = 64, 107 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 108 IssQueSize: Int = 16, 109 NRPhyRegs: Int = 160, 110 NRIntReadPorts: Int = 14, 111 NRIntWritePorts: Int = 8, 112 NRFpReadPorts: Int = 14, 113 NRFpWritePorts: Int = 8, 114 LoadQueueSize: Int = 64, 115 StoreQueueSize: Int = 48, 116 RoqSize: Int = 192, 117 EnableIntMoveElim: Boolean = true, 118 IntRefCounterWidth: Int = 2, 119 dpParams: DispatchParameters = DispatchParameters( 120 IntDqSize = 16, 121 FpDqSize = 16, 122 LsDqSize = 16, 123 IntDqDeqWidth = 4, 124 FpDqDeqWidth = 4, 125 LsDqDeqWidth = 4 126 ), 127 exuParameters: ExuParameters = ExuParameters( 128 JmpCnt = 1, 129 AluCnt = 4, 130 MulCnt = 0, 131 MduCnt = 2, 132 FmacCnt = 4, 133 FmiscCnt = 2, 134 FmiscDivSqrtCnt = 0, 135 LduCnt = 2, 136 StuCnt = 2 137 ), 138 LoadPipelineWidth: Int = 2, 139 StorePipelineWidth: Int = 2, 140 StoreBufferSize: Int = 16, 141 StoreBufferThreshold: Int = 7, 142 EnableFastForward: Boolean = true, 143 RefillSize: Int = 512, 144 TlbEntrySize: Int = 32, 145 TlbSPEntrySize: Int = 4, 146 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 147 NumPerfCounters: Int = 16, 148 icacheParameters: ICacheParameters = ICacheParameters( 149 tagECC = Some("parity"), 150 dataECC = Some("parity"), 151 replacer = Some("setplru"), 152 nMissEntries = 2 153 ), 154 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 155 tagECC = Some("secded"), 156 dataECC = Some("secded"), 157 replacer = Some("setplru"), 158 nMissEntries = 8 159 ), 160 dcacheParameters: DCacheParameters = DCacheParameters( 161 tagECC = Some("secded"), 162 dataECC = Some("secded"), 163 replacer = Some("setplru"), 164 nMissEntries = 16, 165 nProbeEntries = 16, 166 nReleaseEntries = 16, 167 nStoreReplayEntries = 16 168 ), 169 L2Size: Int = 512 * 1024, // 512KB 170 L2NWays: Int = 8, 171 usePTWRepeater: Boolean = false, 172 useFakePTW: Boolean = false, 173 useFakeDCache: Boolean = false, 174 useFakeL1plusCache: Boolean = false, 175 useFakeL2Cache: Boolean = false 176){ 177 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 178 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 179 180 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 181 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 182 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 183 184 val fpExuConfigs = 185 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 186 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 187 188 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 189} 190 191case object DebugOptionsKey extends Field[DebugOptions] 192 193case class DebugOptions 194( 195 FPGAPlatform: Boolean = true, 196 EnableDebug: Boolean = true, 197 EnablePerfDebug: Boolean = true, 198 UseDRAMSim: Boolean = false 199) 200 201trait HasXSParameter { 202 203 implicit val p: Parameters 204 205 val coreParams = p(XSCoreParamsKey) 206 val env = p(DebugOptionsKey) 207 208 val XLEN = coreParams.XLEN 209 val hardId = coreParams.HartId 210 val minFLen = 32 211 val fLen = 64 212 def xLen = XLEN 213 214 val HasMExtension = coreParams.HasMExtension 215 val HasCExtension = coreParams.HasCExtension 216 val HasDiv = coreParams.HasDiv 217 val HasIcache = coreParams.HasICache 218 val HasDcache = coreParams.HasDCache 219 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 220 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 221 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 222 val AddrBytes = AddrBits / 8 // unused 223 val DataBits = XLEN 224 val DataBytes = DataBits / 8 225 val HasFPU = coreParams.HasFPU 226 val FetchWidth = coreParams.FetchWidth 227 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 228 val EnableBPU = coreParams.EnableBPU 229 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 230 val EnableRAS = coreParams.EnableRAS 231 val EnableLB = coreParams.EnableLB 232 val EnableLoop = coreParams.EnableLoop 233 val EnableSC = coreParams.EnableSC 234 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 235 val HistoryLength = coreParams.HistoryLength 236 val PathHistoryLength = coreParams.PathHistoryLength 237 val BtbSize = coreParams.BtbSize 238 // val BtbWays = 4 239 val BtbBanks = PredictWidth 240 // val BtbSets = BtbSize / BtbWays 241 val JbtacSize = coreParams.JbtacSize 242 val JbtacBanks = coreParams.JbtacBanks 243 val RasSize = coreParams.RasSize 244 245 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters, enableSC: Boolean) = { 246 coreParams.branchPredictor(resp_in, p, enableSC) 247 } 248 249 val CacheLineSize = coreParams.CacheLineSize 250 val CacheLineHalfWord = CacheLineSize / 16 251 val ExtHistoryLength = HistoryLength + 64 252 val UBtbWays = coreParams.UBtbWays 253 val BtbWays = coreParams.BtbWays 254 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 255 val IBufSize = coreParams.IBufSize 256 val DecodeWidth = coreParams.DecodeWidth 257 val RenameWidth = coreParams.RenameWidth 258 val CommitWidth = coreParams.CommitWidth 259 val BrqSize = coreParams.BrqSize 260 val FtqSize = coreParams.FtqSize 261 val IssQueSize = coreParams.IssQueSize 262 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 263 val BrTagWidth = log2Up(BrqSize) 264 val NRPhyRegs = coreParams.NRPhyRegs 265 val PhyRegIdxWidth = log2Up(NRPhyRegs) 266 val RoqSize = coreParams.RoqSize 267 val EnableIntMoveElim = coreParams.EnableIntMoveElim 268 val IntRefCounterWidth = coreParams.IntRefCounterWidth 269 val StdFreeListSize = NRPhyRegs - 32 270 val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 271 val LoadQueueSize = coreParams.LoadQueueSize 272 val StoreQueueSize = coreParams.StoreQueueSize 273 val dpParams = coreParams.dpParams 274 val exuParameters = coreParams.exuParameters 275 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 276 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 277 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 278 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 279 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 280 val LoadPipelineWidth = coreParams.LoadPipelineWidth 281 val StorePipelineWidth = coreParams.StorePipelineWidth 282 val StoreBufferSize = coreParams.StoreBufferSize 283 val StoreBufferThreshold = coreParams.StoreBufferThreshold 284 val EnableFastForward = coreParams.EnableFastForward 285 val RefillSize = coreParams.RefillSize 286 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 287 val TlbEntrySize = coreParams.TlbEntrySize 288 val TlbSPEntrySize = coreParams.TlbSPEntrySize 289 val l2tlbParams = coreParams.l2tlbParameters 290 val NumPerfCounters = coreParams.NumPerfCounters 291 292 val instBytes = if (HasCExtension) 2 else 4 293 val instOffsetBits = log2Ceil(instBytes) 294 295 val icacheParameters = coreParams.icacheParameters 296 val l1plusCacheParameters = coreParams.l1plusCacheParameters 297 val dcacheParameters = coreParams.dcacheParameters 298 299 val LRSCCycles = 100 300 301 302 // cache hierarchy configurations 303 val l1BusDataWidth = 256 304 305 val usePTWRepeater = coreParams.usePTWRepeater 306 val useFakeDCache = coreParams.useFakeDCache 307 val useFakePTW = coreParams.useFakePTW 308 val useFakeL1plusCache = coreParams.useFakeL1plusCache 309 // L2 configurations 310 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 311 val L1BusWidth = 256 312 val L2Size = coreParams.L2Size 313 val L2BlockSize = 64 314 val L2NWays = coreParams.L2NWays 315 val L2NSets = L2Size / L2BlockSize / L2NWays 316 317 // L3 configurations 318 val L2BusWidth = 256 319 320 // icache prefetcher 321 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 322 enable = true, 323 _type = "stream", 324 streamParams = StreamPrefetchParameters( 325 streamCnt = 2, 326 streamSize = 4, 327 ageWidth = 4, 328 blockBytes = l1plusCacheParameters.blockBytes, 329 reallocStreamOnMissInstantly = true, 330 cacheName = "icache" 331 ) 332 ) 333 334 // dcache prefetcher 335 val l2PrefetcherParameters = L2PrefetcherParameters( 336 enable = true, 337 _type = "bop", // "stream" or "bop" 338 streamParams = StreamPrefetchParameters( 339 streamCnt = 4, 340 streamSize = 4, 341 ageWidth = 4, 342 blockBytes = L2BlockSize, 343 reallocStreamOnMissInstantly = true, 344 cacheName = "dcache" 345 ), 346 bopParams = BOPParameters( 347 rrTableEntries = 256, 348 rrTagBits = 12, 349 scoreBits = 5, 350 roundMax = 50, 351 badScore = 1, 352 blockBytes = L2BlockSize, 353 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 354 ), 355 ) 356 357 // load violation predict 358 val ResetTimeMax2Pow = 20 //1078576 359 val ResetTimeMin2Pow = 10 //1024 360 // wait table parameters 361 val WaitTableSize = 1024 362 val MemPredPCWidth = log2Up(WaitTableSize) 363 val LWTUse2BitCounter = true 364 // store set parameters 365 val SSITSize = WaitTableSize 366 val LFSTSize = 32 367 val SSIDWidth = log2Up(LFSTSize) 368 val LFSTWidth = 4 369 val StoreSetEnable = true // LWT will be disabled if SS is enabled 370 371 val loadExuConfigs = coreParams.loadExuConfigs 372 val storeExuConfigs = coreParams.storeExuConfigs 373 374 val intExuConfigs = coreParams.intExuConfigs 375 376 val fpExuConfigs = coreParams.fpExuConfigs 377 378 val exuConfigs = coreParams.exuConfigs 379 380} 381