1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.{DecodeStage, ImmUnion} 25import xiangshan.backend.rename.{BusyTable, Rename} 26import xiangshan.backend.dispatch.Dispatch 27import xiangshan.backend.exu._ 28import xiangshan.frontend.{FtqRead, FtqToCtrlIO, FtqPtr} 29import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 30import xiangshan.mem.LsqEnqIO 31 32class CtrlToFtqIO(implicit p: Parameters) extends XSBundle { 33 val roq_commits = Vec(CommitWidth, Valid(new RoqCommitInfo)) 34 val stage2Redirect = Valid(new Redirect) 35 val roqFlush = Valid(new Bundle { 36 val ftqIdx = Output(new FtqPtr) 37 val ftqOffset = Output(UInt(log2Up(PredictWidth).W)) 38 }) 39 40 val loadReplay = Valid(new Redirect) 41 val stage3Redirect = ValidIO(new Redirect) 42} 43 44class RedirectGenerator(implicit p: Parameters) extends XSModule 45 with HasCircularQueuePtrHelper { 46 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 47 val io = IO(new Bundle() { 48 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 49 val loadReplay = Flipped(ValidIO(new Redirect)) 50 val flush = Input(Bool()) 51 val stage1PcRead = Vec(numRedirect+1, new FtqRead(UInt(VAddrBits.W))) 52 val stage2Redirect = ValidIO(new Redirect) 53 val stage3Redirect = ValidIO(new Redirect) 54 val memPredUpdate = Output(new MemPredUpdateReq) 55 val memPredPcRead = new FtqRead(UInt(VAddrBits.W)) // read req send form stage 2 56 }) 57 /* 58 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 59 | | | | | | | 60 |============= reg & compare =====| | ======== 61 | | 62 | | 63 | | Stage2 64 | | 65 redirect (flush backend) | 66 | | 67 === reg === | ======== 68 | | 69 |----- mux (exception first) -----| Stage3 70 | 71 redirect (send to frontend) 72 */ 73 private class Wrapper(val n: Int) extends Bundle { 74 val redirect = new Redirect 75 val valid = Bool() 76 val idx = UInt(log2Up(n).W) 77 } 78 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = { 79 val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx))) 80 val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j => 81 (if (j < i) !xs(j).valid || compareVec(i)(j) 82 else if (j == i) xs(i).valid 83 else !xs(j).valid || !compareVec(j)(i)) 84 )).andR)) 85 resultOnehot 86 } 87 88 val redirects = io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 89 val stage1FtqReadPcs = 90 (io.stage1PcRead zip redirects).map{ case (r, redirect) => 91 r(redirect.ftqIdx, redirect.ftqOffset) 92 } 93 94 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 95 val redirect = Wire(Valid(new Redirect)) 96 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 97 redirect.bits := exuOut.bits.redirect 98 redirect 99 } 100 101 val jumpOut = io.exuMispredict.head 102 val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay) 103 val oldestOneHot = selectOldestRedirect(allRedirect) 104 val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush))) 105 val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR 106 val oldestExuOutput = Mux1H(io.exuMispredict.indices.map(oldestOneHot), io.exuMispredict) 107 val oldestRedirect = Mux1H(oldestOneHot, allRedirect) 108 109 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 110 val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0)) 111 val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd) 112 val s1_redirect_bits_reg = RegNext(oldestRedirect.bits) 113 val s1_redirect_valid_reg = RegNext(oldestValid) 114 val s1_redirect_onehot = RegNext(oldestOneHot) 115 116 // stage1 -> stage2 117 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 118 io.stage2Redirect.bits := s1_redirect_bits_reg 119 io.stage2Redirect.bits.cfiUpdate := DontCare 120 121 val s1_isReplay = s1_redirect_onehot.last 122 val s1_isJump = s1_redirect_onehot.head 123 val real_pc = Mux1H(s1_redirect_onehot, stage1FtqReadPcs) 124 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 125 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 126 val target = Mux(s1_isReplay, 127 real_pc, // repaly from itself 128 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 129 Mux(s1_isJump, s1_jumpTarget, brTarget), 130 snpc 131 ) 132 ) 133 134 // get pc from ftq 135 // valid only if redirect is caused by load violation 136 // store_pc is used to update store set 137 val store_pc = io.memPredPcRead(s1_redirect_bits_reg.stFtqIdx, s1_redirect_bits_reg.stFtqOffset) 138 139 // update load violation predictor if load violation redirect triggered 140 io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B) 141 // update wait table 142 io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 143 io.memPredUpdate.wdata := true.B 144 // update store set 145 io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 146 // store pc is ready 1 cycle after s1_isReplay is judged 147 io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth) 148 149 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 150 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 151 val s2_pc = RegEnable(real_pc, enable = s1_redirect_valid_reg) 152 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 153 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 154 155 io.stage3Redirect.valid := s2_redirect_valid_reg 156 io.stage3Redirect.bits := s2_redirect_bits_reg 157 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 158 stage3CfiUpdate.pc := s2_pc 159 stage3CfiUpdate.pd := s2_pd 160 // stage3CfiUpdate.rasSp := s2_ftqRead.rasSp 161 // stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop 162 // stage3CfiUpdate.predHist := s2_ftqRead.predHist 163 // stage3CfiUpdate.specCnt := s2_ftqRead.specCnt 164 // stage3CfiUpdate.hist := s2_hist 165 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 166 // stage3CfiUpdate.br_hit := s2_sawNotTakenBranch 167 stage3CfiUpdate.target := s2_target 168 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 169 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 170} 171 172class CtrlBlock(implicit p: Parameters) extends XSModule 173 with HasCircularQueuePtrHelper { 174 val io = IO(new Bundle { 175 val frontend = Flipped(new FrontendToCtrlIO) 176 val enqIQ = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp)) 177 // from int block 178 val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput))) 179 val stIn = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuInput))) 180 val stOut = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuOutput))) 181 val memoryViolation = Flipped(ValidIO(new Redirect)) 182 val enqLsq = Flipped(new LsqEnqIO) 183 val jumpPc = Output(UInt(VAddrBits.W)) 184 val jalr_target = Output(UInt(VAddrBits.W)) 185 val roqio = new Bundle { 186 // to int block 187 val toCSR = new RoqCSRIO 188 val exception = ValidIO(new ExceptionInfo) 189 // to mem block 190 val lsq = new RoqLsqIO 191 } 192 val csrCtrl = Input(new CustomCSRCtrlIO) 193 val perfInfo = Output(new Bundle{ 194 val ctrlInfo = new Bundle { 195 val roqFull = Input(Bool()) 196 val intdqFull = Input(Bool()) 197 val fpdqFull = Input(Bool()) 198 val lsdqFull = Input(Bool()) 199 } 200 }) 201 val writeback = Vec(NRIntWritePorts + NRFpWritePorts, Flipped(ValidIO(new ExuOutput))) 202 // redirect out 203 val redirect = ValidIO(new Redirect) 204 val flush = Output(Bool()) 205 val readIntRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 206 val readFpRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 207 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 208 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 209 }) 210 211 val decode = Module(new DecodeStage) 212 val rename = Module(new Rename) 213 val dispatch = Module(new Dispatch) 214 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 215 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 216 val redirectGen = Module(new RedirectGenerator) 217 218 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 219 val roq = Module(new Roq(roqWbSize)) 220 221 val stage2Redirect = redirectGen.io.stage2Redirect 222 val stage3Redirect = redirectGen.io.stage3Redirect 223 val flush = roq.io.flushOut.valid 224 val flushReg = RegNext(flush) 225 226 val exuRedirect = io.exuRedirect.map(x => { 227 val valid = x.valid && x.bits.redirectValid 228 val killedByOlder = x.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg) 229 val delayed = Wire(Valid(new ExuOutput)) 230 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 231 delayed.bits := RegEnable(x.bits, x.valid) 232 delayed 233 }) 234 val loadReplay = Wire(Valid(new Redirect)) 235 loadReplay.valid := RegNext(io.memoryViolation.valid && 236 !io.memoryViolation.bits.roqIdx.needFlush(stage2Redirect, flushReg), 237 init = false.B 238 ) 239 loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid) 240 io.frontend.fromFtq.getRedirectPcRead <> redirectGen.io.stage1PcRead 241 io.frontend.fromFtq.getMemPredPcRead <> redirectGen.io.memPredPcRead 242 redirectGen.io.exuMispredict <> exuRedirect 243 redirectGen.io.loadReplay <> loadReplay 244 redirectGen.io.flush := flushReg 245 246 for(i <- 0 until CommitWidth){ 247 io.frontend.toFtq.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 248 io.frontend.toFtq.roq_commits(i).bits := roq.io.commits.info(i) 249 } 250 io.frontend.toFtq.stage2Redirect <> stage2Redirect 251 io.frontend.toFtq.roqFlush <> RegNext(roq.io.flushOut) 252 io.frontend.toFtq.stage3Redirect <> stage3Redirect 253 io.frontend.toFtq.loadReplay <> loadReplay 254 255 val roqPcRead = io.frontend.fromFtq.getRoqFlushPcRead 256 val flushPC = roqPcRead(roq.io.flushOut.bits.ftqIdx, roq.io.flushOut.bits.ftqOffset) 257 258 val flushRedirect = Wire(Valid(new Redirect)) 259 flushRedirect.valid := flushReg 260 flushRedirect.bits := DontCare 261 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 262 flushRedirect.bits.interrupt := true.B 263 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 264 io.roqio.toCSR.trapTarget, 265 flushPC + 4.U // flush pipe 266 ) 267 val flushRedirectReg = Wire(Valid(new Redirect)) 268 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 269 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 270 271 io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, stage3Redirect) 272 273 decode.io.in <> io.frontend.cfVec 274 // currently, we only update wait table when isReplay 275 decode.io.memPredUpdate(0) <> RegNext(redirectGen.io.memPredUpdate) 276 decode.io.memPredUpdate(1) := DontCare 277 decode.io.memPredUpdate(1).valid := false.B 278 // decode.io.memPredUpdate <> io.toLsBlock.memPredUpdate 279 decode.io.csrCtrl := RegNext(io.csrCtrl) 280 281 282 val jumpInst = dispatch.io.enqIQCtrl(0).bits 283 val jumpPcRead = io.frontend.fromFtq.getJumpPcRead 284 io.jumpPc := jumpPcRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 285 val jumpTargetRead = io.frontend.fromFtq.target_read 286 io.jalr_target := jumpTargetRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 287 288 // pipeline between decode and dispatch 289 for (i <- 0 until RenameWidth) { 290 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 291 flushReg || io.frontend.redirect_cfiUpdate.valid) 292 } 293 294 rename.io.redirect <> stage2Redirect 295 rename.io.flush := flushReg 296 rename.io.roqCommits <> roq.io.commits 297 rename.io.out <> dispatch.io.fromRename 298 rename.io.renameBypass <> dispatch.io.renameBypass 299 rename.io.dispatchInfo <> dispatch.io.preDpInfo 300 rename.io.csrCtrl <> RegNext(io.csrCtrl) 301 302 dispatch.io.redirect <> stage2Redirect 303 dispatch.io.flush := flushReg 304 dispatch.io.enqRoq <> roq.io.enq 305 dispatch.io.enqLsq <> io.enqLsq 306 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 307 intBusyTable.io.allocPregs(i).valid := preg.isInt 308 fpBusyTable.io.allocPregs(i).valid := preg.isFp 309 intBusyTable.io.allocPregs(i).bits := preg.preg 310 fpBusyTable.io.allocPregs(i).bits := preg.preg 311 } 312 dispatch.io.enqIQCtrl := DontCare 313 io.enqIQ <> dispatch.io.enqIQCtrl 314 dispatch.io.csrCtrl <> io.csrCtrl 315 dispatch.io.storeIssue <> io.stIn 316 dispatch.io.readIntRf <> io.readIntRf 317 dispatch.io.readFpRf <> io.readFpRf 318 319 fpBusyTable.io.flush := flushReg 320 intBusyTable.io.flush := flushReg 321 for((wb, setPhyRegRdy) <- io.writeback.take(NRIntWritePorts).zip(intBusyTable.io.wbPregs)){ 322 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 323 setPhyRegRdy.bits := wb.bits.uop.pdest 324 } 325 for((wb, setPhyRegRdy) <- io.writeback.drop(NRIntWritePorts).zip(fpBusyTable.io.wbPregs)){ 326 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 327 setPhyRegRdy.bits := wb.bits.uop.pdest 328 } 329 intBusyTable.io.read <> dispatch.io.readIntState 330 fpBusyTable.io.read <> dispatch.io.readFpState 331 332 roq.io.redirect <> stage2Redirect 333 val exeWbResults = VecInit(io.writeback ++ io.stOut) 334 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 335 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg)) 336 roq_wb.bits := RegNext(wb.bits) 337 } 338 339 // TODO: is 'backendRedirect' necesscary? 340 io.redirect <> stage2Redirect 341 io.flush <> flushReg 342 io.debug_int_rat <> rename.io.debug_int_rat 343 io.debug_fp_rat <> rename.io.debug_fp_rat 344 345// dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 346// dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 347 348 // roq to int block 349 io.roqio.toCSR <> roq.io.csr 350 io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr) 351 io.roqio.exception := roq.io.exception 352 io.roqio.exception.bits.uop.cf.pc := flushPC 353 // roq to mem block 354 io.roqio.lsq <> roq.io.lsq 355 356 io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull) 357 io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull) 358 io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull) 359 io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull) 360} 361