1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.ImmUnion 25import xiangshan.cache._ 26import xiangshan.cache.mmu.{TlbRequestIO, TlbReq, TlbResp, TlbCmd} 27 28class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 29 val loadIn = ValidIO(new LsPipelineBundle) 30 val ldout = Flipped(DecoupledIO(new ExuOutput)) 31 val loadDataForwarded = Output(Bool()) 32 val needReplayFromRS = Output(Bool()) 33 val forward = new PipeLoadForwardQueryIO 34} 35 36// Load Pipeline Stage 0 37// Generate addr, use addr to query DCache and DTLB 38class LoadUnit_S0(implicit p: Parameters) extends XSModule { 39 val io = IO(new Bundle() { 40 val in = Flipped(Decoupled(new ExuInput)) 41 val out = Decoupled(new LsPipelineBundle) 42 val dtlbReq = DecoupledIO(new TlbReq) 43 val dcacheReq = DecoupledIO(new DCacheWordReq) 44 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 45 val isFirstIssue = Input(Bool()) 46 }) 47 48 val s0_uop = io.in.bits.uop 49 // val s0_vaddr = io.in.bits.src(0) + SignExt(s0_uop.ctrl.imm(11,0), VAddrBits) 50 // val s0_mask = genWmask(s0_vaddr, s0_uop.ctrl.fuOpType(1,0)) 51 val imm12 = WireInit(s0_uop.ctrl.imm(11,0)) 52 val s0_vaddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 53 val s0_vaddr_hi = Mux(s0_vaddr_lo(12), 54 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 55 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 56 ) 57 val s0_vaddr = Cat(s0_vaddr_hi, s0_vaddr_lo(11,0)) 58 val s0_mask = genWmask(s0_vaddr_lo, s0_uop.ctrl.fuOpType(1,0)) 59 60 // query DTLB 61 io.dtlbReq.valid := io.in.valid 62 io.dtlbReq.bits.vaddr := s0_vaddr 63 io.dtlbReq.bits.cmd := TlbCmd.read 64 io.dtlbReq.bits.roqIdx := s0_uop.roqIdx 65 io.dtlbReq.bits.debug.pc := s0_uop.cf.pc 66 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 67 68 // query DCache 69 io.dcacheReq.valid := io.in.valid 70 io.dcacheReq.bits.cmd := MemoryOpConstants.M_XRD 71 io.dcacheReq.bits.addr := s0_vaddr 72 io.dcacheReq.bits.mask := s0_mask 73 io.dcacheReq.bits.data := DontCare 74 75 // TODO: update cache meta 76 io.dcacheReq.bits.id := DontCare 77 78 val addrAligned = LookupTree(s0_uop.ctrl.fuOpType(1, 0), List( 79 "b00".U -> true.B, //b 80 "b01".U -> (s0_vaddr(0) === 0.U), //h 81 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 82 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 83 )) 84 85 io.out.valid := io.in.valid && io.dcacheReq.ready 86 87 io.out.bits := DontCare 88 io.out.bits.vaddr := s0_vaddr 89 io.out.bits.mask := s0_mask 90 io.out.bits.uop := s0_uop 91 io.out.bits.uop.cf.exceptionVec(loadAddrMisaligned) := !addrAligned 92 io.out.bits.rsIdx := io.rsIdx 93 94 io.in.ready := !io.in.valid || (io.out.ready && io.dcacheReq.ready) 95 96 XSDebug(io.dcacheReq.fire(), 97 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.cf.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 98 ) 99 XSPerfAccumulate("in", io.in.valid) 100 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready && io.dcacheReq.ready) 101 XSPerfAccumulate("stall_dcache", io.out.valid && io.out.ready && !io.dcacheReq.ready) 102 XSPerfAccumulate("addr_spec_success", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 103 XSPerfAccumulate("addr_spec_failed", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 104 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 105 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && s0_vaddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 106} 107 108 109// Load Pipeline Stage 1 110// TLB resp (send paddr to dcache) 111class LoadUnit_S1(implicit p: Parameters) extends XSModule { 112 val io = IO(new Bundle() { 113 val in = Flipped(Decoupled(new LsPipelineBundle)) 114 val out = Decoupled(new LsPipelineBundle) 115 val dtlbResp = Flipped(DecoupledIO(new TlbResp)) 116 val dcachePAddr = Output(UInt(PAddrBits.W)) 117 val dcacheKill = Output(Bool()) 118 val fullForwardFast = Output(Bool()) 119 val sbuffer = new LoadForwardQueryIO 120 val lsq = new PipeLoadForwardQueryIO 121 }) 122 123 val s1_uop = io.in.bits.uop 124 val s1_paddr = io.dtlbResp.bits.paddr 125 val s1_exception = selectLoad(io.out.bits.uop.cf.exceptionVec, false).asUInt.orR 126 val s1_tlb_miss = io.dtlbResp.bits.miss 127 val s1_mmio = !s1_tlb_miss && io.dtlbResp.bits.mmio 128 val s1_mask = io.in.bits.mask 129 130 io.out.bits := io.in.bits // forwardXX field will be updated in s1 131 132 io.dtlbResp.ready := true.B 133 134 // TOOD: PMA check 135 io.dcachePAddr := s1_paddr 136 io.dcacheKill := s1_tlb_miss || s1_exception || s1_mmio 137 138 // load forward query datapath 139 io.sbuffer.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 140 io.sbuffer.vaddr := io.in.bits.vaddr 141 io.sbuffer.paddr := s1_paddr 142 io.sbuffer.uop := s1_uop 143 io.sbuffer.sqIdx := s1_uop.sqIdx 144 io.sbuffer.mask := s1_mask 145 io.sbuffer.pc := s1_uop.cf.pc // FIXME: remove it 146 147 io.lsq.valid := io.in.valid && !(s1_exception || s1_tlb_miss) 148 io.lsq.vaddr := io.in.bits.vaddr 149 io.lsq.paddr := s1_paddr 150 io.lsq.uop := s1_uop 151 io.lsq.sqIdx := s1_uop.sqIdx 152 io.lsq.sqIdxMask := DontCare // will be overwritten by sqIdxMask pre-generated in s0 153 io.lsq.mask := s1_mask 154 io.lsq.pc := s1_uop.cf.pc // FIXME: remove it 155 156 // Generate forwardMaskFast to wake up insts earlier 157 val forwardMaskFast = io.lsq.forwardMaskFast.asUInt | io.sbuffer.forwardMaskFast.asUInt 158 io.fullForwardFast := (~forwardMaskFast & s1_mask) === 0.U 159 160 161 io.out.valid := io.in.valid// && !s1_tlb_miss 162 io.out.bits.paddr := s1_paddr 163 io.out.bits.mmio := s1_mmio && !s1_exception 164 io.out.bits.tlbMiss := s1_tlb_miss 165 io.out.bits.uop.cf.exceptionVec(loadPageFault) := io.dtlbResp.bits.excp.pf.ld 166 io.out.bits.uop.cf.exceptionVec(loadAccessFault) := io.dtlbResp.bits.excp.af.ld 167 io.out.bits.ptwBack := io.dtlbResp.bits.ptwBack 168 io.out.bits.rsIdx := io.in.bits.rsIdx 169 170 io.in.ready := !io.in.valid || io.out.ready 171 172 XSPerfAccumulate("in", io.in.valid) 173 XSPerfAccumulate("tlb_miss", io.in.valid && s1_tlb_miss) 174 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 175} 176 177 178// Load Pipeline Stage 2 179// DCache resp 180class LoadUnit_S2(implicit p: Parameters) extends XSModule with HasLoadHelper { 181 val io = IO(new Bundle() { 182 val in = Flipped(Decoupled(new LsPipelineBundle)) 183 val out = Decoupled(new LsPipelineBundle) 184 val rsFeedback = ValidIO(new RSFeedback) 185 val dcacheResp = Flipped(DecoupledIO(new DCacheWordResp)) 186 val lsq = new LoadForwardQueryIO 187 val sbuffer = new LoadForwardQueryIO 188 val dataForwarded = Output(Bool()) 189 val needReplayFromRS = Output(Bool()) 190 }) 191 192 val s2_uop = io.in.bits.uop 193 val s2_mask = io.in.bits.mask 194 val s2_paddr = io.in.bits.paddr 195 val s2_tlb_miss = io.in.bits.tlbMiss 196 val s2_data_invalid = io.lsq.dataInvalid 197 val s2_exception = selectLoad(io.in.bits.uop.cf.exceptionVec, false).asUInt.orR 198 val s2_mmio = io.in.bits.mmio && !s2_exception 199 val s2_cache_miss = io.dcacheResp.bits.miss 200 val s2_cache_replay = io.dcacheResp.bits.replay 201 202 // val cnt = RegInit(127.U) 203 // cnt := cnt + io.in.valid.asUInt 204 // val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid || cnt === 0.U 205 206 val s2_forward_fail = io.lsq.matchInvalid || io.sbuffer.matchInvalid 207 208 // assert(!s2_forward_fail) 209 210 io.dcacheResp.ready := true.B 211 val dcacheShouldResp = !(s2_tlb_miss || s2_exception || s2_mmio) 212 assert(!(io.in.valid && dcacheShouldResp && !io.dcacheResp.valid), "DCache response got lost") 213 214 // merge forward result 215 // lsq has higher priority than sbuffer 216 val forwardMask = Wire(Vec(8, Bool())) 217 val forwardData = Wire(Vec(8, UInt(8.W))) 218 219 val fullForward = (~forwardMask.asUInt & s2_mask) === 0.U && !io.lsq.dataInvalid 220 io.lsq := DontCare 221 io.sbuffer := DontCare 222 223 // generate XLEN/8 Muxs 224 for (i <- 0 until XLEN / 8) { 225 forwardMask(i) := io.lsq.forwardMask(i) || io.sbuffer.forwardMask(i) 226 forwardData(i) := Mux(io.lsq.forwardMask(i), io.lsq.forwardData(i), io.sbuffer.forwardData(i)) 227 } 228 229 XSDebug(io.out.fire(), "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 230 s2_uop.cf.pc, 231 io.lsq.forwardData.asUInt, io.lsq.forwardMask.asUInt, 232 io.in.bits.forwardData.asUInt, io.in.bits.forwardMask.asUInt 233 ) 234 235 // data merge 236 val rdataVec = VecInit((0 until XLEN / 8).map(j => 237 Mux(forwardMask(j), forwardData(j), io.dcacheResp.bits.data(8*(j+1)-1, 8*j)))) 238 val rdata = rdataVec.asUInt 239 val rdataSel = LookupTree(s2_paddr(2, 0), List( 240 "b000".U -> rdata(63, 0), 241 "b001".U -> rdata(63, 8), 242 "b010".U -> rdata(63, 16), 243 "b011".U -> rdata(63, 24), 244 "b100".U -> rdata(63, 32), 245 "b101".U -> rdata(63, 40), 246 "b110".U -> rdata(63, 48), 247 "b111".U -> rdata(63, 56) 248 )) 249 val rdataPartialLoad = rdataHelper(s2_uop, rdataSel) 250 251 io.out.valid := io.in.valid && !s2_tlb_miss && !s2_data_invalid 252 // Inst will be canceled in store queue / lsq, 253 // so we do not need to care about flush in load / store unit's out.valid 254 io.out.bits := io.in.bits 255 io.out.bits.data := rdataPartialLoad 256 // when exception occurs, set it to not miss and let it write back to roq (via int port) 257 if (EnableFastForward) { 258 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail && !fullForward 259 } else { 260 io.out.bits.miss := s2_cache_miss && !s2_exception && !s2_forward_fail 261 } 262 io.out.bits.uop.ctrl.fpWen := io.in.bits.uop.ctrl.fpWen && !s2_exception 263 io.out.bits.uop.cf.replayInst := s2_forward_fail && !s2_mmio // if forward fail, repaly this inst 264 io.out.bits.mmio := s2_mmio 265 266 // For timing reasons, sometimes we can not let 267 // io.out.bits.miss := s2_cache_miss && !s2_exception && !fullForward 268 // We use io.dataForwarded instead. It means forward logic have prepared all data needed, 269 // and dcache query is no longer needed. 270 // Such inst will be writebacked from load queue. 271 io.dataForwarded := s2_cache_miss && fullForward && !s2_exception && !s2_forward_fail 272 // io.out.bits.forwardX will be send to lq 273 io.out.bits.forwardMask := forwardMask 274 // data retbrived from dcache is also included in io.out.bits.forwardData 275 io.out.bits.forwardData := rdataVec 276 277 io.in.ready := io.out.ready || !io.in.valid 278 279 // feedback tlb result to RS 280 io.rsFeedback.valid := io.in.valid 281 io.rsFeedback.bits.hit := !s2_tlb_miss && (!s2_cache_replay || s2_mmio || s2_exception || fullForward) && !s2_data_invalid 282 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 283 io.rsFeedback.bits.flushState := io.in.bits.ptwBack 284 io.rsFeedback.bits.sourceType := Mux(s2_tlb_miss, RSFeedbackType.tlbMiss, 285 Mux(io.lsq.dataInvalid, 286 RSFeedbackType.dataInvalid, 287 RSFeedbackType.mshrFull 288 ) 289 ) 290 291 // s2_cache_replay is quite slow to generate, send it separately to LQ 292 io.needReplayFromRS := s2_cache_replay && !fullForward 293 294 XSDebug(io.out.fire(), "[DCACHE LOAD RESP] pc %x rdata %x <- D$ %x + fwd %x(%b)\n", 295 s2_uop.cf.pc, rdataPartialLoad, io.dcacheResp.bits.data, 296 forwardData.asUInt, forwardMask.asUInt 297 ) 298 299 XSPerfAccumulate("in", io.in.valid) 300 XSPerfAccumulate("dcache_miss", io.in.valid && s2_cache_miss) 301 XSPerfAccumulate("full_forward", io.in.valid && fullForward) 302 XSPerfAccumulate("dcache_miss_full_forward", io.in.valid && s2_cache_miss && fullForward) 303 XSPerfAccumulate("replay", io.rsFeedback.valid && !io.rsFeedback.bits.hit) 304 XSPerfAccumulate("replay_tlb_miss", io.rsFeedback.valid && !io.rsFeedback.bits.hit && s2_tlb_miss) 305 XSPerfAccumulate("replay_cache", io.rsFeedback.valid && !io.rsFeedback.bits.hit && !s2_tlb_miss && s2_cache_replay) 306 XSPerfAccumulate("stall_out", io.out.valid && !io.out.ready) 307} 308 309class LoadUnit(implicit p: Parameters) extends XSModule with HasLoadHelper { 310 val io = IO(new Bundle() { 311 val ldin = Flipped(Decoupled(new ExuInput)) 312 val ldout = Decoupled(new ExuOutput) 313 val redirect = Flipped(ValidIO(new Redirect)) 314 val flush = Input(Bool()) 315 val rsFeedback = ValidIO(new RSFeedback) 316 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 317 val isFirstIssue = Input(Bool()) 318 val dcache = new DCacheLoadIO 319 val dtlb = new TlbRequestIO() 320 val sbuffer = new LoadForwardQueryIO 321 val lsq = new LoadToLsqIO 322 val fastUop = ValidIO(new MicroOp) // early wakeup signal generated in load_s1 323 }) 324 325 val load_s0 = Module(new LoadUnit_S0) 326 val load_s1 = Module(new LoadUnit_S1) 327 val load_s2 = Module(new LoadUnit_S2) 328 329 load_s0.io.in <> io.ldin 330 load_s0.io.dtlbReq <> io.dtlb.req 331 load_s0.io.dcacheReq <> io.dcache.req 332 load_s0.io.rsIdx := io.rsIdx 333 load_s0.io.isFirstIssue := io.isFirstIssue 334 335 PipelineConnect(load_s0.io.out, load_s1.io.in, true.B, load_s0.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 336 337 load_s1.io.dtlbResp <> io.dtlb.resp 338 io.dcache.s1_paddr <> load_s1.io.dcachePAddr 339 io.dcache.s1_kill <> load_s1.io.dcacheKill 340 load_s1.io.sbuffer <> io.sbuffer 341 load_s1.io.lsq <> io.lsq.forward 342 343 PipelineConnect(load_s1.io.out, load_s2.io.in, true.B, load_s1.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 344 345 load_s2.io.dcacheResp <> io.dcache.resp 346 load_s2.io.lsq.forwardData <> io.lsq.forward.forwardData 347 load_s2.io.lsq.forwardMask <> io.lsq.forward.forwardMask 348 load_s2.io.lsq.forwardMaskFast <> io.lsq.forward.forwardMaskFast // should not be used in load_s2 349 load_s2.io.lsq.dataInvalid <> io.lsq.forward.dataInvalid 350 load_s2.io.lsq.matchInvalid <> io.lsq.forward.matchInvalid 351 load_s2.io.sbuffer.forwardData <> io.sbuffer.forwardData 352 load_s2.io.sbuffer.forwardMask <> io.sbuffer.forwardMask 353 load_s2.io.sbuffer.forwardMaskFast <> io.sbuffer.forwardMaskFast // should not be used in load_s2 354 load_s2.io.sbuffer.dataInvalid <> io.sbuffer.dataInvalid // always false 355 load_s2.io.sbuffer.matchInvalid <> io.sbuffer.matchInvalid 356 load_s2.io.dataForwarded <> io.lsq.loadDataForwarded 357 io.rsFeedback.bits := RegNext(load_s2.io.rsFeedback.bits) 358 io.rsFeedback.valid := RegNext(load_s2.io.rsFeedback.valid && !load_s2.io.out.bits.uop.roqIdx.needFlush(io.redirect, io.flush)) 359 io.lsq.needReplayFromRS := load_s2.io.needReplayFromRS 360 361 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 362 val sqIdxMaskReg = RegNext(UIntToMask(load_s0.io.in.bits.uop.sqIdx.value, StoreQueueSize)) 363 io.lsq.forward.sqIdxMask := sqIdxMaskReg 364 365 // // use s2_hit_way to select data received in s1 366 // load_s2.io.dcacheResp.bits.data := Mux1H(RegNext(io.dcache.s1_hit_way), RegNext(io.dcache.s1_data)) 367 // assert(load_s2.io.dcacheResp.bits.data === io.dcache.resp.bits.data) 368 369 io.fastUop.valid := io.dcache.s1_hit_way.orR && // dcache hit 370 !io.dcache.s1_disable_fast_wakeup && // load fast wakeup should be disabled when dcache data read is not ready 371 load_s1.io.in.valid && // valid laod request 372 !load_s1.io.dcacheKill && // not mmio or tlb miss 373 !io.lsq.forward.dataInvalidFast // forward failed 374 io.fastUop.bits := load_s1.io.out.bits.uop 375 376 XSDebug(load_s0.io.out.valid, 377 p"S0: pc ${Hexadecimal(load_s0.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s0.io.out.bits.uop.lqIdx.asUInt)}, " + 378 p"vaddr ${Hexadecimal(load_s0.io.out.bits.vaddr)}, mask ${Hexadecimal(load_s0.io.out.bits.mask)}\n") 379 XSDebug(load_s1.io.out.valid, 380 p"S1: pc ${Hexadecimal(load_s1.io.out.bits.uop.cf.pc)}, lId ${Hexadecimal(load_s1.io.out.bits.uop.lqIdx.asUInt)}, tlb_miss ${io.dtlb.resp.bits.miss}, " + 381 p"paddr ${Hexadecimal(load_s1.io.out.bits.paddr)}, mmio ${load_s1.io.out.bits.mmio}\n") 382 383 // writeback to LSQ 384 // Current dcache use MSHR 385 // Load queue will be updated at s2 for both hit/miss int/fp load 386 io.lsq.loadIn.valid := load_s2.io.out.valid 387 io.lsq.loadIn.bits := load_s2.io.out.bits 388 389 // write to rob and writeback bus 390 val s2_wb_valid = load_s2.io.out.valid && !load_s2.io.out.bits.miss && !load_s2.io.out.bits.mmio 391 392 // Int load, if hit, will be writebacked at s2 393 val hitLoadOut = Wire(Valid(new ExuOutput)) 394 hitLoadOut.valid := s2_wb_valid 395 hitLoadOut.bits.uop := load_s2.io.out.bits.uop 396 hitLoadOut.bits.data := load_s2.io.out.bits.data 397 hitLoadOut.bits.redirectValid := false.B 398 hitLoadOut.bits.redirect := DontCare 399 hitLoadOut.bits.debug.isMMIO := load_s2.io.out.bits.mmio 400 hitLoadOut.bits.debug.isPerfCnt := false.B 401 hitLoadOut.bits.debug.paddr := load_s2.io.out.bits.paddr 402 hitLoadOut.bits.fflags := DontCare 403 404 load_s2.io.out.ready := true.B 405 406 io.ldout.bits := Mux(hitLoadOut.valid, hitLoadOut.bits, io.lsq.ldout.bits) 407 io.ldout.valid := hitLoadOut.valid || io.lsq.ldout.valid 408 409 io.lsq.ldout.ready := !hitLoadOut.valid 410 411 when(io.ldout.fire()){ 412 XSDebug("ldout %x\n", io.ldout.bits.uop.cf.pc) 413 } 414} 415