xref: /XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FPU.scala (revision dc597826530cb6803c2396d6ab0e5eb176b732e0) 
1package xiangshan.backend.fu.fpu
2
3import chisel3._
4import chisel3.util._
5import fudian.FloatPoint
6
7object FPU {
8
9  case class FType(expWidth: Int, precision: Int) {
10    val sigWidth = precision - 1
11    val len = expWidth + precision
12  }
13
14  val f32 = FType(8, 24)
15  val f64 = FType(11, 53)
16
17  val ftypes = List(f32, f64)
18
19  val S = ftypes.indexOf(f32).U(log2Ceil(ftypes.length).W)
20  val D = ftypes.indexOf(f64).U(log2Ceil(ftypes.length).W)
21
22  def unbox(x: UInt, typeTag: UInt): UInt = {
23    require(x.getWidth == 64)
24    val isBoxed = x.head(32).andR()
25    Mux(typeTag === D,
26      x,
27      Mux(isBoxed,
28        x.tail(32),
29        FloatPoint.defaultNaNUInt(f32.expWidth, f32.precision)
30      )
31    )
32  }
33
34  def box(x: UInt, typeTag: UInt): UInt = {
35    require(x.getWidth == 64)
36    Mux(typeTag === D, x, Cat(~0.U(32.W), x(31, 0)))
37  }
38
39}
40