1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chisel3._ 20import chisel3.util._ 21import xiangshan._ 22import utils._ 23import system._ 24import chipsalliance.rocketchip.config._ 25import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen} 26import xiangshan.frontend.{ICacheParameters} 27import freechips.rocketchip.devices.debug._ 28import freechips.rocketchip.tile.MaxHartIdBits 29import sifive.blocks.inclusivecache.{InclusiveCache, InclusiveCacheMicroParameters, CacheParameters} 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.exu.ExuParameters 32import xiangshan.backend.dispatch.DispatchParameters 33import xiangshan.cache.{DCacheParameters, L1plusCacheParameters} 34import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 35import xiangshan.cache.mmu.{L2TLBParameters} 36import device.{XSDebugModuleParams, EnableJtag} 37 38class DefaultConfig(n: Int) extends Config((site, here, up) => { 39 case XLen => 64 40 case DebugOptionsKey => DebugOptions() 41 case SoCParamsKey => SoCParameters( 42 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) } 43 ) 44 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 45 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 46 case JtagDTMKey => JtagDTMKey 47 case MaxHartIdBits => 2 48 case EnableJtag => false.B 49}) 50 51// Synthesizable minimal XiangShan 52// * It is still an out-of-order, super-scalaer arch 53// * L1 cache included 54// * L2 cache NOT included 55// * L3 cache included 56class MinimalConfig(n: Int = 1) extends Config( 57 new DefaultConfig(n).alter((site, here, up) => { 58 case SoCParamsKey => up(SoCParamsKey).copy( 59 cores = up(SoCParamsKey).cores.map(_.copy( 60 DecodeWidth = 2, 61 RenameWidth = 2, 62 FetchWidth = 4, 63 IssQueSize = 8, 64 NRPhyRegs = 64, 65 LoadQueueSize = 16, 66 StoreQueueSize = 12, 67 RoqSize = 32, 68 BrqSize = 8, 69 FtqSize = 8, 70 IBufSize = 16, 71 StoreBufferSize = 4, 72 StoreBufferThreshold = 3, 73 dpParams = DispatchParameters( 74 IntDqSize = 12, 75 FpDqSize = 12, 76 LsDqSize = 12, 77 IntDqDeqWidth = 4, 78 FpDqDeqWidth = 4, 79 LsDqDeqWidth = 4 80 ), 81 exuParameters = ExuParameters( 82 JmpCnt = 1, 83 AluCnt = 2, 84 MulCnt = 0, 85 MduCnt = 1, 86 FmacCnt = 1, 87 FmiscCnt = 1, 88 FmiscDivSqrtCnt = 0, 89 LduCnt = 2, 90 StuCnt = 2 91 ), 92 icacheParameters = ICacheParameters( 93 nSets = 64, // 16KB ICache 94 tagECC = Some("parity"), 95 dataECC = Some("parity"), 96 replacer = Some("setplru"), 97 nMissEntries = 2 98 ), 99 dcacheParameters = DCacheParameters( 100 nSets = 64, // 32KB DCache 101 nWays = 8, 102 tagECC = Some("secded"), 103 dataECC = Some("secded"), 104 replacer = Some("setplru"), 105 nMissEntries = 4, 106 nProbeEntries = 4, 107 nReleaseEntries = 4, 108 nStoreReplayEntries = 4, 109 ), 110 EnableBPD = false, // disable TAGE 111 EnableLoop = false, 112 TlbEntrySize = 32, 113 TlbSPEntrySize = 4, 114 l2tlbParameters = L2TLBParameters( 115 l1Size = 4, 116 l2nSets = 4, 117 l2nWays = 4, 118 l3nSets = 4, 119 l3nWays = 8, 120 spSize = 2, 121 missQueueSize = 8 122 ), 123 useFakeL2Cache = true, // disable L2 Cache 124 )), 125 L3Size = 256 * 1024, // 256KB L3 Cache 126 ) 127 }) 128) 129 130// Non-synthesizable MinimalConfig, for fast simulation only 131class MinimalSimConfig(n: Int = 1) extends Config( 132 new MinimalConfig(n).alter((site, here, up) => { 133 case SoCParamsKey => up(SoCParamsKey).copy( 134 cores = up(SoCParamsKey).cores.map(_.copy( 135 useFakeDCache = true, 136 useFakePTW = true, 137 useFakeL1plusCache = true, 138 )), 139 useFakeL3Cache = true 140 ) 141 }) 142) 143 144class MinimalSimConfigForFetch(n: Int = 1) extends Config( 145 new MinimalSimConfig(n).alter((site, here, up) => { 146 case SoCParamsKey => up(SoCParamsKey).copy( 147 cores = up(SoCParamsKey).cores.map(_.copy( 148 FetchWidth = 8, 149 EnableSC = false 150 )) 151 ) 152 }) 153) 154