1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17// See LICENSE.SiFive for license details. 18 19package xiangshan.cache 20 21import chipsalliance.rocketchip.config.Parameters 22import chisel3._ 23import chisel3.util._ 24import xiangshan.{HasXSParameter, XSBundle, XSModule} 25 26// this file contains common building blocks that can be shared by ICache and DCache 27// this is the common parameter base for L1 ICache and L1 DCache 28trait L1CacheParameters { 29 def nSets: Int 30 def nWays: Int 31 def rowBits: Int 32 def blockBytes: Int 33 val pageSize = 4 * 1024 34} 35 36trait HasL1CacheParameters extends HasXSParameter 37 with MemoryOpConstants { 38 val cacheParams: L1CacheParameters 39 40 def nSets = cacheParams.nSets 41 def nWays = cacheParams.nWays 42 def blockBytes = cacheParams.blockBytes 43 def refillBytes = l1BusDataWidth / 8 44 def blockBits = blockBytes * 8 45 46 def idxBits = log2Up(cacheParams.nSets) 47 def wayBits = log2Up(nWays) 48 def blockOffBits = log2Up(cacheParams.blockBytes) 49 def refillOffBits = log2Up(l1BusDataWidth / 8) 50 51 def untagBits = blockOffBits + idxBits 52 // 4K page 53 def pgIdxBits = 12 54 def pgUntagBits = untagBits min pgIdxBits 55 def tagBits = PAddrBits - pgUntagBits 56 57 // the basic unit at which we store contents 58 // SRAM bank width 59 def rowBits = cacheParams.rowBits 60 def rowBytes = rowBits/8 61 def rowOffBits = log2Up(rowBytes) 62 // the number of rows in a block 63 def blockRows = blockBytes / rowBytes 64 65 // outer bus width 66 def beatBits = l1BusDataWidth 67 def beatBytes = beatBits / 8 68 def refillCycles = blockBytes / beatBytes 69 def beatOffBits = log2Up(beatBytes) 70 71 // inner bus width(determined by XLEN) 72 def wordBits = DataBits 73 def wordBytes = wordBits / 8 74 def wordOffBits = log2Up(wordBytes) 75 // the number of words in a block 76 def blockWords = blockBytes / wordBytes 77 def refillWords = refillBytes / wordBytes 78 79 def get_phy_tag(paddr: UInt) = (paddr >> pgUntagBits).asUInt() 80 def get_tag(addr: UInt) = get_phy_tag(addr) 81 def get_idx(addr: UInt) = addr(untagBits-1, blockOffBits) 82 def get_untag(addr: UInt) = addr(pgUntagBits-1, 0) 83 def get_block(addr: UInt) = addr >> blockOffBits 84 def get_block_addr(addr: UInt) = (addr >> blockOffBits) << blockOffBits 85 def get_refill_addr(addr: UInt) = (addr >> refillOffBits) << refillOffBits 86 87 def get_beat(addr: UInt) = addr(blockOffBits - 1, beatOffBits) 88 def get_row(addr: UInt) = addr(blockOffBits - 1, rowOffBits) 89 def get_word(addr: UInt) = addr(blockOffBits - 1, wordOffBits) 90 91 def beatRows = beatBits/rowBits 92 def rowWords = rowBits/wordBits 93 def blockBeats = blockBytes / beatBytes 94 95 def full_divide(a: Int, b: Int) = a >= b && isPow2(a / b) 96} 97 98abstract class L1CacheModule(implicit p: Parameters) extends XSModule 99 with HasL1CacheParameters 100 101abstract class L1CacheBundle(implicit p: Parameters) extends XSBundle 102 with HasL1CacheParameters 103