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/aosp_15_r20/external/mesa3d/docs/relnotes/
H A D7.10.rst36 - New fragment shader back-end for i965-class hardware.
37 - Support for Sandybridge chipset in i965 DRI driver.
81 [i965 gles2c bisected] OpenGL ES 2.0 conformance
108 [i965] brw_fs.cpp:1461: void
143 - i965: Update renderer strings for sandybridge
1034 - i965: Share the KIL_NV implementation between glsl and non-glsl.
1035 - i965: Also enable CC statistics when doing OQs.
1036 - i965: Track the windowizer's dispatch for kill pixel, promoted, and
1043 - i965: Fix the vector/expression splitting for the write_mask change.
1044 - i965: When splitting vector variable assignment, ignore unset
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H A D10.2.5.rst41 - i965/fs: Refactor check for potential copy propagated instructions.
42 - i965/fs: skip copy-propate for logical instructions with negated src
44 - i965/vec4: skip copy-propate for logical instructions with negated
53 - i965: Fix z_offset computation in intel_miptree_unmap_depthstencil()
79 - i965: Generalize the pixel_x/y workaround for all UW types.
102 - i965: Add auxiliary surface field #defines for Broadwell.
111 - i965: Don't copy propagate abs into Broadwell logic instructions.
112 - i965: Set execution size to 8 for instructions with force_sechalf
114 - i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.
115 - i965/fs: Use WE_all for gl_SampleID header register munging.
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H A D10.2.4.rst42 - i965/fs: Refactor check for potential copy propagated instructions.
43 - i965/fs: skip copy-propate for logical instructions with negated src
45 - i965/vec4: skip copy-propate for logical instructions with negated
61 - i965: Generalize the pixel_x/y workaround for all UW types.
72 - i965: Add auxiliary surface field #defines for Broadwell.
76 - i965: Don't copy propagate abs into Broadwell logic instructions.
77 - i965: Set execution size to 8 for instructions with force_sechalf
79 - i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.
80 - i965/fs: Use WE_all for gl_SampleID header register munging.
81 - i965: Add plumbing for Broadwell's auxiliary surface support.
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H A D9.0.3.rst42 [bisected i965]Oglc shad-compiler(advanced.TestLessThani) regressed
141 - i965/disasm: Fix horizontal stride of dest registers
145 - i965/fs: Fix the gen6-specific if handling for 80ecb8f15b9ad7d6edc
146 - i965/fs: Don't generate saturates over existing variable values.
147 - i965: Actually add support for GL_ANY_SAMPLES_PASSED from GL_ARB_oq2.
148 - i965/vs: Try again when we've successfully spilled a reg.
149 - i965/gen7: Set up all samplers even if samplers are sparsely used.
171 - i965: Fix primitive restart on Haswell.
172 - i965: Refactor texture swizzle generation into a helper.
173 - i965: Do texture swizzling in hardware on Haswell.
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H A D17.3.4.rst44 - [GEN9+] 2-3% perf drop in GfxBench Manhattan 3.1 from "i965:
66 - i965: perform 2 uploads with dual slot \*64*PASSTHRU formats on gen<8
111 - cherry-ignore: i965: Accept CONTEXT_ATTRIB_PRIORITY for
124 - cherry-ignore: add i965 shader cache fixes
160 - i965: Call brw_cache_flush_for_render in predraw_resolve_framebuffer
161 - i965: Add more precise cache tracking helpers
162 - i965/blorp: Add more destination flushing
163 - i965: Track the depth and render caches separately
164 - i965: Track format and aux usage in the render cache
166 - i965/miptree: Refactor CCS_E and CCS_D cases in render_aux_usage
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H A D10.5.1.rst69 [HSW, regression, bisected] i965/fs: Emit MAD instructions when
72 [HSW, regression, bisected] i965: Add LINTERP/CINTERP to
84 - i965/vec4: Don't lose the saturate modifier in copy propagation.
88 - i965/gs: Check newly-generated GS-out VUE map against correct stage
108 - i965: Fix out-of-bounds accesses into pull_constant_loc array
112 - i965/fs/nir: Use emit_math for nir_op_fpow
128 - i965: Split Gen4-5 BlitFramebuffer code; prefer BLT over Meta.
131 - i965/fs: Set force_writemask_all on shader_time instructions.
132 - i965/fs: Set smear on shader_time diff register.
133 - i965/fs: Make emit_shader_time_write return rather than emit.
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H A D11.0.8.rst71 - cherry-ignore: don't pick a specific i965 formats patch
72 - Revert "i965/nir: Remove unused indirect handling"
73 - Revert "i965/state: Get rid of dword_pitch arguments to buffer
75 - Revert "i965/vec4: Use a stride of 1 and byte offsets for UBOs"
76 - Revert "i965/fs: Use a stride of 1 and byte offsets for UBOs"
77 - Revert "i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge"
82 - i965: Resolve color and flush for all active shader images in
112 - i965/vec4: Use byte offsets for UBO pulls on Sandy Bridge
113 - i965/fs: Use a stride of 1 and byte offsets for UBOs
114 - i965/vec4: Use a stride of 1 and byte offsets for UBOs
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H A D9.1.4.rst34 [bisected i965] Bus error (core dumped) on oglc texdecaltile
119 - i965: Fix glColorPointer(GL_FIXED)
147 - i965: fix problem with constant out of bounds access (v3)
154 - i965/fs: Bake regs_written into the IR instead of recomputing it
156 - i965/vs: Fix implied_mrf_writes() for integer division pre-gen6.
162 - i965: Shut up the last release build warning.
184 - mesa: Add i965 varying index patches to .cherry-ignore.
185 - i965: Turn brw->urb.vs_size and gs_size into local variables.
186 - i965: Use a variable for the push constant size in kB.
187 - i965: Update URB partitioning code for Haswell's GT3 variant.
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H A D17.1.4.rst33 Stellaris - colored overlay of sectors doesn't render on i965
63 - i965: Add and initialize l3_banks field for gen7+
64 - i965: Fix broxton 2x6 l3 config
107 - i965: update MaxTextureRectSize to match PRMs and comply with OpenGL
117 - i965: Flush around state base address
118 - i965: Take a uint64_t immediate in emit_pipe_control_write
119 - i965: Unify the two emit_pipe_control functions
120 - i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESS
121 - i965/blorp: Do an end-of-pipe sync around CCS ops
122 - i965: Do an end-of-pipe sync after flushes
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H A D9.1.3.rst56 [i965 Bisected]Ogles1conform/Ogles2conform/Ogles3conform cases
104 - i965/fs: Don't try to use bogus interpolation modes pre-Gen6.
114 - i965/fs: Remove creation of a MOV instruction that's never used.
115 - i965/fs: Move varying uniform offset compuation into the helper func.
116 - i965: Make the constant surface interface take a normal byte size.
117 - i965/fs: Avoid inappropriate optimization with regs_written > 1.
118 - i965/fs: Do CSE on gen7's varying-index pull constant loads.
119 - i965/fs: Clean up the setup of gen4 simd16 message destinations.
120 - i965/gen7: Skip resetting SOL offsets at batch start with HW
122 - i965/gen6: Reduce updates of transform feedback offsets with HW
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H A D7.10.1.rst39 - Fix an i965 shader bug where the negative absolute value was
55 [i965] After updating to Mesa 7.9, Civilization IV starts to show
219 - i965/fs: When producing ir_unop_abs of an operand, strip negate.
220 - i965/vs: When MOVing to produce ABS, strip negate of the operand.
221 - i965/fs: Do flat shading when appropriate.
222 - i965: Avoid double-negation of immediate values in the VS.
224 - i965: Fix dead pointers to fp->Parameters->ParameterValues[] after
226 - docs: Add a relnote for the Civ IV on i965.
233 - i965: Fix a bug in i965 compute-to-MRF.
234 - i965/fs: Add a helper function for detecting math opcodes.
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H A D8.0.5.rst157 - i965/gen7: Reduce GT1 WM thread count according to updated BSpec.
158 - i965/fs: Invalidate live intervals in passes that remove an
160 - i965: Fix bug in the old FS backend's projtex() calculation.
161 - i965: Add support for GL_SKIP_DECODE_EXT on other SRGB formats.
162 - i965/vs: Convert EdgeFlagPointer values appropriately for the VS on
164 - i965: Fix accumulator_contains() test to also reject swizzles of the
168 - i965: Drop the confusing saturate argument to math instruction setup.
173 - Revert "i965: Avoid unnecessary recompiles for shaders that don't use
175 - i965: Fix regression in depth texture rendering on pre-SNB
198 - i965/fs: Initialize output_components[] by filling it with zeros.
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H A D12.0.2.rst75 [i965 on HD4600 Haswell] xcom switch to ingame cinematics cause
114 - i965: Fix miptree layout for EGLImage-based renderbuffers
115 - i965: Respect miptree offsets in intel_readpixels_tiled_memcpy()
139 - i965: store reference to the context within struct brw_fence (v2)
149 - Revert "i965/miptree: Set logical_depth0 == 6 for cube maps"
162 - i965: Emit SKL VF cache invalidation W/A from
164 - i965: Make room in the batch epilogue for three more pipe controls.
165 - i965: Fix remaining flush vs invalidate race conditions in
221 - i965/miptree: Enforce that height == 1 for 1-D array textures
222 - i965/miptree: Set logical_depth0 == 6 for cube maps
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H A D10.2.2.rst38 [i965 Bisected]Piglit/glx_glx-make-glxdrawable-current fails
47 [i965] glClear on a multisample texture doesn't work
119 - i965: Don't use the head sentinel as an fs_inst in Gen4 workaround
121 - i965: Invalidate live intervals when inserting Gen4 SEND workarounds.
122 - i965/vec4: Fix dead code elimination for VGRFs of size > 1.
123 - i965: Add missing MOCS setup for 3DSTATE_INDEX_BUFFER on Broadwell.
124 - i965: Drop Broadwell perf_debugs about missing MOCS that aren't
126 - i965: Add missing newlines to a few perf_debug messages.
127 - i965/vec4: Use the sampler for pull constant loads on Broadwell.
128 - i965: Use 8x4 aligned rectangles for HiZ operations on Broadwell.
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H A D13.0.6.rst117 - i965: move brw_define.h ifndef guard to the top
162 - i965: Use a better guardband calculation.
164 - i965/fs: Remove the inline pack_double_2x32 optimization
185 - i965: Fix fast depth clears for surfaces with a dimension of 16384.
186 - i965: Use a UW source type for CS_OPCODE_CS_TERMINATE.
187 - i965: Fix check for negative pitch in can_do_fast_copy_blit().
188 - i965: Support the force_glsl_version driconf option.
189 - i965: Combine the Gen6 SF and Clip viewport atoms.
197 - i965/fs: fix uninitialized memory access
244 - i965/fs: mark last DF uniform array element as 64 bit live one
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H A D19.0.0.rst39 GL_ARB_shader_ballot on i965.
59 - [i965] Downward causes GPU hangs and misrendering on Haswell
83 - i965 incorrectly calculates the number of layers for texture views
118 - i965 regressions from EXT_texture_sRGB_R8
253 - i965: Lift restriction in external textures for EGLImage support
314 - i965: avoid 'unused variable' warnings
315 - i965/batch: avoid reverting batch buffer if saved state is an empty
320 - i965: re-emit index buffer state on a reset option change.
324 - i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREG
327 - i965/icl: Fix L3 configurations
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H A D9.1.2.rst41 [i965 Bisected]Oglc fbblit(advanced.blitFb-3d-cube.mirror.both) fails
116 - i965: Avoid segfault in gen6_upload_state
120 - i965/vs: Fix Gen4/5 VUE map inconsistency with gl_ClipVertex
131 - i965/fs: Fix register allocation for uniform pull constants in
133 - i965/fs: Fix broken rendering in large shaders with UBO loads.
134 - i965/fs: Also do the gen4 SEND dependency workaround against other
136 - i965: Add definitions for gen7+ data cache messages.
161 - i965: Fix INTEL_DEBUG=shader_time for Haswell.
162 - i965: Specialize SURFACE_STATE creation for shader time.
163 - i965: Make INTEL_DEBUG=shader_time use the RAW surface format.
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H A D13.0.0.rst28 - OpenGL ES 3.1 on i965/hsw
29 - OpenGL ES 3.2 on i965/gen9+ (Skylake and later)
30 - GL_ARB_ES3_1_compatibility on i965
31 - GL_ARB_ES3_2_compatibility on i965/gen8+
35 - GL_ARB_enhanced_layouts on i965, nv50, nvc0, radeonsi, llvmpipe,
41 - GL_ARB_shader_viewport_layer_array on i965/gen6+
42 - GL_ARB_stencil_texturing on i965/hsw
43 - GL_ARB_texture_stencil8 on i965/hsw
45 - GL_KHR_blend_equation_advanced on i965
47 - GL_KHR_texture_compression_astc_sliced_3d on i965
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H A D8.0.3.rst51 [bisected i965] oglc sRGB(Mipmap.1D_textures) regressed
53 [i965]oglc max_values(negative.textureSize.textureCube) segfaults
159 - i965: fix typo
163 - i965/fs: Jump from discard statements to the end of the program when
167 - i965/fs: Move GL_CLAMP handling to coordinate setup.
168 - i965/fs: Implement GL_CLAMP behavior on texture rectangles on gen6+.
181 - i965/vs: Fix up swizzle for dereference_array of matrices.
232 - i965: Actually upload sampler state pointers for the VS unit on Gen6.
233 - i965/fs: Fix FB writes that tried to use the non-existent m16
239 - i965: Fix GPU hangs in the dummy fragment shader.
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H A D7.11.1.rst193 - i965/fs: Respect ARB_color_buffer_float clamping.
194 - i965: Add missing \_NEW_POLYGON flag to polygon stipple upload.
195 - i965: Fix polygon stipple offset state flagging.
198 - glsl: Fix gl_NormalMatrix swizzle setup to match i965's invariants.
256 - i965/gen5+: Fix incorrect miptree layout for non-power-of-two
258 - i965: Use proper texture alignment units for cubemaps on Gen5+.
259 - i965: Fix incorrect maximum PS thread count shift on Ivybridge.
260 - i965: Emit depth stalls and flushes before changing depth state on
262 - i965/fs: Allow SIMD16 with control flow on Ivybridge.
263 - i965: Allow SIMD16 color writes on Ivybridge.
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H A D11.1.3.rst80 - i965: Fix assert conditions for src/dst x/y offsets
84 - i965: Make sure we blit a full compressed block
85 - i965/skl: Add two missing device IDs
94 - i965/blorp: Fix hiz ops on MSAA surfaces
139 - i965: Reupload push and pull constants when we get new shader image
141 - i965/fs: Add missing analysis invalidation in opt_sampler_eot().
142 - i965/fs: Add missing analysis invalidation in fixup_3src_null_dest().
143 - i965/vec4: Consider removal of no-op MOVs as progress during register
182 - i965: Only magnify depth for 3D textures, not array textures.
200 - i965/vec4: don't copy ATTR into 3src instructions with complex
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H A D9.2.1.rst83 - i965/fs: Gen4: Zero out extra coordinates when using shadow compare
84 - i965: Fix cube array coordinate normalization
85 - i965: fix bogus swizzle in brw_cubemap_normalize
108 - i965/gen4: Fix fragment program rectangle texture shadow compares.
109 - i965: Reenable glBitmap() after the sRGB winsys enabling.
136 - i965/vs: Detect GRF sources in split_virtual_grfs send-from-GRF code.
137 - i965/fs: Detect GRF sources in split_virtual_grfs send-from-GRF code.
138 - i965/vec4: Only zero out unused message components when there are
140 - i965: Fix brw_vs_prog_data_compare to actually check field members.
156 - i965: Initialize inout_offset parameter to brw_search_cache().
H A D8.0.1.rst94 - i965: Rewrite the HiZ op
95 - i965: Remove file i965/junk, accidentally added in 7b36c68
103 - i965: Fix HiZ change compiler warning.
104 - i965: Report the failure message when failing to compile the fragment
106 - i965/fs: Enable register spilling on gen7 too.
117 - i965: Fix border color on Ironlake.
118 - i965/fs: Add a new fs_inst::regs_written function.
119 - i965/fs: Take # of components into account in try_rewrite_rhs_to_dst.
120 - i965: Emit Ivybridge VS workaround flushes.
H A D17.2.6.rst78 - cherry-ignore: i965: Mark BOs as external when we export their handle
88 - i965: Program DWord Length in MI_FLUSH_DW
89 - i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
129 - i965: Add stencil buffers to cache set regardless of stencil
134 - i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE
135 - i965: Make L3 configuration atom listen for TCS/TES program updates.
137 - i965: Implement another VF cache invalidate workaround on Gen8+.
138 - i965: Upload invariant state once at the start of the batch on
143 - i965/fs: Fix extract_i8/u8 to a 64-bit destination
144 - i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
H A D10.6.2.rst92 - i965/fs: Fix ir_txs in emit_texture_gen4_simd16().
93 - i965: Reserve more batch space to accomodate Gen6 perfmonitors.
94 - i965/vs: Fix matNxM vertex attributes where M != 4.
96 - Revert "i965: Delete linked GLSL IR when using NIR."
113 - i965/fs: Don't mess up stride for uniform integer multiplication.
123 - i965: allocate at least 1 BLEND_STATE element
127 - i965/skl: Set the pulls bary bit in 3DSTATE_PS_EXTRA
130 - i965: Don't try to print the GLSL IR if it has been freed
135 - i965: Delete linked GLSL IR when using NIR.
138 - i965: use EmitNoIndirectSampler for gen < 7

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