feat(rv64v): support first only fault instruction

feat(VLSU, Trigger): add vector segment access Trigger logic

feat(VLSU): element in which the exception occurs needs to retain its old value

feat(Trigger): add vector memory access Trigger logic

fix(csr): add support Non-registers interrupt pending to diff xip (#3572)

fix(csr): not skip read/write menvcfg/henvcfg (#3686)

Previously, menvcfg and henvcfg were added to "PerfCnt" to skip
read/write them, because its implementation is different between
XiangShan and

fix(csr): not skip read/write menvcfg/henvcfg (#3686)

Previously, menvcfg and henvcfg were added to "PerfCnt" to skip
read/write them, because its implementation is different between
XiangShan and NEMU. This patch removes this workaround as both XiangShan
and NEMU support menvcfg and henvcfg. This could solve the pbmte diff
problem.

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feat(CSR): add No.16,18 and 19 exceptions (#3640)

fix(rv64v): not modify fflags when vl is zero (#3658)

fix(CSR): remove reg in mhartid (#3665)

* mhartid should be assigned directly to multicycle hartid from top.

fix(csr): intermediate data should be stored when output not fire (#3634)

* Normal csr instrctions could fire by one cycle, while support IMSIC now.
* IMSIC and CSR have different clocks.
* Theref

fix(csr): intermediate data should be stored when output not fire (#3634)

* Normal csr instrctions could fire by one cycle, while support IMSIC now.
* IMSIC and CSR have different clocks.
* Therefore, CSR interacts with IMSIC through asynchronous reading.
* Implementd by fsm, and its state includes idle, waitIMSIC, finish.
* Output can fire when NewCSR requests an IMSIC response, and the
intermediate data should be stored.

---------

Co-authored-by: lewislzh <[email protected]>

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fix(CSR,interrupt): use rdata instead of regOut to produce interrupt (#3644)

* Make rdataFields as Output for InterruptFilter usage.
* This commit fix the problem that SEIP cannot be raised.

fix(csr): change connect0LatencyCtrlSingal to connectNonPipedCtrlSingal (#3647)

fix(vlwakeup): fix vl write back wakeup from intExu or vfExu (#3643)

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in Utility.
See also [Pull Request in
CoupledL2](https://github.com/OpenXiangShan/CoupledL2/pull/251#discussion_r1770738535).

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(csr): fix trap inst update when CSRR insts raise trap and remove useless io (#3620)

This PR fix trap inst update.
Because of CSRR inst is out of order insts, trap inst should select the
oldest

fix(csr): fix trap inst update when CSRR insts raise trap and remove useless io (#3620)

This PR fix trap inst update.
Because of CSRR inst is out of order insts, trap inst should select the
oldest trap inst when CSRR inst raise trap.

---------

Co-authored-by: Xuan Hu <[email protected]>

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refactor(Pmem): use `Seq` for physical memory ranges (#3622)

fix(CSR): Add legalization code for mstatus.MPP, mnstatus.MNPP and dcsr.PRV (#3577)

fix(imisc): fix exception generate when access imsic.

fix(prefetch): MMIO address should not send prefetch requests (#3615)

TODO: Prefetcher should check pmp & pma in order to decide whether to
send requests

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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fix(CSR): add a finite state machine in NewCSR (#3597)

CSR instructions used to be executed without pipelining, so a state
machine is not needed inside the CSR module. After adding an
optimization

fix(CSR): add a finite state machine in NewCSR (#3597)

CSR instructions used to be executed without pipelining, so a state
machine is not needed inside the CSR module. After adding an
optimization that allows certain CSRR instructions to be pipelined, a
state machine is required, since the arbiter to integer register files
must allow a write request before a CSRR instructions is successfully
executed.

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fix(VCVT): disable logic about scalar move instructions. (#3607)

fix(vstopi): wrong API usage in InterruptFilter (#3557)

* Don't use asTypeOf to convert UInt to CSRBundle, since CSRBundle's
assign follows the different rule with other chisel3.Data type.

feat(Zicbom,Zicboz): add permission check and convert CBO.INVAL to CBO.FLUSH when CBIE=0b01 (#3559)

* CSR
* When reset, xenvcfg.CBZE = 1, xenvcfg.CBCFE = 1, xenvcfg.CBIE = 0b11,
while x in {m, s,

feat(Zicbom,Zicboz): add permission check and convert CBO.INVAL to CBO.FLUSH when CBIE=0b01 (#3559)

* CSR
* When reset, xenvcfg.CBZE = 1, xenvcfg.CBCFE = 1, xenvcfg.CBIE = 0b11,
while x in {m, s, h}.
* Support xenvcfg.CBIE = Flush(0b01)
* Decode
* Use the illegalInst and virtualInst conditions from CSR to assert
EX_II or EX_VI.
* Convert CBO.INVAL to CBO.FLUSH when envcfg.CBIE === EnvCBIE.Flush.

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