fix(csr): filter out Read-Only CSR in regOut (#4412)

fix(intr,difftest): add interrupt delegate (#4516)

fix(vstopi): fix vstopi result selection

* AIA Spec:
* Ties in nominal priority are broken as usual by the default priority
* order from Table 8, unless hvictl fields VTI = 1 and IID ≠ 9
* (last ite

fix(vstopi): fix vstopi result selection

* AIA Spec:
* Ties in nominal priority are broken as usual by the default priority
* order from Table 8, unless hvictl fields VTI = 1 and IID ≠ 9
* (last item in the candidate list above), in which case
* default priority order is determined solely by hvictl.DPR.

* If bit IPRIOM (IPRIO Mode) of hvictl is zero, IPRIO in vstopi is 1;
* else, if the priority number for the highest-priority candidate
* is within the range 1 to 255, IPRIO is that value; else, IPRIO
* is set to either 0 or 255 in the manner documented for stopi
* in Section 5.4.2.

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fix(xtopi): fix m/stopi.IRPIO generation conditions

* If all bytes of the supervisor-level iprio array are read-only zeros,
* a simplified implementation of field IPRIO is allowed in which
* its val

fix(xtopi): fix m/stopi.IRPIO generation conditions

* If all bytes of the supervisor-level iprio array are read-only zeros,
* a simplified implementation of field IPRIO is allowed in which
* its value is always 1 whenever stopi is not zero.
*
* We are configurable and do not need to simplify the implementation.

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fix(xiselect): set the minimum range for xiselect (#4594)

The miselect register implements at least enough bits to support all
implemented miselect values.
The siselect register will support the val

fix(xiselect): set the minimum range for xiselect (#4594)

The miselect register implements at least enough bits to support all
implemented miselect values.
The siselect register will support the value range 0..0xFFF at a
minimum.
The vsiselect register will support the value range 0..0xFFF at a
minimum.

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fix(csr): fix trap handle bundle format (#4579)

feat(PMA, CSR): support PMA CSR configurable (#4233)

fix(vstopi): remove SEI from Candidate 4 (#4533)

* if hvictl.VTI = 0:
* the highest-priority pending-and-enabled major interrupt indicated
* by vsip and vsie other than a supervisor external interru

fix(vstopi): remove SEI from Candidate 4 (#4533)

* if hvictl.VTI = 0:
* the highest-priority pending-and-enabled major interrupt indicated
* by vsip and vsie other than a supervisor external interrupt(code 9),
* using the priority numbers assigned by hviprio1 and hviprio2.
*
* A hypervisor can choose to employ registers hviprio1 and hviprio2
* when emulating the (virtual) supervisor-level iprio array accessed
* indirectly through siselect and sireg (really vsiselect and vsireg)
* for a virtual hart. For interrupts not in the subset supported by
* hviprio1 and hviprio2, the priority number bytes in the emulated
* iprio array can be read-only zeros.

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fix(CSR): remove useless logic of `mIRVec` (#4553)

fix(difftest): fix sync aia event valid (#4517)

fix(CSR): use GEILEN from IMSICParams (#4520)

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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feat(AIA): integrate ChiselAIA again (#4509)

fix(difftest, CSR): sync non-reg interrupt pending right after reset (#4449)

Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

fix(csr, difftest): do not update difftest framework on reset

fix(csr): CSRR instruction read xireg inOrder (#4393)

* AIA registers are designed to be access asynchronously, so newCSR will
wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg

fix(csr): CSRR instruction read xireg inOrder (#4393)

* AIA registers are designed to be access asynchronously, so newCSR will
wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg
inOrder.

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fix(vfalu): fix bug of allFFlagsEn, when vm is all zero flags should be zero (#4380)

feat(AIA): integrate ChiselAIA (#4378)

fix(Trigger): fix comparison between consecutive pc and tdada2 (#4346)

fix(CSR): add VTYPE to in-order read CSRs (#4354)

Since CSR VTYPE is not renamed (VL is renamed), the instruction CSRR
with VTYPE cannot be executed out-of-order.

chore(fu): delete redundant code in VCVT (#4328)

fix(PFEvent): use `CSRModule` for distribute_csr in PFEvent (#4321)

fix(dbltrp): set sdt to 0 when exe sret to VU (#4313)

style(csr): fix typo in CSR (#4310)