| #
780ade3f |
| 20-Dec-2020 |
Yinan Xu <[email protected]> |
lsq: optimize enqueue logic
|
| #
43ad9482 |
| 19-Dec-2020 |
Lingrui98 <[email protected]> |
change signal names related to brInfo
|
| #
819e6a63 |
| 18-Dec-2020 |
Yinan Xu <[email protected]> |
brq: send brUpdate to frontend when replay
|
| #
b424051c |
| 14-Dec-2020 |
Yinan Xu <[email protected]> |
rename: use PipelineConnect instead of DecodeBuffer
|
| #
c0bcc0d1 |
| 13-Dec-2020 |
Yinan Xu <[email protected]> |
rename: move io.isWalk out of DecodeBuffer
|
| #
21e7a6c5 |
| 13-Dec-2020 |
Yinan Xu <[email protected]> |
roq,commits: update commit io
|
| #
43913318 |
| 11-Dec-2020 |
Yinan Xu <[email protected]> |
dispatch: remove replay logic
|
| #
67cc1812 |
| 09-Dec-2020 |
Yinan Xu <[email protected]> |
CtrlBlock: mis-prediction has higher priority when replay has the same roqIdx
|
| #
98993cf5 |
| 08-Dec-2020 |
Yinan Xu <[email protected]> |
brq: treat replay as redirect
|
| #
21732575 |
| 03-Dec-2020 |
Yinan Xu <[email protected]> |
replay: send redirect when replay
|
| #
5e5d3dcb |
| 02-Dec-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into opt-redirect
|
| #
99b8dc2c |
| 30-Nov-2020 |
Yinan Xu <[email protected]> |
rename: don't bypass preg and leave it to dispatch1
Rename now provides vectors indicating whether there're matches between lsrc1/lsrc2/lsrc3/ldest
and previous instructions' ldest. Dispatch1 update
rename: don't bypass preg and leave it to dispatch1
Rename now provides vectors indicating whether there're matches between lsrc1/lsrc2/lsrc3/ldest
and previous instructions' ldest. Dispatch1 updates uops' psrc1/psrc2/psrc3/old_pdest with
previous instructions pdest. This method optimizes rename' timing.
show more ...
|
| #
8b922c39 |
| 29-Nov-2020 |
Yinan Xu <[email protected]> |
ifu: only use redirect.bits for addr
|
| #
5e33e227 |
| 28-Nov-2020 |
Yinan Xu <[email protected]> |
Merge remote-tracking branch 'origin/master' into opt-dispatch1
|
| #
1c931a03 |
| 27-Nov-2020 |
Yinan Xu <[email protected]> |
CtrlBlock: fix bug and use isFp for fpBusyTable
|
| #
3fae98ac |
| 27-Nov-2020 |
Yinan Xu <[email protected]> |
busytable: moved out of rename
|
| #
21b47d38 |
| 27-Nov-2020 |
Yinan Xu <[email protected]> |
dispatch1: support Roq extra walk via io.extraWalk
|
| #
08fafef0 |
| 27-Nov-2020 |
Yinan Xu <[email protected]> |
lsq,roq: output ready when empty entries >= enqnum
|
| #
0bd67ba5 |
| 18-Nov-2020 |
Yinan Xu <[email protected]> |
lsq: rename all lsroq to lsq
|
| #
1c2588aa |
| 18-Nov-2020 |
Yinan Xu <[email protected]> |
XSCore: use Blocks
|
| #
0412e00d |
| 16-Nov-2020 |
LinJiawei <[email protected]> |
[WIP] backend: connect ctrl block
|
| #
694b0180 |
| 16-Nov-2020 |
LinJiawei <[email protected]> |
[WIP] dispatch: do not need exuConfig form its params
|
| #
7ca3937d |
| 13-Nov-2020 |
Yinan Xu <[email protected]> |
xscore: use integerBlock,memBlock,floatBlock
|
| #
b7130bae |
| 13-Nov-2020 |
Yinan Xu <[email protected]> |
MemBlock: add reservation stations and connections
|
| #
66bcc42f |
| 12-Nov-2020 |
Yinan Xu <[email protected]> |
IntegerBlock: add reservation stations
|