1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 8import xiangshan.backend.rename.{Rename, BusyTable} 9import xiangshan.backend.brq.Brq 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 15 16class CtrlToIntBlockIO extends XSBundle { 17 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 18 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 19 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 20 val redirect = ValidIO(new Redirect) 21} 22 23class CtrlToFpBlockIO extends XSBundle { 24 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 25 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 26 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 27 val redirect = ValidIO(new Redirect) 28} 29 30class CtrlToLsBlockIO extends XSBundle { 31 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 32 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 33 val enqLsq = new Bundle() { 34 val canAccept = Input(Bool()) 35 val req = Vec(RenameWidth, ValidIO(new MicroOp)) 36 val resp = Vec(RenameWidth, Input(new LSIdx)) 37 } 38 val redirect = ValidIO(new Redirect) 39} 40 41class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 42 val io = IO(new Bundle { 43 val frontend = Flipped(new FrontendToBackendIO) 44 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 45 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 46 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 47 val toIntBlock = new CtrlToIntBlockIO 48 val toFpBlock = new CtrlToFpBlockIO 49 val toLsBlock = new CtrlToLsBlockIO 50 val roqio = new Bundle { 51 // to int block 52 val toCSR = new RoqCSRIO 53 val exception = ValidIO(new MicroOp) 54 val isInterrupt = Output(Bool()) 55 // to mem block 56 val commits = Vec(CommitWidth, ValidIO(new RoqCommit)) 57 val roqDeqPtr = Output(new RoqPtr) 58 } 59 val oldestStore = Input(Valid(new RoqPtr)) 60 }) 61 62 val decode = Module(new DecodeStage) 63 val brq = Module(new Brq) 64 val decBuf = Module(new DecodeBuffer) 65 val rename = Module(new Rename) 66 val dispatch = Module(new Dispatch) 67 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 68 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 69 70 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 71 72 val roq = Module(new Roq(roqWbSize)) 73 74 // When replay and mis-prediction have the same roqIdx, 75 // mis-prediction should have higher priority, since mis-prediction flushes the load instruction. 76 // Thus, only when mis-prediction roqIdx is after replay roqIdx, replay should be valid. 77 val brqIsAfterLsq = isAfter(brq.io.redirect.bits.roqIdx, io.fromLsBlock.replay.bits.roqIdx) 78 val redirectArb = Mux(io.fromLsBlock.replay.valid && (!brq.io.redirect.valid || brqIsAfterLsq), 79 io.fromLsBlock.replay.bits, brq.io.redirect.bits) 80 val redirectValid = roq.io.redirect.valid || brq.io.redirect.valid || io.fromLsBlock.replay.valid 81 val redirect = Mux(roq.io.redirect.valid, roq.io.redirect.bits, redirectArb) 82 83 io.frontend.redirect.valid := redirectValid 84 io.frontend.redirect.bits := Mux(roq.io.redirect.valid, roq.io.redirect.bits.target, redirectArb.target) 85 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 86 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 87 88 decode.io.in <> io.frontend.cfVec 89 decode.io.toBrq <> brq.io.enqReqs 90 decode.io.brTags <> brq.io.brTags 91 decode.io.out <> decBuf.io.in 92 93 brq.io.roqRedirect <> roq.io.redirect 94 brq.io.memRedirect.valid := brq.io.redirect.valid || io.fromLsBlock.replay.valid 95 brq.io.memRedirect.bits <> redirectArb 96 brq.io.bcommit <> roq.io.bcommit 97 brq.io.enqReqs <> decode.io.toBrq 98 brq.io.exuRedirect <> io.fromIntBlock.exuRedirect 99 100 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 101 decBuf.io.redirect.valid <> redirectValid 102 decBuf.io.redirect.bits <> redirect 103 decBuf.io.out <> rename.io.in 104 105 rename.io.redirect.valid <> redirectValid 106 rename.io.redirect.bits <> redirect 107 rename.io.roqCommits <> roq.io.commits 108 rename.io.out <> dispatch.io.fromRename 109 rename.io.renameBypass <> dispatch.io.renameBypass 110 111 dispatch.io.redirect.valid <> redirectValid 112 dispatch.io.redirect.bits <> redirect 113 dispatch.io.enqRoq <> roq.io.enq 114 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 115 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.oldestStore.valid 116 dispatch.io.dequeueRoqIndex.bits := Mux(io.oldestStore.valid, 117 io.oldestStore.bits, 118 roq.io.commitRoqIndex.bits 119 ) 120 dispatch.io.readIntRf <> io.toIntBlock.readRf 121 dispatch.io.readFpRf <> io.toFpBlock.readRf 122 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 123 intBusyTable.io.allocPregs(i).valid := preg.isInt 124 fpBusyTable.io.allocPregs(i).valid := preg.isFp 125 intBusyTable.io.allocPregs(i).bits := preg.preg 126 fpBusyTable.io.allocPregs(i).bits := preg.preg 127 } 128 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 129 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 130 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 131 132 133 val flush = redirectValid && (redirect.isException || redirect.isFlushPipe) 134 fpBusyTable.io.flush := flush 135 intBusyTable.io.flush := flush 136 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 137 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen && (wb.bits.uop.ctrl.ldest =/= 0.U) 138 setPhyRegRdy.bits := wb.bits.uop.pdest 139 } 140 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 141 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 142 setPhyRegRdy.bits := wb.bits.uop.pdest 143 } 144 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 145 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 146 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 147 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 148 for(i <- 0 until ReplayWidth){ 149 intBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isInt 150 fpBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isFp 151 intBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg 152 fpBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg 153 } 154 155 roq.io.memRedirect := DontCare 156 roq.io.memRedirect.valid := false.B 157 roq.io.brqRedirect.valid := brq.io.redirect.valid || io.fromLsBlock.replay.valid 158 roq.io.brqRedirect.bits <> redirectArb 159 roq.io.exeWbResults.take(roqWbSize-1).zip( 160 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 161 ).foreach{ 162 case(x, y) => 163 x.bits := y.bits 164 x.valid := y.valid && !y.bits.redirectValid 165 } 166 roq.io.exeWbResults.last := brq.io.out 167 168 io.toIntBlock.redirect.valid := redirectValid 169 io.toIntBlock.redirect.bits := redirect 170 io.toFpBlock.redirect.valid := redirectValid 171 io.toFpBlock.redirect.bits := redirect 172 io.toLsBlock.redirect.valid := redirectValid 173 io.toLsBlock.redirect.bits := redirect 174 175 // roq to int block 176 io.roqio.toCSR <> roq.io.csr 177 io.roqio.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 178 io.roqio.exception.bits := roq.io.exception 179 io.roqio.isInterrupt := roq.io.redirect.bits.isFlushPipe 180 // roq to mem block 181 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 182 io.roqio.commits := roq.io.commits 183} 184