1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 8import xiangshan.backend.rename.{Rename, BusyTable} 9import xiangshan.backend.brq.Brq 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 15 16class CtrlToIntBlockIO extends XSBundle { 17 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 18 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 19 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 20 val redirect = ValidIO(new Redirect) 21} 22 23class CtrlToFpBlockIO extends XSBundle { 24 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 25 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 26 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 27 val redirect = ValidIO(new Redirect) 28} 29 30class CtrlToLsBlockIO extends XSBundle { 31 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 32 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 33 val enqLsq = new Bundle() { 34 val canAccept = Input(Bool()) 35 val req = Vec(RenameWidth, ValidIO(new MicroOp)) 36 val resp = Vec(RenameWidth, Input(new LSIdx)) 37 } 38 val redirect = ValidIO(new Redirect) 39} 40 41class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 42 val io = IO(new Bundle { 43 val frontend = Flipped(new FrontendToBackendIO) 44 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 45 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 46 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 47 val toIntBlock = new CtrlToIntBlockIO 48 val toFpBlock = new CtrlToFpBlockIO 49 val toLsBlock = new CtrlToLsBlockIO 50 val roqio = new Bundle { 51 // to int block 52 val toCSR = new RoqCSRIO 53 val exception = ValidIO(new MicroOp) 54 val isInterrupt = Output(Bool()) 55 // to mem block 56 val commits = Vec(CommitWidth, ValidIO(new RoqCommit)) 57 val roqDeqPtr = Output(new RoqPtr) 58 } 59 val oldestStore = Input(Valid(new RoqPtr)) 60 }) 61 62 val decode = Module(new DecodeStage) 63 val brq = Module(new Brq) 64 val decBuf = Module(new DecodeBuffer) 65 val rename = Module(new Rename) 66 val dispatch = Module(new Dispatch) 67 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 68 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 69 70 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 71 72 val roq = Module(new Roq(roqWbSize)) 73 74 val lsqIsAfterBrq = isAfter(io.fromLsBlock.replay.bits.roqIdx, brq.io.redirect.bits.roqIdx) 75 val redirectArb = Mux(brq.io.redirect.valid && (!io.fromLsBlock.replay.valid || lsqIsAfterBrq), 76 brq.io.redirect.bits, io.fromLsBlock.replay.bits) 77 val redirectValid = roq.io.redirect.valid || brq.io.redirect.valid || io.fromLsBlock.replay.valid 78 val redirect = Mux(roq.io.redirect.valid, roq.io.redirect.bits, redirectArb) 79 80 io.frontend.redirect.valid := redirectValid 81 io.frontend.redirect.bits := Mux(roq.io.redirect.valid, roq.io.redirect.bits.target, redirectArb.target) 82 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 83 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 84 85 decode.io.in <> io.frontend.cfVec 86 decode.io.toBrq <> brq.io.enqReqs 87 decode.io.brTags <> brq.io.brTags 88 decode.io.out <> decBuf.io.in 89 90 brq.io.roqRedirect <> roq.io.redirect 91 brq.io.memRedirect.valid := brq.io.redirect.valid || io.fromLsBlock.replay.valid 92 brq.io.memRedirect.bits <> redirectArb 93 brq.io.bcommit <> roq.io.bcommit 94 brq.io.enqReqs <> decode.io.toBrq 95 brq.io.exuRedirect <> io.fromIntBlock.exuRedirect 96 97 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 98 decBuf.io.redirect.valid <> redirectValid 99 decBuf.io.redirect.bits <> redirect 100 decBuf.io.out <> rename.io.in 101 102 rename.io.redirect.valid <> redirectValid 103 rename.io.redirect.bits <> redirect 104 rename.io.roqCommits <> roq.io.commits 105 rename.io.out <> dispatch.io.fromRename 106 rename.io.renameBypass <> dispatch.io.renameBypass 107 108 dispatch.io.redirect.valid <> redirectValid 109 dispatch.io.redirect.bits <> redirect 110 dispatch.io.enqRoq <> roq.io.enq 111 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 112 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.oldestStore.valid 113 dispatch.io.dequeueRoqIndex.bits := Mux(io.oldestStore.valid, 114 io.oldestStore.bits, 115 roq.io.commitRoqIndex.bits 116 ) 117 dispatch.io.readIntRf <> io.toIntBlock.readRf 118 dispatch.io.readFpRf <> io.toFpBlock.readRf 119 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 120 intBusyTable.io.allocPregs(i).valid := preg.isInt 121 fpBusyTable.io.allocPregs(i).valid := preg.isFp 122 intBusyTable.io.allocPregs(i).bits := preg.preg 123 fpBusyTable.io.allocPregs(i).bits := preg.preg 124 } 125 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 126 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 127 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 128 129 130 val flush = redirectValid && (redirect.isException || redirect.isFlushPipe) 131 fpBusyTable.io.flush := flush 132 intBusyTable.io.flush := flush 133 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 134 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen && (wb.bits.uop.ctrl.ldest =/= 0.U) 135 setPhyRegRdy.bits := wb.bits.uop.pdest 136 } 137 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 138 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 139 setPhyRegRdy.bits := wb.bits.uop.pdest 140 } 141 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 142 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 143 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 144 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 145 for(i <- 0 until ReplayWidth){ 146 intBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isInt 147 fpBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isFp 148 intBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg 149 fpBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg 150 } 151 152 roq.io.memRedirect := DontCare 153 roq.io.memRedirect.valid := false.B 154 roq.io.brqRedirect.valid := brq.io.redirect.valid || io.fromLsBlock.replay.valid 155 roq.io.brqRedirect.bits <> redirectArb 156 roq.io.exeWbResults.take(roqWbSize-1).zip( 157 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 158 ).foreach{ 159 case(x, y) => 160 x.bits := y.bits 161 x.valid := y.valid && !y.bits.redirectValid 162 } 163 roq.io.exeWbResults.last := brq.io.out 164 165 io.toIntBlock.redirect.valid := redirectValid 166 io.toIntBlock.redirect.bits := redirect 167 io.toFpBlock.redirect.valid := redirectValid 168 io.toFpBlock.redirect.bits := redirect 169 io.toLsBlock.redirect.valid := redirectValid 170 io.toLsBlock.redirect.bits := redirect 171 172 // roq to int block 173 io.roqio.toCSR <> roq.io.csr 174 io.roqio.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 175 io.roqio.exception.bits := roq.io.exception 176 io.roqio.isInterrupt := roq.io.redirect.bits.isFlushPipe 177 // roq to mem block 178 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 179 io.roqio.commits := roq.io.commits 180} 181