1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.Rename 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 14 15class CtrlToIntBlockIO extends XSBundle { 16 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 17 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 18 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 19 val redirect = ValidIO(new Redirect) 20 val roqToCSR = new RoqCSRIO 21} 22 23class CtrlToFpBlockIO extends XSBundle { 24 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 25 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 26 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 27 val redirect = ValidIO(new Redirect) 28} 29 30class CtrlToLsBlockIO extends XSBundle { 31 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 32 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 33 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 34 val redirect = ValidIO(new Redirect) 35 // from roq: send commits info to lsq 36 val commits = Vec(CommitWidth, ValidIO(new RoqCommit)) 37 // from roq: the newest roqDeqPtr 38 val roqDeqPtr = Output(new RoqPtr) 39} 40 41class CtrlBlock extends XSModule { 42 val io = IO(new Bundle { 43 val frontend = Flipped(new FrontendToBackendIO) 44 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 45 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 46 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 47 val toIntBlock = new CtrlToIntBlockIO 48 val toFpBlock = new CtrlToFpBlockIO 49 val toLsBlock = new CtrlToLsBlockIO 50 }) 51 52 val decode = Module(new DecodeStage) 53 val brq = Module(new Brq) 54 val decBuf = Module(new DecodeBuffer) 55 val rename = Module(new Rename) 56 val dispatch = Module(new Dispatch) 57 // TODO: move busyTable to dispatch1 58 // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 59 // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 60 61 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 62 63 val roq = Module(new Roq(roqWbSize)) 64 65 val redirect = Mux( 66 roq.io.redirect.valid, 67 roq.io.redirect, 68 Mux( 69 brq.io.redirect.valid, 70 brq.io.redirect, 71 io.fromLsBlock.replay 72 ) 73 ) 74 75 io.frontend.redirect := redirect 76 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 77 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 78 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 79 io.frontend.sfence <> io.fromIntBlock.sfence 80 io.frontend.tlbCsrIO <> io.fromIntBlock.tlbCsrIO 81 82 decode.io.in <> io.frontend.cfVec 83 decode.io.toBrq <> brq.io.enqReqs 84 decode.io.brTags <> brq.io.brTags 85 decode.io.out <> decBuf.io.in 86 87 brq.io.roqRedirect <> roq.io.redirect 88 brq.io.memRedirect <> io.fromLsBlock.replay 89 brq.io.bcommit <> roq.io.bcommit 90 brq.io.enqReqs <> decode.io.toBrq 91 brq.io.exuRedirect <> io.fromIntBlock.exuRedirect 92 93 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 94 decBuf.io.redirect <> redirect 95 decBuf.io.out <> rename.io.in 96 97 rename.io.redirect <> redirect 98 rename.io.roqCommits <> roq.io.commits 99 // they should be moved to busytables 100 rename.io.wbIntResults <> io.fromIntBlock.wbRegs 101 rename.io.wbFpResults <> io.fromFpBlock.wbRegs 102 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 103 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 104 rename.io.intPregRdy <> dispatch.io.intPregRdy 105 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 106 rename.io.replayPregReq <> dispatch.io.replayPregReq 107 rename.io.out <> dispatch.io.fromRename 108 109 dispatch.io.redirect <> redirect 110 dispatch.io.toRoq <> roq.io.dp1Req 111 dispatch.io.roqIdxs <> roq.io.roqIdxs 112 dispatch.io.toLsroq <> io.toLsBlock.lsqIdxReq 113 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 114 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.fromLsBlock.oldestStore.valid 115 dispatch.io.dequeueRoqIndex.bits := Mux(io.fromLsBlock.oldestStore.valid, 116 io.fromLsBlock.oldestStore.bits, 117 roq.io.commitRoqIndex.bits 118 ) 119 dispatch.io.readIntRf <> io.toIntBlock.readRf 120 dispatch.io.readFpRf <> io.toFpBlock.readRf 121 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 122 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 123 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 124 125 126 roq.io.memRedirect <> io.fromLsBlock.replay 127 roq.io.brqRedirect <> brq.io.redirect 128 roq.io.dp1Req <> dispatch.io.toRoq 129 130 131 roq.io.exeWbResults.take(roqWbSize-1).zip( 132 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 133 ).foreach{ 134 case(x, y) => 135 x.bits := y.bits 136 x.valid := y.valid && !y.bits.redirectValid 137 } 138 roq.io.exeWbResults.last := brq.io.out 139 140 io.toIntBlock.redirect := redirect 141 io.toIntBlock.roqToCSR <> roq.io.csr 142 143 io.toFpBlock.redirect := redirect 144 145 io.toLsBlock.redirect := redirect 146 io.toLsBlock.roqDeqPtr := roq.io.roqDeqPtr 147 io.toLsBlock.commits := roq.io.commits 148 149 150 151} 152