1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 8import xiangshan.backend.rename.{Rename, BusyTable} 9import xiangshan.backend.brq.Brq 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 15 16class CtrlToIntBlockIO extends XSBundle { 17 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 18 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 19 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 20 val redirect = ValidIO(new Redirect) 21} 22 23class CtrlToFpBlockIO extends XSBundle { 24 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 25 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 26 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 27 val redirect = ValidIO(new Redirect) 28} 29 30class CtrlToLsBlockIO extends XSBundle { 31 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 32 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 33 val enqLsq = new Bundle() { 34 val canAccept = Input(Bool()) 35 val req = Vec(RenameWidth, ValidIO(new MicroOp)) 36 val resp = Vec(RenameWidth, Input(new LSIdx)) 37 } 38 val redirect = ValidIO(new Redirect) 39} 40 41class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 42 val io = IO(new Bundle { 43 val frontend = Flipped(new FrontendToBackendIO) 44 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 45 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 46 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 47 val toIntBlock = new CtrlToIntBlockIO 48 val toFpBlock = new CtrlToFpBlockIO 49 val toLsBlock = new CtrlToLsBlockIO 50 val roqio = new Bundle { 51 // to int block 52 val toCSR = new RoqCSRIO 53 val exception = ValidIO(new MicroOp) 54 val isInterrupt = Output(Bool()) 55 // to mem block 56 val commits = new RoqCommitIO 57 val roqDeqPtr = Output(new RoqPtr) 58 } 59 }) 60 61 val decode = Module(new DecodeStage) 62 val brq = Module(new Brq) 63 val decBuf = Module(new DecodeBuffer) 64 val rename = Module(new Rename) 65 val dispatch = Module(new Dispatch) 66 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 67 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 68 69 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 70 71 val roq = Module(new Roq(roqWbSize)) 72 73 // When replay and mis-prediction have the same roqIdx, 74 // mis-prediction should have higher priority, since mis-prediction flushes the load instruction. 75 // Thus, only when mis-prediction roqIdx is after replay roqIdx, replay should be valid. 76 val brqIsAfterLsq = isAfter(brq.io.redirect.bits.roqIdx, io.fromLsBlock.replay.bits.roqIdx) 77 val redirectArb = Mux(io.fromLsBlock.replay.valid && (!brq.io.redirect.valid || brqIsAfterLsq), 78 io.fromLsBlock.replay.bits, brq.io.redirect.bits) 79 val redirectValid = roq.io.redirect.valid || brq.io.redirect.valid || io.fromLsBlock.replay.valid 80 val redirect = Mux(roq.io.redirect.valid, roq.io.redirect.bits, redirectArb) 81 82 io.frontend.redirect.valid := redirectValid 83 io.frontend.redirect.bits := Mux(roq.io.redirect.valid, roq.io.redirect.bits.target, redirectArb.target) 84 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 85 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 86 87 decode.io.in <> io.frontend.cfVec 88 decode.io.toBrq <> brq.io.enqReqs 89 decode.io.brTags <> brq.io.brTags 90 decode.io.out <> decBuf.io.in 91 92 brq.io.roqRedirect <> roq.io.redirect 93 brq.io.memRedirect.valid := brq.io.redirect.valid || io.fromLsBlock.replay.valid 94 brq.io.memRedirect.bits <> redirectArb 95 brq.io.bcommit <> roq.io.bcommit 96 brq.io.enqReqs <> decode.io.toBrq 97 brq.io.exuRedirect <> io.fromIntBlock.exuRedirect 98 99 decBuf.io.isWalking := roq.io.commits.hasWalkInstr 100 decBuf.io.redirect.valid <> redirectValid 101 decBuf.io.redirect.bits <> redirect 102 decBuf.io.out <> rename.io.in 103 104 rename.io.redirect.valid <> redirectValid 105 rename.io.redirect.bits <> redirect 106 rename.io.roqCommits <> roq.io.commits 107 rename.io.out <> dispatch.io.fromRename 108 rename.io.renameBypass <> dispatch.io.renameBypass 109 110 dispatch.io.redirect.valid <> redirectValid 111 dispatch.io.redirect.bits <> redirect 112 dispatch.io.enqRoq <> roq.io.enq 113 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 114 dispatch.io.readIntRf <> io.toIntBlock.readRf 115 dispatch.io.readFpRf <> io.toFpBlock.readRf 116 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 117 intBusyTable.io.allocPregs(i).valid := preg.isInt 118 fpBusyTable.io.allocPregs(i).valid := preg.isFp 119 intBusyTable.io.allocPregs(i).bits := preg.preg 120 fpBusyTable.io.allocPregs(i).bits := preg.preg 121 } 122 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 123 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 124 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 125 126 127 val flush = redirectValid && (redirect.isException || redirect.isFlushPipe) 128 fpBusyTable.io.flush := flush 129 intBusyTable.io.flush := flush 130 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 131 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen && (wb.bits.uop.ctrl.ldest =/= 0.U) 132 setPhyRegRdy.bits := wb.bits.uop.pdest 133 } 134 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 135 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 136 setPhyRegRdy.bits := wb.bits.uop.pdest 137 } 138 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 139 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 140 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 141 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 142 143 roq.io.memRedirect := DontCare 144 roq.io.memRedirect.valid := false.B 145 roq.io.brqRedirect.valid := brq.io.redirect.valid || io.fromLsBlock.replay.valid 146 roq.io.brqRedirect.bits <> redirectArb 147 roq.io.exeWbResults.take(roqWbSize-1).zip( 148 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 149 ).foreach{ 150 case(x, y) => 151 x.bits := y.bits 152 x.valid := y.valid && !y.bits.redirectValid 153 } 154 roq.io.exeWbResults.last := brq.io.out 155 156 io.toIntBlock.redirect.valid := redirectValid 157 io.toIntBlock.redirect.bits := redirect 158 io.toFpBlock.redirect.valid := redirectValid 159 io.toFpBlock.redirect.bits := redirect 160 io.toLsBlock.redirect.valid := redirectValid 161 io.toLsBlock.redirect.bits := redirect 162 163 // roq to int block 164 io.roqio.toCSR <> roq.io.csr 165 io.roqio.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 166 io.roqio.exception.bits := roq.io.exception 167 io.roqio.isInterrupt := roq.io.redirect.bits.isFlushPipe 168 // roq to mem block 169 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 170 io.roqio.commits := roq.io.commits 171} 172