1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.{Rename, BusyTable} 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 14 15class CtrlToIntBlockIO extends XSBundle { 16 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 17 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 18 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 19 val redirect = ValidIO(new Redirect) 20} 21 22class CtrlToFpBlockIO extends XSBundle { 23 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 24 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 25 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 26 val redirect = ValidIO(new Redirect) 27} 28 29class CtrlToLsBlockIO extends XSBundle { 30 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 31 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 32 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 33 val redirect = ValidIO(new Redirect) 34} 35 36class CtrlBlock extends XSModule { 37 val io = IO(new Bundle { 38 val frontend = Flipped(new FrontendToBackendIO) 39 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 40 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 41 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 42 val toIntBlock = new CtrlToIntBlockIO 43 val toFpBlock = new CtrlToFpBlockIO 44 val toLsBlock = new CtrlToLsBlockIO 45 val roqio = new Bundle { 46 // to int block 47 val toCSR = new RoqCSRIO 48 val exception = ValidIO(new MicroOp) 49 val isInterrupt = Output(Bool()) 50 // to mem block 51 val commits = Vec(CommitWidth, ValidIO(new RoqCommit)) 52 val roqDeqPtr = Output(new RoqPtr) 53 } 54 val oldestStore = Input(Valid(new RoqPtr)) 55 }) 56 57 val decode = Module(new DecodeStage) 58 val brq = Module(new Brq) 59 val decBuf = Module(new DecodeBuffer) 60 val rename = Module(new Rename) 61 val dispatch = Module(new Dispatch) 62 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 63 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 64 65 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 66 67 val roq = Module(new Roq(roqWbSize)) 68 69 val redirect = Mux( 70 roq.io.redirect.valid, 71 roq.io.redirect, 72 Mux( 73 brq.io.redirect.valid, 74 brq.io.redirect, 75 io.fromLsBlock.replay 76 ) 77 ) 78 79 io.frontend.redirect := redirect 80 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 81 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 82 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 83 84 decode.io.in <> io.frontend.cfVec 85 decode.io.toBrq <> brq.io.enqReqs 86 decode.io.brTags <> brq.io.brTags 87 decode.io.out <> decBuf.io.in 88 89 brq.io.roqRedirect <> roq.io.redirect 90 brq.io.memRedirect <> io.fromLsBlock.replay 91 brq.io.bcommit <> roq.io.bcommit 92 brq.io.enqReqs <> decode.io.toBrq 93 brq.io.exuRedirect <> io.fromIntBlock.exuRedirect 94 95 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 96 decBuf.io.redirect <> redirect 97 decBuf.io.out <> rename.io.in 98 99 rename.io.redirect <> redirect 100 rename.io.roqCommits <> roq.io.commits 101 rename.io.out <> dispatch.io.fromRename 102 103 dispatch.io.redirect <> redirect 104 dispatch.io.toRoq <> roq.io.dp1Req 105 dispatch.io.roqIdxs <> roq.io.roqIdxs 106 dispatch.io.toLsq <> io.toLsBlock.lsqIdxReq 107 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 108 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.oldestStore.valid 109 dispatch.io.dequeueRoqIndex.bits := Mux(io.oldestStore.valid, 110 io.oldestStore.bits, 111 roq.io.commitRoqIndex.bits 112 ) 113 dispatch.io.readIntRf <> io.toIntBlock.readRf 114 dispatch.io.readFpRf <> io.toFpBlock.readRf 115 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 116 intBusyTable.io.allocPregs(i).valid := preg.isInt 117 fpBusyTable.io.allocPregs(i).valid := preg.isFp 118 intBusyTable.io.allocPregs(i).bits := preg.preg 119 fpBusyTable.io.allocPregs(i).bits := preg.preg 120 } 121 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 122 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 123 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 124 125 126 val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe) 127 fpBusyTable.io.flush := flush 128 intBusyTable.io.flush := flush 129 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 130 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen && (wb.bits.uop.ctrl.ldest =/= 0.U) 131 setPhyRegRdy.bits := wb.bits.uop.pdest 132 } 133 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 134 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 135 setPhyRegRdy.bits := wb.bits.uop.pdest 136 } 137 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 138 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 139 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 140 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 141 for(i <- 0 until ReplayWidth){ 142 intBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isInt 143 fpBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isFp 144 intBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg 145 fpBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg 146 } 147 148 roq.io.memRedirect <> io.fromLsBlock.replay 149 roq.io.brqRedirect <> brq.io.redirect 150 roq.io.dp1Req <> dispatch.io.toRoq 151 152 153 roq.io.exeWbResults.take(roqWbSize-1).zip( 154 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 155 ).foreach{ 156 case(x, y) => 157 x.bits := y.bits 158 x.valid := y.valid && !y.bits.redirectValid 159 } 160 roq.io.exeWbResults.last := brq.io.out 161 162 io.toIntBlock.redirect := redirect 163 io.toFpBlock.redirect := redirect 164 io.toLsBlock.redirect := redirect 165 166 // roq to int block 167 io.roqio.toCSR <> roq.io.csr 168 io.roqio.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 169 io.roqio.exception.bits := roq.io.exception 170 io.roqio.isInterrupt := roq.io.redirect.bits.isFlushPipe 171 // roq to mem block 172 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 173 io.roqio.commits := roq.io.commits 174} 175