1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.Rename 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 14 15class CtrlToIntBlockIO extends XSBundle { 16 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 17 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 18 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 19 val redirect = ValidIO(new Redirect) 20} 21 22class CtrlToFpBlockIO extends XSBundle { 23 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 24 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 25 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 26 val redirect = ValidIO(new Redirect) 27} 28 29class CtrlToLsBlockIO extends XSBundle { 30 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 31 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 32 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 33 val redirect = ValidIO(new Redirect) 34} 35 36class CtrlBlock extends XSModule { 37 val io = IO(new Bundle { 38 val frontend = Flipped(new FrontendToBackendIO) 39 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 40 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 41 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 42 val toIntBlock = new CtrlToIntBlockIO 43 val toFpBlock = new CtrlToFpBlockIO 44 val toLsBlock = new CtrlToLsBlockIO 45 val roqio = new Bundle { 46 // to int block 47 val toCSR = new RoqCSRIO 48 val exception = ValidIO(new MicroOp) 49 val isInterrupt = Output(Bool()) 50 // to mem block 51 val commits = Vec(CommitWidth, ValidIO(new RoqCommit)) 52 val roqDeqPtr = Output(new RoqPtr) 53 } 54 val oldestStore = Input(Valid(new RoqPtr)) 55 }) 56 57 val decode = Module(new DecodeStage) 58 val brq = Module(new Brq) 59 val decBuf = Module(new DecodeBuffer) 60 val rename = Module(new Rename) 61 val dispatch = Module(new Dispatch) 62 // TODO: move busyTable to dispatch1 63 // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 64 // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 65 66 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 67 68 val roq = Module(new Roq(roqWbSize)) 69 70 val redirect = Mux( 71 roq.io.redirect.valid, 72 roq.io.redirect, 73 Mux( 74 brq.io.redirect.valid, 75 brq.io.redirect, 76 io.fromLsBlock.replay 77 ) 78 ) 79 80 io.frontend.redirect := redirect 81 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 82 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 83 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 84 85 decode.io.in <> io.frontend.cfVec 86 decode.io.toBrq <> brq.io.enqReqs 87 decode.io.brTags <> brq.io.brTags 88 decode.io.out <> decBuf.io.in 89 90 brq.io.roqRedirect <> roq.io.redirect 91 brq.io.memRedirect <> io.fromLsBlock.replay 92 brq.io.bcommit <> roq.io.bcommit 93 brq.io.enqReqs <> decode.io.toBrq 94 brq.io.exuRedirect <> io.fromIntBlock.exuRedirect 95 96 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 97 decBuf.io.redirect <> redirect 98 decBuf.io.out <> rename.io.in 99 100 rename.io.redirect <> redirect 101 rename.io.roqCommits <> roq.io.commits 102 // they should be moved to busytables 103 rename.io.wbIntResults <> io.fromIntBlock.wbRegs 104 rename.io.wbFpResults <> io.fromFpBlock.wbRegs 105 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 106 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 107 rename.io.intPregRdy <> dispatch.io.intPregRdy 108 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 109 rename.io.replayPregReq <> dispatch.io.replayPregReq 110 rename.io.out <> dispatch.io.fromRename 111 112 dispatch.io.redirect <> redirect 113 dispatch.io.toRoq <> roq.io.dp1Req 114 dispatch.io.roqIdxs <> roq.io.roqIdxs 115 dispatch.io.toLsroq <> io.toLsBlock.lsqIdxReq 116 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 117 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.oldestStore.valid 118 dispatch.io.dequeueRoqIndex.bits := Mux(io.oldestStore.valid, 119 io.oldestStore.bits, 120 roq.io.commitRoqIndex.bits 121 ) 122 dispatch.io.readIntRf <> io.toIntBlock.readRf 123 dispatch.io.readFpRf <> io.toFpBlock.readRf 124 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 125 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 126 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 127 128 129 roq.io.memRedirect <> io.fromLsBlock.replay 130 roq.io.brqRedirect <> brq.io.redirect 131 roq.io.dp1Req <> dispatch.io.toRoq 132 133 134 roq.io.exeWbResults.take(roqWbSize-1).zip( 135 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 136 ).foreach{ 137 case(x, y) => 138 x.bits := y.bits 139 x.valid := y.valid && !y.bits.redirectValid 140 } 141 roq.io.exeWbResults.last := brq.io.out 142 143 io.toIntBlock.redirect := redirect 144 io.toFpBlock.redirect := redirect 145 io.toLsBlock.redirect := redirect 146 147 // roq to int block 148 io.roqio.toCSR <> roq.io.csr 149 io.roqio.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 150 io.roqio.exception.bits := roq.io.exception 151 io.roqio.isInterrupt := roq.io.redirect.bits.isFlushPipe 152 // roq to mem block 153 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 154 io.roqio.commits := roq.io.commits 155} 156