1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.Rename 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 14 15class CtrlToIntBlockIO extends XSBundle { 16 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 17 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 18 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 19 val redirect = ValidIO(new Redirect) 20 val roqToCSR = new RoqCSRIO 21} 22 23class CtrlToFpBlockIO extends XSBundle { 24 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 25 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 26 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 27 val redirect = ValidIO(new Redirect) 28} 29 30class CtrlToLsBlockIO extends XSBundle { 31 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 32 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 33 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 34 val redirect = ValidIO(new Redirect) 35 // from roq: send commits info to lsq 36 val commits = Vec(CommitWidth, ValidIO(new RoqCommit)) 37 // from roq: the newest roqDeqPtr 38 val roqDeqPtr = Input(new RoqPtr) 39} 40 41class CtrlBlock extends XSModule { 42 val io = IO(new Bundle { 43 val frontend = Flipped(new FrontendToBackendIO) 44 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 45 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 46 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 47 val toIntBlock = new CtrlToIntBlockIO 48 val toFpBlock = new CtrlToFpBlockIO 49 val toLsBlock = new CtrlToLsBlockIO 50 }) 51 52 val decode = Module(new DecodeStage) 53 val brq = Module(new Brq) 54 val decBuf = Module(new DecodeBuffer) 55 val rename = Module(new Rename) 56 val dispatch = Module(new Dispatch) 57 // TODO: move busyTable to dispatch1 58 // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 59 // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 60 61 val fpWbSize = exuConfigs.count(_.writeFpRf) 62 val intWbSize = exuConfigs.count(_.writeIntRf) 63 // wb int exu + wb fp exu + ldu / stu + brq 64 val roqWbSize = intWbSize + fpWbSize + exuParameters.LduCnt + exuParameters.StuCnt + 1 65 66 val roq = Module(new Roq(roqWbSize)) 67 68 val redirect = Mux( 69 roq.io.redirect.valid, 70 roq.io.redirect, 71 Mux( 72 brq.io.redirect.valid, 73 brq.io.redirect, 74 io.fromLsBlock.replay 75 ) 76 ) 77 78 io.frontend.redirect := redirect 79 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 80 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 81 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 82 io.frontend.sfence <> io.fromIntBlock.sfence 83 io.frontend.tlbCsrIO <> io.fromIntBlock.tlbCsrIO 84 85 decode.io.in <> io.frontend.cfVec 86 decode.io.toBrq <> brq.io.enqReqs 87 decode.io.brTags <> brq.io.brTags 88 decode.io.out <> decBuf.io.in 89 90 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 91 decBuf.io.redirect <> redirect 92 decBuf.io.out <> rename.io.in 93 94 rename.io.redirect <> redirect 95 rename.io.roqCommits <> roq.io.commits 96 // they should be moved to busytables 97 rename.io.wbIntResults <> io.fromIntBlock.wbIntRegs ++ io.fromFpBlock.wbIntRegs ++ io.fromLsBlock.wbIntRegs 98 rename.io.wbFpResults <> io.fromIntBlock.wbFpRegs ++ io.fromFpBlock.wbFpRegs ++ io.fromLsBlock.wbFpRegs 99 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 100 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 101 rename.io.intPregRdy <> dispatch.io.intPregRdy 102 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 103 rename.io.replayPregReq <> dispatch.io.replayPregReq 104 rename.io.out <> dispatch.io.fromRename 105 106 dispatch.io.redirect <> redirect 107 dispatch.io.toRoq <> roq.io.dp1Req 108 dispatch.io.roqIdxs <> roq.io.roqIdxs 109 dispatch.io.toLsroq <> io.toLsBlock.lsqIdxReq 110 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 111 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.fromLsBlock.oldestStore.valid 112 dispatch.io.dequeueRoqIndex.bits := Mux(io.fromLsBlock.oldestStore.valid, io.fromLsBlock.oldestStore.bits, roq.io.commitRoqIndex.bits) 113 dispatch.io.readIntRf <> io.toIntBlock.readRf 114 dispatch.io.readFpRf <> io.toFpBlock.readRf 115 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 116 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 117 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 118 119 io.toIntBlock.roqToCSR <> roq.io.csr 120 // val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe) 121 // fpBusyTable.flush := flush 122 // intBusyTable.flush := flush 123 // busytable io 124 // maybe update busytable in dispatch1? 125 126} 127