1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.Rename 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.issue.ReservationStationNew 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr} 14import xiangshan.mem._ 15import xiangshan.backend.fu.FunctionUnit._ 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 20 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 21 val redirect = ValidIO(new Redirect) 22} 23 24class CtrlToFpBlockIO extends XSBundle { 25 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 26 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 27 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 28 val redirect = ValidIO(new Redirect) 29} 30 31class CtrlToLsBlockIO extends XSBundle { 32 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 33 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 34 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 35 val redirect = ValidIO(new Redirect) 36} 37 38class CtrlBlock 39( 40 jmpCfg: ExuConfig, 41 aluCfg: ExuConfig, 42 mduCfg: ExuConfig, 43 fmacCfg: ExuConfig, 44 fmiscCfg: ExuConfig, 45 ldCfg: ExuConfig, 46 stCfg: ExuConfig 47) extends XSModule { 48 val io = IO(new Bundle { 49 val frontend = Flipped(new FrontendToBackendIO) 50 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 51 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 52 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 53 val toIntBlock = new CtrlToIntBlockIO 54 val toFpBlock = new CtrlToFpBlockIO 55 val toLsBlock = new CtrlToLsBlockIO 56 }) 57 58 val decode = Module(new DecodeStage) 59 val brq = Module(new Brq) 60 val decBuf = Module(new DecodeBuffer) 61 val rename = Module(new Rename) 62 val dispatch = Module(new Dispatch( 63 jmpCfg, aluCfg, mduCfg, 64 fmacCfg, fmiscCfg, 65 ldCfg, stCfg 66 )) 67 // TODO: move busyTable to dispatch1 68 // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 69 // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 70 val roq = Module(new Roq) 71 72 val fromExeBlock = (io.fromIntBlock, io.fromFpBlock, io.fromLsBlock) 73 val toExeBlock = (io.toIntBlock, io.toFpBlock, io.toLsBlock) 74 75 val redirect = Mux( 76 roq.io.redirect.valid, 77 roq.io.redirect, 78 Mux( 79 brq.io.redirect.valid, 80 brq.io.redirect, 81 io.fromLsBlock.replay 82 ) 83 ) 84 85 io.frontend.redirect := redirect 86 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 87 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 88 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 89 io.frontend.sfence <> io.fromIntBlock.sfence 90 io.frontend.tlbCsrIO <> io.fromIntBlock.tlbCsrIO 91 92 decode.io.in <> io.frontend.cfVec 93 decode.io.toBrq <> brq.io.enqReqs 94 decode.io.brTags <> brq.io.brTags 95 decode.io.out <> decBuf.io.in 96 97 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 98 decBuf.io.redirect <> redirect 99 decBuf.io.out <> rename.io.in 100 101 rename.io.redirect <> redirect 102 rename.io.roqCommits <> roq.io.commits 103 // they should be moved to busytables 104 rename.io.wbIntResults <> io.fromIntBlock.wbIntRegs ++ io.fromFpBlock.wbIntRegs ++ io.fromLsBlock.wbIntRegs 105 rename.io.wbFpResults <> io.fromIntBlock.wbFpRegs ++ io.fromFpBlock.wbFpRegs ++ io.fromLsBlock.wbFpRegs 106 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 107 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 108 rename.io.intPregRdy <> dispatch.io.intPregRdy 109 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 110 rename.io.replayPregReq <> dispatch.io.replayPregReq 111 rename.io.out <> dispatch.io.fromRename 112 113 dispatch.io.redirect <> redirect 114 dispatch.io.toRoq <> roq.io.dp1Req 115 dispatch.io.roqIdxs <> roq.io.roqIdxs 116 dispatch.io.toLsroq <> io.toLsBlock.lsqIdxReq 117 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 118 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.fromLsBlock.oldestStore.valid 119 dispatch.io.dequeueRoqIndex.bits := Mux(io.fromLsBlock.oldestStore.valid, io.fromLsBlock.oldestStore.bits, roq.io.commitRoqIndex.bits) 120 dispatch.io.readIntRf <> io.toIntBlock.readRf 121 dispatch.io.readFpRf <> io.toFpBlock.readRf 122 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 123 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 124 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 125 126 // val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe) 127 // fpBusyTable.flush := flush 128 // intBusyTable.flush := flush 129 // busytable io 130 // maybe update busytable in dispatch1? 131 132} 133