1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.Rename 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.issue.ReservationStationNew 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr} 14import xiangshan.mem._ 15import xiangshan.backend.fu.FunctionUnit._ 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 20 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 21 val redirect = ValidIO(new Redirect) 22} 23 24class CtrlToFpBlockIO extends XSBundle { 25 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 26 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 27 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 28 val redirect = ValidIO(new Redirect) 29} 30 31class CtrlToLsBlockIO extends XSBundle { 32 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 33 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 34 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 35 val redirect = ValidIO(new Redirect) 36 // from roq: send commits info to lsq 37 val commits = Vec(CommitWidth, ValidIO(new RoqCommit)) 38 // from roq: the newest roqDeqPtr 39 val roqDeqPtr = Input(new RoqPtr) 40} 41 42class CtrlBlock 43( 44 jmpCfg: ExuConfig, 45 aluCfg: ExuConfig, 46 mduCfg: ExuConfig, 47 fmacCfg: ExuConfig, 48 fmiscCfg: ExuConfig, 49 ldCfg: ExuConfig, 50 stCfg: ExuConfig 51) extends XSModule { 52 val io = IO(new Bundle { 53 val frontend = Flipped(new FrontendToBackendIO) 54 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 55 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 56 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 57 val toIntBlock = new CtrlToIntBlockIO 58 val toFpBlock = new CtrlToFpBlockIO 59 val toLsBlock = new CtrlToLsBlockIO 60 }) 61 62 val decode = Module(new DecodeStage) 63 val brq = Module(new Brq) 64 val decBuf = Module(new DecodeBuffer) 65 val rename = Module(new Rename) 66 val dispatch = Module(new Dispatch( 67 jmpCfg, aluCfg, mduCfg, 68 fmacCfg, fmiscCfg, 69 ldCfg, stCfg 70 )) 71 // TODO: move busyTable to dispatch1 72 // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 73 // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 74 val roq = Module(new Roq) 75 76 val fromExeBlock = (io.fromIntBlock, io.fromFpBlock, io.fromLsBlock) 77 val toExeBlock = (io.toIntBlock, io.toFpBlock, io.toLsBlock) 78 79 val redirect = Mux( 80 roq.io.redirect.valid, 81 roq.io.redirect, 82 Mux( 83 brq.io.redirect.valid, 84 brq.io.redirect, 85 io.fromLsBlock.replay 86 ) 87 ) 88 89 io.frontend.redirect := redirect 90 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 91 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 92 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 93 io.frontend.sfence <> io.fromIntBlock.sfence 94 io.frontend.tlbCsrIO <> io.fromIntBlock.tlbCsrIO 95 96 decode.io.in <> io.frontend.cfVec 97 decode.io.toBrq <> brq.io.enqReqs 98 decode.io.brTags <> brq.io.brTags 99 decode.io.out <> decBuf.io.in 100 101 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 102 decBuf.io.redirect <> redirect 103 decBuf.io.out <> rename.io.in 104 105 rename.io.redirect <> redirect 106 rename.io.roqCommits <> roq.io.commits 107 // they should be moved to busytables 108 rename.io.wbIntResults <> io.fromIntBlock.wbIntRegs ++ io.fromFpBlock.wbIntRegs ++ io.fromLsBlock.wbIntRegs 109 rename.io.wbFpResults <> io.fromIntBlock.wbFpRegs ++ io.fromFpBlock.wbFpRegs ++ io.fromLsBlock.wbFpRegs 110 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 111 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 112 rename.io.intPregRdy <> dispatch.io.intPregRdy 113 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 114 rename.io.replayPregReq <> dispatch.io.replayPregReq 115 rename.io.out <> dispatch.io.fromRename 116 117 dispatch.io.redirect <> redirect 118 dispatch.io.toRoq <> roq.io.dp1Req 119 dispatch.io.roqIdxs <> roq.io.roqIdxs 120 dispatch.io.toLsroq <> io.toLsBlock.lsqIdxReq 121 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 122 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.fromLsBlock.oldestStore.valid 123 dispatch.io.dequeueRoqIndex.bits := Mux(io.fromLsBlock.oldestStore.valid, io.fromLsBlock.oldestStore.bits, roq.io.commitRoqIndex.bits) 124 dispatch.io.readIntRf <> io.toIntBlock.readRf 125 dispatch.io.readFpRf <> io.toFpBlock.readRf 126 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 127 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 128 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 129 130 // val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe) 131 // fpBusyTable.flush := flush 132 // intBusyTable.flush := flush 133 // busytable io 134 // maybe update busytable in dispatch1? 135 136} 137