1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.{Rename, BusyTable} 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 14 15class CtrlToIntBlockIO extends XSBundle { 16 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 17 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 18 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 19 val redirect = ValidIO(new Redirect) 20} 21 22class CtrlToFpBlockIO extends XSBundle { 23 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 24 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 25 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 26 val redirect = ValidIO(new Redirect) 27} 28 29class CtrlToLsBlockIO extends XSBundle { 30 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 31 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 32 val enqLsq = new Bundle() { 33 val canAccept = Input(Bool()) 34 val req = Vec(RenameWidth, ValidIO(new MicroOp)) 35 val resp = Vec(RenameWidth, Input(new LSIdx)) 36 } 37 val redirect = ValidIO(new Redirect) 38} 39 40class CtrlBlock extends XSModule { 41 val io = IO(new Bundle { 42 val frontend = Flipped(new FrontendToBackendIO) 43 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 44 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 45 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 46 val toIntBlock = new CtrlToIntBlockIO 47 val toFpBlock = new CtrlToFpBlockIO 48 val toLsBlock = new CtrlToLsBlockIO 49 val roqio = new Bundle { 50 // to int block 51 val toCSR = new RoqCSRIO 52 val exception = ValidIO(new MicroOp) 53 val isInterrupt = Output(Bool()) 54 // to mem block 55 val commits = Vec(CommitWidth, ValidIO(new RoqCommit)) 56 val roqDeqPtr = Output(new RoqPtr) 57 } 58 val oldestStore = Input(Valid(new RoqPtr)) 59 }) 60 61 val decode = Module(new DecodeStage) 62 val brq = Module(new Brq) 63 val decBuf = Module(new DecodeBuffer) 64 val rename = Module(new Rename) 65 val dispatch = Module(new Dispatch) 66 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 67 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 68 69 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 70 71 val roq = Module(new Roq(roqWbSize)) 72 73 val redirect = Mux( 74 roq.io.redirect.valid, 75 roq.io.redirect, 76 Mux( 77 brq.io.redirect.valid, 78 brq.io.redirect, 79 io.fromLsBlock.replay 80 ) 81 ) 82 83 io.frontend.redirect := redirect 84 io.frontend.redirect.valid := redirect.valid && !redirect.bits.isReplay 85 io.frontend.outOfOrderBrInfo <> brq.io.outOfOrderBrInfo 86 io.frontend.inOrderBrInfo <> brq.io.inOrderBrInfo 87 88 decode.io.in <> io.frontend.cfVec 89 decode.io.toBrq <> brq.io.enqReqs 90 decode.io.brTags <> brq.io.brTags 91 decode.io.out <> decBuf.io.in 92 93 brq.io.roqRedirect <> roq.io.redirect 94 brq.io.memRedirect <> io.fromLsBlock.replay 95 brq.io.bcommit <> roq.io.bcommit 96 brq.io.enqReqs <> decode.io.toBrq 97 brq.io.exuRedirect <> io.fromIntBlock.exuRedirect 98 99 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 100 decBuf.io.redirect <> redirect 101 decBuf.io.out <> rename.io.in 102 103 rename.io.redirect <> redirect 104 rename.io.roqCommits <> roq.io.commits 105 rename.io.out <> dispatch.io.fromRename 106 rename.io.renameBypass <> dispatch.io.renameBypass 107 108 dispatch.io.redirect <> redirect 109 dispatch.io.enqRoq <> roq.io.enq 110 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 111 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.oldestStore.valid 112 dispatch.io.dequeueRoqIndex.bits := Mux(io.oldestStore.valid, 113 io.oldestStore.bits, 114 roq.io.commitRoqIndex.bits 115 ) 116 dispatch.io.readIntRf <> io.toIntBlock.readRf 117 dispatch.io.readFpRf <> io.toFpBlock.readRf 118 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 119 intBusyTable.io.allocPregs(i).valid := preg.isInt 120 fpBusyTable.io.allocPregs(i).valid := preg.isFp 121 intBusyTable.io.allocPregs(i).bits := preg.preg 122 fpBusyTable.io.allocPregs(i).bits := preg.preg 123 } 124 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 125 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 126 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 127 128 129 val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe) 130 fpBusyTable.io.flush := flush 131 intBusyTable.io.flush := flush 132 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 133 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen && (wb.bits.uop.ctrl.ldest =/= 0.U) 134 setPhyRegRdy.bits := wb.bits.uop.pdest 135 } 136 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 137 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 138 setPhyRegRdy.bits := wb.bits.uop.pdest 139 } 140 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 141 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 142 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 143 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 144 for(i <- 0 until ReplayWidth){ 145 intBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isInt 146 fpBusyTable.io.replayPregs(i).valid := dispatch.io.replayPregReq(i).isFp 147 intBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg 148 fpBusyTable.io.replayPregs(i).bits := dispatch.io.replayPregReq(i).preg 149 } 150 151 roq.io.memRedirect <> io.fromLsBlock.replay 152 roq.io.brqRedirect <> brq.io.redirect 153 roq.io.exeWbResults.take(roqWbSize-1).zip( 154 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 155 ).foreach{ 156 case(x, y) => 157 x.bits := y.bits 158 x.valid := y.valid && !y.bits.redirectValid 159 } 160 roq.io.exeWbResults.last := brq.io.out 161 162 io.toIntBlock.redirect := redirect 163 io.toFpBlock.redirect := redirect 164 io.toLsBlock.redirect := redirect 165 166 // roq to int block 167 io.roqio.toCSR <> roq.io.csr 168 io.roqio.exception.valid := roq.io.redirect.valid && roq.io.redirect.bits.isException 169 io.roqio.exception.bits := roq.io.exception 170 io.roqio.isInterrupt := roq.io.redirect.bits.isFlushPipe 171 // roq to mem block 172 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 173 io.roqio.commits := roq.io.commits 174} 175