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/nrf52832-nimble/rt-thread/libcpu/mips/loongson_1c/
H A Dls1c.h49 #define LS1C_EHCI_IRQ (32+0)
50 #define LS1C_OHCI_IRQ (32+1)
51 #define LS1C_OTG_IRQ (32+2)
52 #define LS1C_MAC_IRQ (32+3)
53 #define LS1C_CAM_IRQ (32+4)
54 #define LS1C_UART4_IRQ (32+5)
55 #define LS1C_UART5_IRQ (32+6)
56 #define LS1C_UART6_IRQ (32+7)
57 #define LS1C_UART7_IRQ (32+8)
58 #define LS1C_UART8_IRQ (32+9)
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/nrf52832-nimble/rt-thread/libcpu/arm/realview-a8-vmm/
H A Dgic.c37 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4)
38 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4)
39 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4)
40 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4)
41 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4)
42 #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4)
43 #define GIC_DIST_ACTIVE_CLEAR(hw_base, n) __REG32((hw_base) + 0x380 + ((n)/32) * 4)
66 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_ack()
80 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_mask()
92 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_clear_pending()
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/nrf52832-nimble/packages/NimBLE-latest/nimble/host/src/
H A Dble_sm_alg.c236 ble_hs_log_flat_buf(u, 32); in ble_sm_alg_f4()
238 ble_hs_log_flat_buf(v, 32); in ble_sm_alg_f4()
252 swap_buf(m, u, 32); in ble_sm_alg_f4()
253 swap_buf(m + 32, v, 32); in ble_sm_alg_f4()
291 uint8_t ws[32]; in ble_sm_alg_f5()
296 ble_sm_alg_log_buf("w", w, 32); in ble_sm_alg_f5()
300 swap_buf(ws, w, 32); in ble_sm_alg_f5()
302 rc = ble_sm_alg_aes_cmac(salt, ws, 32, t); in ble_sm_alg_f5()
363 swap_buf(m + 32, r, 16); in ble_sm_alg_f6()
396 ble_sm_alg_log_buf("u", u, 32); in ble_sm_alg_g2()
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/nrf52832-nimble/rt-thread/libcpu/arm/zynq7000/
H A Dgic.c36 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + (n/32) * 4)
37 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4)
38 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4)
64 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_ack()
78 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_mask()
107 rt_uint32_t mask = 1 << (irq % 32); in arm_gic_umask()
142 _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; in arm_gic_dist_init()
160 for (i = 32; i < _gic_max_irq; i += 16) in arm_gic_dist_init()
164 for (i = 32; i < _gic_max_irq; i += 4) in arm_gic_dist_init()
172 for (i = 0; i < _gic_max_irq; i += 32) in arm_gic_dist_init()
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/nrf52832-nimble/rt-thread/libcpu/mips/x1000/
H A Dx1000.h142 #define BITS_H2L(msb, lsb) ((0xFFFFFFFF >> (32-((msb)-(lsb)+1))) << (lsb))
255 #define RTC_RTCCR (0x00) /* rw, 32, 0x00000081 */
256 #define RTC_RTCSR (0x04) /* rw, 32, 0x???????? */
257 #define RTC_RTCSAR (0x08) /* rw, 32, 0x???????? */
258 #define RTC_RTCGR (0x0c) /* rw, 32, 0x0??????? */
259 #define RTC_HCR (0x20) /* rw, 32, 0x00000000 */
260 #define RTC_HWFCR (0x24) /* rw, 32, 0x0000???0 */
261 #define RTC_HRCR (0x28) /* rw, 32, 0x00000??0 */
262 #define RTC_HWCR (0x2c) /* rw, 32, 0x00000008 */
263 #define RTC_HWRSR (0x30) /* rw, 32, 0x00000000 */
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H A Dx1000_intc.h77 #define IRQ_RTC 32
114 #define __intc_unmask_irq(n) (REG_INTC_IMCR((n)/32) = (1 << ((n)%32)))
115 #define __intc_mask_irq(n) (REG_INTC_IMSR((n)/32) = (1 << ((n)%32)))
116 #define __intc_ack_irq(n) (REG_INTC_IPR((n)/32) = (1 << ((n)%32))) /* A dummy ack, as …
H A Dcpu.c34 .icache_line_size = 32,
37 .dcache_line_size = 32,
57 /* indexed write 32 tlb entry */ in rt_hw_tlb_init()
58 for(i = 0; i < 32; i++) in rt_hw_tlb_init()
78 entryhi += 0x0800000; /* 32MB */ in rt_hw_tlb_init()
/nrf52832-nimble/nordic/nrfx/hal/
H A Dnrf_clock.h79 NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */
81 NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_LFRC, /**< Internal 32 kHz RC oscillator. */
85 NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
87 NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_LFXO, /**< External 32 kHz crystal. */
91 …NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth, /**< Internal 32 kHz synthesizer from HFCLK syst…
95 * External 32 kHz low swing signal. Used only with the LFCLKSRC register.
101 * External 32 kHz full swing signal. Used only with the LFCLKSRC register.
119 …NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscil…
121 …NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_HFXO /**< External 32 MHz crystal oscillator. …
259 * @retval NRF_CLOCK_LFCLK_RC If the internal 32 kHz RC oscillator
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H A Dnrf_i2s.h107 NRF_I2S_MCK_32MDIV2 = (int)I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2, ///< 32 MHz / 2 = 16.0 MHz.
110 … NRF_I2S_MCK_32MDIV3 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3, ///< 32 MHz / 3 = 10.6666667 MHz.
113 NRF_I2S_MCK_32MDIV4 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4, ///< 32 MHz / 4 = 8.0 MHz.
116 NRF_I2S_MCK_32MDIV5 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5, ///< 32 MHz / 5 = 6.4 MHz.
119 … NRF_I2S_MCK_32MDIV6 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6, ///< 32 MHz / 6 = 5.3333333 MHz.
121 NRF_I2S_MCK_32MDIV8 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8, ///< 32 MHz / 8 = 4.0 MHz.
122 NRF_I2S_MCK_32MDIV10 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10, ///< 32 MHz / 10 = 3.2 MHz.
123 … NRF_I2S_MCK_32MDIV11 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11, ///< 32 MHz / 11 = 2.9090909 MHz.
124 … NRF_I2S_MCK_32MDIV15 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15, ///< 32 MHz / 15 = 2.1333333 MHz.
125 NRF_I2S_MCK_32MDIV16 = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16, ///< 32 MHz / 16 = 2.0 MHz.
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/nrf52832-nimble/rt-thread/libcpu/risc-v/k210/
H A Dinterrupt.c53 uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32]; in rt_hw_plic_irq_enable()
55 current |= (uint32_t)1 << (irq_number % 32); in rt_hw_plic_irq_enable()
57 plic->target_enables.target[core_id].enable[irq_number / 32] = current; in rt_hw_plic_irq_enable()
69 uint32_t current = plic->target_enables.target[core_id].enable[irq_number / 32]; in rt_hw_plic_irq_disable()
71 current &= ~((uint32_t)1 << (irq_number % 32)); in rt_hw_plic_irq_disable()
73 plic->target_enables.target[core_id].enable[irq_number / 32] = current; in rt_hw_plic_irq_disable()
88 for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++) in rt_hw_interrupt_init()
122 for (idx = 0; idx < ((PLIC_NUM_SOURCES + 32u) / 32u); idx ++) in rt_hw_scondary_interrupt_init()
/nrf52832-nimble/rt-thread/examples/test/
H A Dmem_test.c56 /**< 32bit test */ in mem_test()
69 printf("32bit test fail @ 0x%08X\r\nsystem halt!!!!!",(uint32_t)p_uint32_t); in mem_test()
74 printf("32bit test pass!!\r\n"); in mem_test()
77 /**< 32bit Loopback test */ in mem_test()
91 printf("32bit Loopback test fail @ 0x%08X", (uint32_t)p_uint32_t); in mem_test()
98 printf("32bit Loopback test pass!!\r\n"); in mem_test()
/nrf52832-nimble/packages/NimBLE-latest/nimble/host/mesh/src/
H A Dcrypto.h81 static inline int bt_mesh_session_key(const u8_t dhkey[32], in bt_mesh_session_key() argument
85 return bt_mesh_k1(dhkey, 32, prov_salt, "prsk", session_key); in bt_mesh_session_key()
88 static inline int bt_mesh_prov_nonce(const u8_t dhkey[32], in bt_mesh_prov_nonce() argument
95 err = bt_mesh_k1(dhkey, 32, prov_salt, "prsn", tmp); in bt_mesh_prov_nonce()
103 static inline int bt_mesh_dev_key(const u8_t dhkey[32], in bt_mesh_dev_key() argument
107 return bt_mesh_k1(dhkey, 32, prov_salt, "prdk", dev_key); in bt_mesh_dev_key()
151 int bt_mesh_prov_conf_key(const u8_t dhkey[32], const u8_t conf_salt[16],
/nrf52832-nimble/rt-thread/libcpu/unicore32/sep6200/
H A Dinterrupt.c64 if(intnum < 32) \
67 *(volatile unsigned long*)SEP6200_VIC_SFT_INT_H |= (1 << (intnum - 32)); \
72 if(intnum < 32) \
75 *(volatile unsigned long*)SEP6200_VIC_SFT_INT_H &= ~(1 << (intnum - 32)); \
80 if(intnum < 32) \
83 *(volatile unsigned long*)SEP6200_VIC_INT_EN_H |= (1 << (intnum - 32)); \
88 if(intnum < 32) \
91 *(volatile unsigned long*)SEP6200_VIC_INT_EN_H &= ~(1 << (intnum - 32)); \
/nrf52832-nimble/nordic/nrfx/mdk/
H A Dnrf52840_peripherals.h70 #define P0_PIN_NUM 32
128 #define TIMER0_MAX_SIZE 32
129 #define TIMER1_MAX_SIZE 32
130 #define TIMER2_MAX_SIZE 32
131 #define TIMER3_MAX_SIZE 32
132 #define TIMER4_MAX_SIZE 32
171 #define SPIM3_MAX_DATARATE 32
H A Dnrf52832_peripherals.h68 #define P0_PIN_NUM 32
126 #define TIMER0_MAX_SIZE 32
127 #define TIMER1_MAX_SIZE 32
128 #define TIMER2_MAX_SIZE 32
129 #define TIMER3_MAX_SIZE 32
130 #define TIMER4_MAX_SIZE 32
/nrf52832-nimble/rt-thread/components/net/uip/uip/
H A Duip_arch.h11 * check sum and 32-bit additions.
67 * Carry out a 32-bit addition.
70 * 32-bit arithmetic, uIP uses an external C function for doing the
71 * required 32-bit additions in the TCP protocol processing. This
75 * \note The 32-bit integer pointed to by the op32 parameter and the
79 * \param op32 A pointer to a 4-byte array representing a 32-bit
/nrf52832-nimble/rt-thread/components/CMSIS/Include/
H A Dcore_cmInstr.h111 /** \brief Reverse byte order (32 bit)
152 /** \brief Rotate Right in unsigned value (32 bit)
206 /** \brief LDR Exclusive (32 bit)
208 This function performs a exclusive LDR command for 32 bit values.
240 /** \brief STR Exclusive (32 bit)
242 This function performs a exclusive STR command for 32 bit values.
265 \param [in] sat Bit position to saturate to (1..32)
397 /** \brief Reverse byte order (32 bit)
453 /** \brief Rotate Right in unsigned value (32 bit)
463 return (op1 >> op2) | (op1 << (32 - op2)); in __ROR()
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/nrf52832-nimble/rt-thread/libcpu/c-sky/common/
H A Dcsi_instr.h112 \brief Reverse byte order (32 bit)
155 \brief Rotate Right in unsigned value (32 bit)
163 return (op1 >> op2) | (op1 << (32U - op2)); in __ROR()
217 \param [in] y Bit position to saturate to [1..32]
271 result = 0xFFFFFFFF >> (32 - sat); in __USAT()
298 result = 0xFFFFFFFF >> (32 - sat); in __IUSAT()
372 \brief LDRT Unprivileged (32 bit)
373 \details Executes a Unprivileged LDRT instruction for 32 bit values.
414 \brief STRT Unprivileged (32 bit)
415 \details Executes a Unprivileged STRT instruction for 32 bit values.
/nrf52832-nimble/nordic/cmsis/include/
H A Dcmsis_armcc.h373 \brief Reverse byte order (32 bit)
411 \brief Rotate Right in unsigned value (32 bit)
495 \brief LDR Exclusive (32 bit)
496 \details Executes a exclusive LDR instruction for 32 bit values.
538 \brief STR Exclusive (32 bit)
539 \details Executes a exclusive STR instruction for 32 bit values.
563 \param [in] sat Bit position to saturate to (1..32)
580 \brief Rotate Right with Extend (32 bit)
614 \brief LDRT Unprivileged (32 bit)
615 \details Executes a Unprivileged LDRT instruction for 32 bit values.
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/nrf52832-nimble/rt-thread/src/
H A Dscheduler.c15 * 2006-09-05 Bernard add 32 priority level support
42 #if RT_THREAD_PRIORITY_MAX > 32
44 rt_uint8_t rt_thread_ready_table[32];
113 else if ((rt_ubase_t)thread->sp <= ((rt_ubase_t)thread->stack_addr + 32)) in _rt_scheduler_stack_check()
132 #if RT_THREAD_PRIORITY_MAX > 32 in _get_highest_priority_thread()
175 #if RT_THREAD_PRIORITY_MAX > 32 in _get_highest_priority_thread()
231 #if RT_THREAD_PRIORITY_MAX > 32 in rt_system_scheduler_init()
240 #if RT_THREAD_PRIORITY_MAX > 32 in rt_system_scheduler_init()
615 #if RT_THREAD_PRIORITY_MAX > 32 in rt_schedule_insert_thread()
629 #if RT_THREAD_PRIORITY_MAX > 32 in rt_schedule_insert_thread()
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/nrf52832-nimble/rt-thread/components/utilities/zmodem/
H A Dzdef.h11 #define ZBIN32 'C' /* binary frame with 32 bit FCS */
12 #define ZBINR32 'D' /* RLE packed Binary frame with 32 bit FCS */
15 #define ZVBIN32 'c' /* binary frame with 32 bit FCS */
16 #define ZVBINR32 'd' /* RLE packed Binary frame with 32 bit FCS */
77 #define CANFC32 0x28 /* receiver can use 32 bit Frame Check */
88 #define ZATTNLEN 32 /* max length of attention string */
127 extern rt_uint8_t Txfcs32; /* TRUE means send binary frames with 32 bit FCS */
132 extern rt_uint8_t Txfcs32; /* TURE means send binary frames with 32 bit FCS */
/nrf52832-nimble/rt-thread/libcpu/mips/common/
H A Dmips_regs.h32 #define MIPS_REG_NR 32
34 rt_uint32_t regs[MIPS_REG_NR]; /* 32 ��ͨ��Ŀ�ļĴ��� */
69 float s[32]; /* even singles, padded */
78 double d[32]; /* even doubles, followed by odd doubles */
125 #define STK_OFFSET_SR ((32 + 0) * SZREG)
126 #define STK_OFFSET_HI ((32 + 1) * SZREG)
127 #define STK_OFFSET_LO ((32 + 2) * SZREG)
128 #define STK_OFFSET_BADVADDR ((32 + 3) * SZREG)
129 #define STK_OFFSET_CAUSE ((32 + 4) * SZREG)
130 #define STK_OFFSET_EPC ((32 + 5) * SZREG)
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H A Dmips_addrspace.h49 * 32-bit MIPS address spaces
108 * Memory segments (32bit kernel mode addresses)
109 * These are the traditional names used in the 32-bit universe.
169 * The R8000 doesn't have the 32-bit compat spaces so we don't define them
174 #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
/nrf52832-nimble/rt-thread/include/
H A Drtdbg.h64 * GREEN 32
97 case DBG_INFO: _DBG_LOG_HDR("I", 32); break; \
113 _DBG_COLOR(32); \
121 _DBG_COLOR(32); \
155 #define LOG_I(fmt, ...) dbg_log_line("I", 32, fmt, ##__VA_ARGS__)
/nrf52832-nimble/nordic/nrfx/templates/nRF52840/
H A Dnrfx_config.h404 // <2147483648=> 32MHz/2
405 // <1342177280=> 32MHz/3
406 // <1073741824=> 32MHz/4
407 // <805306368=> 32MHz/5
408 // <671088640=> 32MHz/6
409 // <536870912=> 32MHz/8
410 // <402653184=> 32MHz/10
411 // <369098752=> 32MHz/11
412 // <285212672=> 32MHz/15
413 // <268435456=> 32MHz/16
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